High precision 12-bit current source
Low noise
Long term stability
Current output from 0 mA to 300 mA
Output fault indication
Low drift
Programmable maximum current
24-lead 4 mm × 4 mm leadframe chip scale package
3-wire serial interface
APPLICATIONS
Tunable laser current source
Programmable high output current source
Automatic test equipment
GENERAL DESCRIPTION
The ADN8810 is a 12-bit current source with an adjustable
full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output
compliance voltage is 2.5 V, even at output currents up to
300 mA.
RESETRESET
4.096V
SERIAL
INTERFACE
ADDRESS
ADN8810
FUNCTIONAL BLOCK DIAGRAM
5V5V3.3V
3
VREF
CS
SCLK
SDI
ADDR0-2
ENCOMP
INDICATION
DVDD AVDD PVDD
ADN8810
FAULT
SB
SB
FAULT
AVSS
Figure 1.
DVSS
IOUT
DGND
FB
R
SN
R
1.6V
R
1.6V
SN
SN
D1
03195-0-001
The device is particularly suited for tunable laser control and
can drive tunable laser front mirror, back mirror, phase, gain,
and amplification sections. A host CPU or microcontroller
controls the operation of the ADN8810 over a 3-wire SPI®
interface. The 3-bit address allows up to eight devices to be
independently controlled while attached to the same SPI bus.
The ADN8810 is guaranteed with ± 4 LSB INL and ± 0.75 LSB
DNL. Noise and digital feedthrough are kept low to ensure low
jitter operation for laser diode applications. Full-scale and
scaled output currents are given in Equations 1 and 2,
respectively.
V
10
REF
(1)
R
SN
⎛
V
Code I
REF
4096k
R
1
SN
⎜
⎜
15
R
⎝
SN
⎞
⎟
(2)
+×××=1.0
⎟
⎠
I×≈
FS
OUT
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DC PERFORMANCE
Resolution N 12 Bit
Relative Accuracy INL ± 4 LSB
Differential Nonlinearity DNL ± 0.75 LSB
Offset 4 8 LSB
Offset Drift
R
= 1.6 Ω; I
SN
= 127 mA
OUT
Gain Error 1 %FS
REFERENCE INPUT
Reference Input Voltage V
3.9 4.096 4.3 V
REF
Input Current 1 µA
Bandwidth BW
2 MHz
REF
ANALOG OUTPUT
Output Current Change vs. Output
Voltage Change
Max Output Current I
Output Compliance Voltage V
∆I
/∆V
OUT
OUT
MAX
–40°C to +85°C; IFS=300 mA 2.0 2.5 V
COMP
V
= 0.7 V to 2.0 V 100 400 ppm/V
OUT
R
= 1.37 Ω
SN1
AC PERFORMANCE
Settling Time
τ
S
3 µs
Bandwidth BW 5 MHz
Current Noise Density @10 kHz iN IFS = 250 mA 7.5
I
I
= 100 mA 3
FS
= 50 mA 1.5
FS
Standby Recovery 6 µs
POWER SUPPLY1
Power Supply Voltage DVDD 3.0 5 5.5 V
AVDD 4.5 5 5.5 V
PVDD 3.0 3.3 5.5 V
Power Supply Rejection Ratio PSRR AVDD = 4.5 V to 5.5 V; * 0.4 5 µA/V
PVDD = 3.0 V to 3.6 V; * 0.4 5 µA/V
Supply Current I
I
I
I
I
DVDD
AVDD
PVDD
AVDD
PVDD
I
= 0 mA, SB = DVDD
O
I
= 0 mA, SB = DVDD
O
I
= 0 mA, SB = DVDD
O
SB
= 0 V
SB
= 0 V
FAU LT D ETEC TION
Load Open Threshold PVDD – 0.6 V
Load Short Threshold AVSS + 0.2 V
FAULT Logic Output VOH DVDD = 5.0 V 4.5 V
VOL DVDD = 5.0 V 0.5 V
LOGIC INPUTS
Input Leakage Current IIL 1 µA
Input Low Voltage VIL DVDD = 3.0 V 0.5 V
DVDD = 5 V 0.8 V
Input High Voltage VIH DVDD = 3.0 V 2.4 V
DVDD = 5 V 4 V
15 ppm/°C
300 mA
nA/√Hz
nA/√Hz
nA/√Hz
11 50 µA
1 2 mA
3 mA
1 mA
0.33 mA
Rev. 0 | Page 3 of 16
ADN8810
Parameter Symbol Condition Min Typ Max Unit
INTERFACE TIMING2
Clock Frequency f
RESET
Pulsewidth
NOTES
1
With respect to AVSS.
2
See Timing Characteristics for timing specifications.
= 20 Ω
* R
SN
12.5 MHz
CLK
t
40 ns
11
Rev. 0 | Page 4 of 16
ADN8810
TIMING CHARACTERISTICS
1, 2
Tabl e 2. Timi n g C h ar a cte r isti cs
Parameter Description Min Typ Max Unit
f
SCLK Frequency 12.5 MHz
CLK
t1 SCLK Cycle Time 80 ns
t2 SCLK Width High 40 ns
t3 SCLK Width Low 40 ns
t4
t5
t6
t7
CS
Low to SCLK High Setup
CS
High to SCLK High Setup
CS
SCLK High to
SCLK High to
Low Hold
CS
High Hold
15 ns
15 ns
35 ns
20 ns
t8 Data Setup 15 ns
t9 Data Hold 2 ns
t10
t11
t12
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (V
CS
High Pulsewidth
RESET
Pulsewidth
CS
High to
RESET
Low Hold
+ VIH)/2.
IL
30 ns
40 ns
30 ns
t
1
SCLK
t
6
t
4
t
3
t
2
t
5
t
7
CS
SDI
RESET
t
10
t
8
t
9
A3*
*ADDRESS BIT A3 MUST BE LOGIC LOW
A2
A1A0D11D10D0
t
12
t
11
03195-0-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 16
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