12-Bit High Output Current Source
FEATURES
High precision 12-bit current source
Low noise
Long term stability
Current output from 0 mA to 300 mA
Output fault indication
Low drift
Programmable maximum current
24-lead 4 mm × 4 mm leadframe chip scale package
3-wire serial interface
APPLICATIONS
Tunable laser current source
Programmable high output current source
Automatic test equipment
GENERAL DESCRIPTION
The ADN8810 is a 12-bit current source with an adjustable
full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output
compliance voltage is 2.5 V, even at output currents up to
300 mA.
RESET RESET
4.096V
SERIAL
INTERFACE
ADDRESS
ADN8810
FUNCTIONAL BLOCK DIAGRAM
5V 5V 3.3V
3
VREF
CS
SCLK
SDI
ADDR0-2
ENCOMP
INDICATION
DVDD AVDD PVDD
ADN8810
FAULT
SB
SB
FAULT
AVSS
Figure 1.
DVSS
IOUT
DGND
FB
R
SN
R
1.6V
R
1.6V
SN
SN
D1
03195-0-001
The device is particularly suited for tunable laser control and
can drive tunable laser front mirror, back mirror, phase, gain,
and amplification sections. A host CPU or microcontroller
controls the operation of the ADN8810 over a 3-wire SPI®
interface. The 3-bit address allows up to eight devices to be
independently controlled while attached to the same SPI bus.
The ADN8810 is guaranteed with ± 4 LSB INL and ± 0.75 LSB
DNL. Noise and digital feedthrough are kept low to ensure low
jitter operation for laser diode applications. Full-scale and
scaled output currents are given in Equations 1 and 2,
respectively.
V
10
REF
(1)
R
SN
⎛
V
Code I
REF
4096 k
R
1
SN
⎜
⎜
15
R
⎝
SN
⎞
⎟
(2)
+×××= 1.0
⎟
⎠
I×≈
FS
OUT
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
ADN8810
TABLE OF CONTENTS
ADN8810–Specifications ................................................................ 3
Serial Data Interface................................................................... 11
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
ADN8810 Terminology ................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description.................................................................. 11
Setting Full-Scale Output Current ........................................... 11
Reference Voltage Source .......................................................... 11
Power Supplies............................................................................ 11
REVISION HISTORY
Revision 0: Initial Version
Standby and Reset Modes ......................................................... 12
Power Dissipation ...................................................................... 12
Using Multiple ADN8810s for Additional Output Current . 12
Adding Dither to the Output Current..................................... 12
Driving Common-Anode Laser Diodes ................................. 13
PC Board Layout Recommendations...................................... 13
Suggested Pad Layout for CP-24 Package ............................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Rev. 0 | Page 2 of 16
ADN8810
ADN8810–SPECIFICATIONS
Table 1. Electrical Characteristics (AVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, TA= 25°C, covering IOUT
from 2% IFS to 100% IFS, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
DC PERFORMANCE
Resolution N 12 Bit
Relative Accuracy INL ± 4 LSB
Differential Nonlinearity DNL ± 0.75 LSB
Offset 4 8 LSB
Offset Drift
R
= 1.6 Ω; I
SN
= 127 mA
OUT
Gain Error 1 %FS
REFERENCE INPUT
Reference Input Voltage V
3.9 4.096 4.3 V
REF
Input Current 1 µA
Bandwidth BW
2 MHz
REF
ANALOG OUTPUT
Output Current Change vs. Output
Voltage Change
Max Output Current I
Output Compliance Voltage V
∆I
/∆V
OUT
OUT
MAX
–40°C to +85°C; IFS=300 mA 2.0 2.5 V
COMP
V
= 0.7 V to 2.0 V 100 400 ppm/V
OUT
R
= 1.37 Ω
SN1
AC PERFORMANCE
Settling Time
τ
S
3 µs
Bandwidth BW 5 MHz
Current Noise Density @10 kHz iN IFS = 250 mA 7.5
I
I
= 100 mA 3
FS
= 50 mA 1.5
FS
Standby Recovery 6 µs
POWER SUPPLY1
Power Supply Voltage DVDD 3.0 5 5.5 V
AVDD 4.5 5 5.5 V
PVDD 3.0 3.3 5.5 V
Power Supply Rejection Ratio PSRR AVDD = 4.5 V to 5.5 V; * 0.4 5 µA/V
PVDD = 3.0 V to 3.6 V; * 0.4 5 µA/V
Supply Current I
I
I
I
I
DVDD
AVDD
PVDD
AVDD
PVDD
I
= 0 mA, SB = DVDD
O
I
= 0 mA, SB = DVDD
O
I
= 0 mA, SB = DVDD
O
SB
= 0 V
SB
= 0 V
FAU LT D ETEC TION
Load Open Threshold PVDD – 0.6 V
Load Short Threshold AVSS + 0.2 V
FAULT Logic Output VOH DVDD = 5.0 V 4.5 V
VOL DVDD = 5.0 V 0.5 V
LOGIC INPUTS
Input Leakage Current IIL 1 µA
Input Low Voltage VIL DVDD = 3.0 V 0.5 V
DVDD = 5 V 0.8 V
Input High Voltage VIH DVDD = 3.0 V 2.4 V
DVDD = 5 V 4 V
15 ppm/°C
300 mA
nA/√Hz
nA/√Hz
nA/√Hz
11 50 µA
1 2 mA
3 mA
1 mA
0.33 mA
Rev. 0 | Page 3 of 16
ADN8810
Parameter Symbol Condition Min Typ Max Unit
INTERFACE TIMING2
Clock Frequency f
RESET
Pulsewidth
NOTES
1
With respect to AVSS.
2
See Timing Characteristics for timing specifications.
= 20 Ω
* R
SN
12.5 MHz
CLK
t
40 ns
11
Rev. 0 | Page 4 of 16
ADN8810
TIMING CHARACTERISTICS
1, 2
Tabl e 2. Timi n g C h ar a cte r isti cs
Parameter Description Min Typ Max Unit
f
SCLK Frequency 12.5 MHz
CLK
t1 SCLK Cycle Time 80 ns
t2 SCLK Width High 40 ns
t3 SCLK Width Low 40 ns
t4
t5
t6
t7
CS
Low to SCLK High Setup
CS
High to SCLK High Setup
CS
SCLK High to
SCLK High to
Low Hold
CS
High Hold
15 ns
15 ns
35 ns
20 ns
t8 Data Setup 15 ns
t9 Data Hold 2 ns
t10
t11
t12
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (V
CS
High Pulsewidth
RESET
Pulsewidth
CS
High to
RESET
Low Hold
+ VIH)/2.
IL
30 ns
40 ns
30 ns
t
1
SCLK
t
6
t
4
t
3
t
2
t
5
t
7
CS
SDI
RESET
t
10
t
8
t
9
A3*
*ADDRESS BIT A3 MUST BE LOGIC LOW
A2
A1 A0 D11 D10 D0
t
12
t
11
03195-0-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 16
ADN8810
ABSOLUTE MAXIMUM RATINGS
Table 3. ADN8810 Absolute Maximum Ratings
Parameter Rating
Supply Voltage 6 V
Input Voltage GND to VS+ 0.3 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range –65°C to +150°C
Operating Temperature Range –40°C to +85°C
Junction Temperature Range CP
Package
Lead Temperature Range
(Soldering 10 sec)
–65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 16
ADN8810
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND
DVDD
RESETCSSCLK
24
23 22 21 20 19
1
ADDR2
RSN
ADDR1
ADDR0
FAULT
NC = NO CONNECT
PIN 1
2
IDENTIFIER
3
FB
4
5
6
ADN8810
TOP VIEW
(Not to Scale)
789101112
SB
IOUT
PVDD
Figure 3. Pin Configuration
Table 4. Pin Function Description
Pin No. Mnemonic Type Description
1 ADDR2 Digital Input Chip Address, Bit 2
2 RSN Analog Input Sense Resistor RS2 Feedback
3 FB Analog Input Sense Resistor RS1 Feedback
4 ADDR1 Digital Input Chip Address, Bit 1
5 ADDR0 Digital Input Chip Address, Bit 0
6 FAULT Digital Output Load Open/Short Indication
7
SB
Digital Input Active Deactivates Output Stage (High Output Impedance State)
8, 11 PVDD Power Power Supply for IOUT (3.3 V Recommended)
9, 10 IOUT Analog Output Current Output
12 ENCOMP Digital Input Connect to AVSS
13 NC No Connection
14 VREF Analog Input Input for High Accuracy External Reference Voltage (ADR292ER)
15 AVDD Power Power Supply for DAC
16 AVSS Ground Connect to Analog Ground or Most Negative Potential in Dual-Supply Applications
17 NC No Connection
18 DVSS Ground Connect to Digital Ground or Most Negative Potential in Dual-Supply Applications
19 SDI Digital Input Serial Data Input
20 SCLK Digital Input Serial Clock Input
21
22
CS
RESET
Digital Input Chip Select; Active Low
Digital Input Asynchronous Reset to Return DAC Output to Code Zero; Active Low
23 DVDD Power Power Supply for Digital Interface
24 DGND Ground Digital Ground
IOUT
PVDD
SDI
18
17
16
15
14
13
ENCOMP
DVSS
NC
AVSS
AVDD
VREF
NC
03195-0-003
Rev. 0 | Page 7 of 16
ADN8810
ADN8810 TERMINOLOGY
Relative Accuracy
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in least significant bits (LSBs), from an
ideal line passing through the endpoints of the DAC transfer
function. Figure 5 shows a typical INL vs. code plot. The
ADN8810 INL is measured from 2% to 100% of the full-scale
(FS) output.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
the measured change and the ideal 1 LSB change between
any two adjacent codes. A specified differential nonlinearity
of ± 1 LSB maximum ensures monotonicity. The ADN8810
is guaranteed monotonic by design. Figure 6 shows a typical
DNL vs. code plot
Offset Error
Offset error, or zero-code error, is an interpolation of the output
voltage at code 0x000 as predicted by the line formed from the
output voltages at code 0
FS). Ideally, the offset error should be 0 V. Offset error occurs
from a combination of the offset voltage of the amplifier and
offset errors in the DAC. It is expressed in LSBs.
Offset Drift
This is a measure of the change in offset error with a change in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the output transfer characteristic from
ideal. The transfer characteristic is the line formed from the
output voltages at code 0
FS). It is expressed as a percent of the full-scale range.
.
x040 (2% FS) and code 0xFFF (100%
x040 (2% FS) and code 0xFFF (100%
Compliance Voltage
The maximum output voltage from the ADN8810 is a function
of output current and supply voltage. Compliance voltage
defines the maximum output voltage at a given current and
supply voltage to guarantee the device operates within its INL,
DNL, and gain error specifications.
Output Current Change vs. Output Voltage Change
This is a measure of the ADN8810 output impedance and is
similar to a load regulation spec in voltage references. For a
given code, the output current changes slightly as output voltage
increases. It is measured as an absolute value in (ppm of fullscale range)/V.
GAIN ERROR
PLUS
OFFSET ERROR
INTERPOLATED
IDEAL
OUTPUT VOLTAGE
OFFSET
ERROR
DAC CODE
Figure 4. Output Transfer Function
ACTUAL
(EXAGGERATED)
0xFFF0x040
03195-0-004
Rev. 0 | Page 8 of 16
ADN8810
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0
INL ERROR (LSB)
–0.2
–0.4
–0.6
–0.8
0 4,500500
1,000 1,500 2,000 2,500 3,000 3,500 4,000
CODE
Figure 5. Typical INL Plot
0.4
0.3
0.2
0.1
0
DNL ERROR (LSB)
–0.1
–0.2
–0.3
0 4,500500
1,000 1,500 2,000 2,500 3,000 3,500 4,000
CODE
Figure 6. Typical DNL Plot
0.20
0.15
0.10
0.05
0
DINL (LSB)
–0.05
–0.10
–0.15
–0.20
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 7. ∆ INL vs. Temperature
03195-0-005
03195-0-006
03195-0-007
0.20
0.15
0.10
0.05
0
∆DNL (LSB)
–0.05
–0.10
–0.15
–0.20
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 8. ∆ DNL vs. Temperature
0.258
RS = 1.6Ω
0.257
0.256
0.255
0.254
0.253
FULL-SCALE OUTPUT (A)
0.252
0.251
0.250
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 9. Full-Scale Output vs. Temperature
20.765
20.760
20.755
20.750
20.745
20.740
20.735
FULL-SCALE OUTPUT (mA)
20.730
20.725
20.720
= 20Ω
R
S
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 10. Full-Scale Output vs. Temperature
03195-0-008
03195-0-009
03195-0-010
Rev. 0 | Page 9 of 16
ADN8810
0.50
CODE = x000
0.45
0.40
0.35
0.30
(mA)
0.25
PVDD
I
0.20
0.15
0.10
0.05
0
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 11. PVDD Supply Current vs. Temperature
12
CODE = x000
10
8
(µA)
6
DVDD
I
4
2
0
–40 85–15
10 35 60
TEMPERATURE (°C)
03195-0-011
03195-0-012
5
10
RS = 1.6Ω
4
10
3
10
2
10
OUTPUT IMPEDANCE (Ω)
1
10
10
10 1M100
1k 10k 100k
FREQUENCY (Hz)
Figure 14. Output Impedance vs. Frequency
0
CODE: x700 TO xFFF
0
CS
0
0
0
0
VOLTAGE (2.7V/DIV)
0
I
OUT
0
00000000000
TIME (1µs/DIV)
5V/DIV
300mA/DIV
03195-0-014
03195-0-015
Figure 12. DVDD Supply Current vs. Temperature
1.5
CODE = x000
1.4
1.3
(mA)
AVDD
I
1.2
1.1
1.0
–40 85–15
10 35 60
TEMPERATURE (°C)
Figure 13. AVDD Supply Current vs. Temperature
03195-0-013
CS
I
OUT
00000000000
Figure 15. Full-Scale Settling Time
CODE: x7FF TO x800
RS = 1.6Ω
TIME (200ns/DIV)
Figure 16. 1 LSB Settling Time
5V/DIV
10mA/DIV
03195-0-016
Rev. 0 | Page 10 of 16
ADN8810
FUNCTIONAL DESCRIPTION
The ADN8810 is a single 12-bit current output D/A converter
with a 3-wire SPI interface. Up to eight devices can be
independently programmed from the same SPI bus.
The full-scale output current is set with two external resistors.
The maximum output current can reach 300 mA. Figure 17
shows the functional block diagram of the ADN8810.
FAULT
AVDD
DVDD
FB ENCMP
• AVDD provides power to the analog front end of the
ADN8810 including the DAC. Use this supply line to
power the external voltage reference. For best performance,
AVDD should be low noise.
• DVDD provides power for the digital circuitry. This
RESET
SB
includes the serial interface logic, the
and
inputs, and the FAULT output. Tie DVDD to the same
supply line used for other digital circuitry. It is not
necessary for DVDD to be low noise.
logic
SB
VREF
CS
SCLK
SDI
BIAS
GEN
CONTROL
LOGIC
DGND ADDR2 ADDR1 ADDR0 DVSSRESET
Figure 17. Functional Block Diagram
FAULT
DETECTION
12-BIT
DAC
DATA LATCH
ADDRESS
DECODER
12-BIT
1.5kΩ
15kΩ
1.5kΩ
PVDD
PVDD
IOUT
IOUT
AVSS
R
SN
SETTING FULL-SCALE OUTPUT CURRENT
Two external resistors set the full-scale output current from the
ADN8810. These resistors are equal in value and are labeled R
SN
in the Functional Block Diagram on the front page. Use 1% or
better tolerance resistors to achieve the most accurate output
current and the highest output impedance.
Equation 1 shows the approximate full-scale output current.
The exact output current is determined by the data register code
as shown in Equation 2. The variable code is an integer from 0
to 4095, representing the full 12-bit range of the ADN8810.
096.4
(1)
RI×≈10
SN
R
Code
1
⎛
⎜
000,1 k
15
R
⎝
SN
SN
⎞
+××= 1.0
(2)
⎟
⎠
I
FS
OUT
REFERENCE VOLTAGE SOURCE
The ADN8810 is designed to operate with a 4.096 V reference
voltage connected to VREF. The output current is directly
proportional to this reference voltage. A low noise precision
reference should be used to achieve the best performance. The
ADR292, ADR392, or REF198 is recommended.
POWER SUPPLIES
There are three principal supply current paths through the
ADN8810:
03195-0-017
• PVDD is the power pin for the output amplifier. It can
operate from as low as 3.0 V to minimize power dissipation
in the ADN8810. For best performance, PVDD should be
low noise.
Current is returned through three pins:
• AVSS is the return path for both AVDD and PVDD. This
pin is connected to the substrate of the die as well as the
slug on the bottom of the LFCSP package. For singlesupply operation, this pin should be connected to a low
noise ground plane.
• DVSS returns current from the digital circuitry powered by
DVDD. Connect DVSS to the same ground line or plane
used for other digital devices in the application.
• DGND is the ground reference for the digital circuitry. In a
single-supply application, connect DGND to DVSS.
For single-supply operation, set AVDD to 5 V, set PVDD from
3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground.
SERIAL DATA INTERFACE
The ADN8810 uses a serial peripheral interface (SPI) with three
CS
input signals: SDI, CLK, and
diagram for these signals.
Data applied to the SDI pin is clocked into the input shift
register on the rising edge of CLK. After all 16 bits of the dataword have been clocked into the input shift register, a logic high
CS
loads the shift register byte into the ADN8810. If more
on
than 16 bits of data are clocked into the shift register before
goes high, bits will be pushed out of the register in first-in first-
out (FIFO) fashion.
The four most significant bits (MSB) of the data byte are
checked against the device’s address. If they match, the next 12
bits of the data byte are loaded into the DAC to set the output
current. The first bit (MSB) of the data byte must be a logic zero,
and the following three bits must correspond to the logic levels
on pins ADDR2, ADDR1, and ADDR0, respectively, for the
. Figure 2 shows the timing
CS
Rev. 0 | Page 11 of 16
ADN8810
DAC to be updated. Up to eight ADN8810 devices with unique
addresses can be driven from the same serial data bus.
Table 5 shows how the 16-bit DATA input word is divided into
an address byte and a data byte. The first four bits in the input
Table 5. Serial Data Input Examples
Address Byte Data Byte
SDI Input A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Ex. 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Ex. 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Ex. 3 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
word correspond to the address. Note that the first bit loaded
(A3) must always be zero. The remaining bits set the 12-bit data
byte for the DAC output. Three example inputs are
demonstrated.
Example 1: This SDI input sets the device with an address of
111 to its minimum output current, 0 A. Connecting the
ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this
address.
Example 2: This input sets the device with an address of 000 to
a current equal to half of the full-scale output.
Example 3: The ADN8810 with an address of 100 is set to full-
scale output.
STANDBY AND RESET MODES
Applying a logic low to the SB pin deactivates the ADN8810 and
puts the output into a high impedance state. The device
continues to draw 1.3 mA of typical supply current in standby.
SB
Once logic high is reasserted on the
pin, the output current
returns to its previous value within 6 µs.
RESET
Applying logic low to
to all zeros, bringing the output current to 0 A. Once
will set the ADN8810 data register
RESET
is
deasserted, the data register can be reloaded. Data cannot be
loaded into the device while it is in Standby or Reset mode.
POWER DISSIPATION
The power dissipation of the ADN8810 is equal to the output
current multiplied by the voltage drop from
output.
DISS
()
OUTOUTOUT
The power dissipated by the ADN8810 will cause a temperature
increase in the device. For this reason, PVDD should be as low
as possible to minimize power dissipation.
While in operation, the ADN8810 die temperature, also known
as junction temperature, must remain below 150°C to prevent
damage. The junction temperature is approximately
J
where T
PTT ×θ+= (4)
DISSJAA
is the ambient temperature in °C, and θJA is the
A
thermal resistance of the package (32°C/W).
PVDD to the
RIVPVDDIP ×−−×= ² (3)
S
Example 4: A 300 mA full-scale output current is required to
drive a laser diode within an 85°C environment. The laser diode
has a 2 V drop and PVDD is 3.3 V.
Using Equation 3, the power dissipation in the ADN8810 is
found to be 267 mW. At T
= 85°C, this makes the junction
A
temperature 93.5°C, which is well below the 150°C limit. Note
that even with PVDD set to 5 V, the junction temperature would
increase to only 110°C.
USING MULTIPLE ADN8810S FOR ADDITIONAL OUTPUT CURRENT
Connect multiple ADN8810 devices in parallel to increase the
available output current. Each device can deliver up to 300 mA
of current. To program all parallel devices simultaneously, set all
device addresses to the same address byte and drive all
CS
, SDI,
and CLK from the same serial data interface bus. The circuit in
Figure 18 uses two ADN8810 devices and delivers 600 mA to
the pump laser.
CS
SERIAL
INTERFACE
(FROM µC
OR DSP)
Figure 18. Using Multiple Devices for Additional Output Current
SCLK
SDI
ADDR2
CS
SCLK
SDI
ADDR2
ADN8810
ADDR1
ADN8810
ADDR1
FB
IOUT
R
ADDR0
FB
IOUT
R
ADDR0
R
S
1.37Ω
R
S
1.37Ω
SN
R
S
1.37Ω
R
S
1.37Ω
SN
D1
600mA
I
LD
ADDING DITHER TO THE OUTPUT CURRENT
Some tunable laser applications require the laser diode bias
current to be modulated or dithered. This is accomplished by
dithering the V
demonstrates one method.
voltage input to the ADN8810. Figure 19
REF
03195-0-018
Rev. 0 | Page 12 of 16
ADN8810
R2
1.62kΩ
5V
AD8605
TO V
REF
03195-0-019
DITHER
C
1µF
4.096V
R1
1.62kΩ
Figure 19. Adding Dither to the Reference Voltage
Set the gain of the dither by adjusting the ratio of R2 to R1.
Increase C to lower the cutoff frequency of the high-pass filter
created by C and R1. The cutoff frequency of Figure 19 is
approximately 10 Hz.
The AD8605 is recommended as a low offset, rail-to-rail input
amplifier for this circuit.
DRIVING COMMON-ANODE LASER DIODES
The ADN8810 can power common-anode laser diodes. These
are laser diodes whose anodes are fixed to the laser module
case. The module case is typically tied to either VDD or ground.
For common-anode-to-ground applications, a negative 5 V
supply must be provided.
In Figure 20, R
I
sets up the diode current by the equation
S
⎛
⎜
+×=
1.1096.4
⎜
S
⎝
⎞
11
Code
⎟
×
⎟
kR
⎠
(5)
40965.16
pins. Figure shows a simple method to level shift a standard
TTL or CMOS (0 V to 5 V) signal down using external FETs.
5V
ADR292
3
VREF
RESET
CS
SCLK
SDI
ADDR0-2
SB
ADN8810
5V
VOUTVIN
GND
C
M
S
T
T
L
/
L
O
O
L
S
E
V
L
E
C
I
G
PVDDAVDDDVDDENCOMP
IOUT
R
DGNDDVSSAVSS
NOTE: LEAVE FB WITH NO CONNECTION
Figure 20. Driving Common-Anode-to-VDD Laser Diodes
–5V
O
L
ADR292
GND
–5V
–
5
L
C
I
G
3
VREF
RESET
CS
SCLK
SDI
ADDR0-2
ADN8810
VOUTVIN
0
V
T
O
E
V
L
S
E
PVDDAVDDDVDDENCOMP
IOUT
R
DGNDDVSSAVSSSB
FB NC
SN
FB NC
SN
5V
D1
I = 300mA
@ CODE 0x7F
FDC633N
OR EQUIV
R
S
6.81Ω
D1
I = 300mA
@ CODE 0x7F
FDC633N
OR EQUIV
R
S
6.81Ω
03195-0-020
where Code is an integer value from 0 to 4,095. Using the values
in Figure 20, the diode current is 300.7 mA at a code value of
2,045 (0
x7FF), or one-half full-scale. This effectively provides
11-bit current control from 0 mA to 300 mA of diode current.
The maximum output current of this configuration is limited by
the compliance voltage at the IOUT pin of the ADN8810. The
voltage at IOUT cannot exceed 1 V below PVDD, in this case
4 V. The IOUT voltage is equal to the voltage drop across R
plus
S
the gate-to-source voltage of the external FET. For this reason,
select a FET with a low threshold voltage.
In addition, the voltage across the R
resistor cannot exceed the
S
voltage at the cathode of the laser diode. Given a forward laser
diode voltage drop of 2 V in Figure 20, the voltage at the R
(I
× R
) cannot exceed 3 V. This sets an upper limit to the value
S
SN
pin
of Code in Equation 5.
Although the configuration for anode-to-ground diodes is
similar, the supply voltages must be shifted down to 0 V and
–5 V, as shown in Figure. The AVDD, DVDD, and PVDD pins
are connected to ground with AVSS connected to –5 V. The
4.096 V reference must also be referred to the –5 V supply
voltage. The diode current is still determined by Equation 5.
All logic levels must be shifted down to 0 V and –5 V levels as
well. This includes
RESET
, CS, SCLK, SDI, SB, and all ADDR
–5V
NOTE: LEAVE FB WITH NO CONNECTION
–5V
Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a Negative
Supply
+3V
TTL/CMOS
LEVEL
10kΩ
–5V
NDC7003P
OR EQUIV
100kΩ
NDC7002N
OR EQUIV
–5V
TO:
RESET
CS
SCLK
SDI
03195-0-021
Figure 22. Level Shifting TTL/CMOS Logic
PC BOARD LAYOUT RECOMMENDATIONS
Although they can be driven from the same power supply
voltage, keep DVDD and AVDD current paths separate on the
PC board to maintain the highest accuracy; likewise for AVSS
and DGND. Tie common potentials together at a single point
located near the power regulator. This technique is known as
star grounding and is shown in Figure. This method reduces
digital crosstalk into the laser diode or load.
03195-0-021
Rev. 0 | Page 13 of 16
ADN8810
TO OTHER 5V
DIGITAL LOGIC
LOGIC GROUND
RETURN
Figure 23. Star Supply and Ground Technique
POWER SUPPLY
5V
DVDD PVDD DVSS
3V GND
AVDD AVSS
DGND
ADN8810
IOUT
LOAD
LOAD
GND
03195-0-023
SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE
shows the dimensions for the PC board pad layout for the
ADN8810. The package is a 4 mm × 4 mm, 24-lead LFCSP. The
metallic slug underneath the package should be soldered to a
copper pad connected to AVSS, the lowest supply voltage to the
ADN8810. For single-supply applications, this is ground. Use
multiple vias to this pad to improve the thermal dissipation of
the package.
0.027
(0.69)
To improve thermal dissipation, the slug on the bottom of the
LFCSP package should be soldered to the PC board with
multiple vias into a low noise ground plane. Connecting these
vias to a copper area on the bottom side of the board will
further improve thermal dissipation.
Use identical trace lengths for the two output sense resistors.
These lengths are shown as X and Y in Figure 24. Differences in
trace lengths cause differences in parasitic series resistance.
Because the sense resistors can be as low as 1.37 Ω, small
parasitic differences can lower both the output current accuracy
and the output impedance. Application Note AN-619 shows a
good layout for these traces.
ADN8810
FB
IOUT
R
R
R
SN
SN
Y
X
SN
TO LOAD
03195-0-024
Figure 24. Use Identical Trace Lengths for Sense Resistors
0.004
(0.10)
0.172
(4.36)
0.109
(2.78)
DIMENSIONS ARE SHOWN
IN INCHES AND (MM).
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
0.106
(2.68)
Figure 25. Suggested PC Board Layout for CP-24 Pad Landing
0.011
(0.28)
0.020
(0.50)
PACKAGE
OUTLINE
03195-0-025
Rev. 0 | Page 14 of 16
ADN8810
OUTLINE DIMENSIONS
0.08
0.60 MAX
19
18
BOTTOM
13
12
VIEW
24
7
1
6
2.50 REF
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
0.25MIN
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
12° MAX
4.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65TYP
COMPLIANT TOJEDEC STANDARDSMO-220-VGGD-2
0.30
0.23
0.18
3.75
BSC SQ
0.20 REF
0.60 MAX
0.05 MAX
0.02 NOM
0.50
BSC
0.50
0.40
0.30
COPLANARITY
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN8810ACP –40°C to +85°C 24-Lead LFCSP CP-24
ADN8810ACP- REEL7 –40°C to +85°C 24-Lead LFCSP CP-24
ADN8810-EVAL Evaluation Board
Rev. 0 | Page 15 of 16
ADN8810
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03195-0-1/04(0)
Rev. 0 | Page 16 of 16
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