ANALOG DEVICES ADN8102 Service Manual

3.75 Gbps Quad Bidirectional

q

FEATURES

Optimized for dc to 3.75 Gbps data Programmable input equalization

Up to 22 dB boost at 1.875 GHz Compensates up to 30 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps

Programmable output pre-emphasis/de-emphasis

Up to 12 dB boost at 1.875 GHz (3.75 Gbps) Compensates up to 15 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps Flexible 1.8 V to 3.3 V core supply Per lane P/N pair inversion for routing ease Low power: 125 mW/channel up to 3.75 Gbps DC- or ac-coupled differential CML inputs Programmable CML output levels 50 Ω on-chip termination Loss-of-signal detection Temperature range operation: −40°C to +85°C Supports 8b10b, scrambled, or uncoded NRZ data

2

I

C control interface

64-lead LFCSP (QFN) package

APPLICATIONS

10GBase-CX4 HiGig™ InfiniBand® 1×, 2× Fibre Channel XAUI™ Gigabit Ethernet over backplane or cable CPRI™ 50 Ω cables

CX4 E

ualizer

ADN8102

FUNCTIONAL BLOCK DIAGRAM

LOS_B

RECEIVE

EQUALIZ ATION

Ix_B[3:0]

Ox_A[3:0]

ADDR[1:0]

SCL

SDA

RESET

LB

EQ

TRANSMIT

PRE-EMPHASIS

PE

GENERAL DESCRIPTION

The ADN8102 is a quad, bidirectional, CX4 cable/backplane equalizer with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 3.75 Gbps.

The receive inputs provide programmable equalization to compensate for up to 30 meters of CX4 cable (24 AWG) or 40 inches of FR4, and programmable pre-emphasis to compensate for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4 at 3.75 Gbps. Each channel also provides programmable loss-ofsignal detection and loopback capability for system testing and debugging.

The ADN8102 is controlled through toggle pins, an I interface that provides more flexible control, or a combination of both. Every channel implements an asynchronous path supporting dc to 3.75 Gbps NRZ data, fully independent of other channels. The ADN8102 has low latency and very low channel-to-channel skew.

The main application for the ADN8102 is to support switching in chassis-to-chassis applications over CX4 or InfiniBand cables.

The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP (QFN) package and operates from −40°C to +85°C.

ADN8102

2:1

CONTROL LO GIC

Figure 1.

TRANSMIT

PRE-EMPHASIS

2:1

RECEIVE

EQUALIZ ATION

PE

EQ

Ox_B[3:0]

LOS_A

Ix_A[3:0]

EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB

2

C® control

07060-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADN8102

REVISION HISTORY

10/10—Rev. A to Rev. B

Changes to Power Supply/Supply Current Parameter, Table 1 ... 4 Added t

Renumbered Sequentially ................................................................ 5

Added Junction Temperature Parameter, Table 3 ........................ 6

Changes to Introduction Section .................................................. 16

Added Table 5; Renumbered Sequentially .................................. 16

Changes to Equalization Settings Section ................................... 17

Added Table 7 and Advanced Equalization Settings Section ... 17

Changes to Table 8 .......................................................................... 18

Added Table 12 ............................................................................... 20

Changes to Loopback Section and Changes to Table 13 ........... 20

Added Table 14 ............................................................................... 21

Changes to Table 15 ........................................................................ 21

Changes to Table 17 ........................................................................ 22

Deleted High Current Setting and Output Level Shift

Section .............................................................................................. 23

Deleted Table 14; Renumbered Sequentially .............................. 24

Changes to Table 18 ........................................................................ 24

Added Table 19 ............................................................................... 24

Deleted Table 15 .............................................................................. 25

Added Applications Information Section and Output

Compliance Section ....................................................................... 27

Parameter and Note 1, Table 2 and Figure 3;

RESET

Moved TxHeadroom and Figure 44 ............................................. 27

Changes to TxHeadroom and Figure 44 ..................................... 27

Added Table 20 ............................................................................... 27

Added Table 21 ............................................................................... 28

Deleted Transmission Lines Section and Soldering Guidelines

for Chip Scale Package Section ..................................................... 28

Changes to Printed Circuit Board (PCB) Layout Guidelines

Section .............................................................................................. 29

Added Figure 45, Supply Sequencing Section, Thermal Paddle

Design Section, and Figure 46 ...................................................... 29

Added Stencil Design for the Thermal Paddle, Figure 47, and

Figure 48 .......................................................................................... 30

8/08—Rev. 0 to Rev. A

Changes to Features Section ............................................................ 1

Changes to Loss of Signal/Signal Detect Section ....................... 18

Added Recommended LOS Settings Section .............................. 18

Deleted Figure 39; Renumbered Sequentially ............................ 18

Exposed Paddle Notation Added to Outline Dimensions ........ 31

5/08—Revision 0: Initial Version

Rev. B | Page 2 of 36

ADN8102

SPECIFICATIONS

VCC = 1.8 V, VEE = 0 V, V T

= 25°C, unless otherwise noted.

A

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Data Rate/Channel (NRZ) 3.75 Gbps

Deterministic Jitter Data rate < 3.75 Gbps; BER = 1 × 10

Random Jitter VCC = 1.8 V 1.5 ps rms

Residual Deterministic Jitter

With Input Equalization Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 0.20 UI Data rate < 3.25 Gbps; 0 meters to 30 meters CX4 0.19 UI Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 0.24 UI Data rate < 3.75 Gbps; 0 meters to 30 meters CX4 0.21 UI

With Output Pre-Emphasis Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 0.13 UI Data rate < 3.25 Gbps; 0 meters to 15 meters CX4 0.37 UI Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 0.14 UI Data rate < 3.75 Gbps; 0 meters to 15 meters CX4 0.41 UI Output Rise/Fall Time 20% to 80% 75 ps Propagation Delay 1 ns Channel-to-Channel Skew 50 ps

OUTPUT PRE-EMPHASIS

Equalization Method 1-tap programmable pre-emphasis Maximum Boost 800 mV p-p output swing 6 dB 200 mV p-p output swing 12 dB Pre-Emphasis Tap Range Minimum 2 mA Maximum 12 mA

INPUT EQUALIZATION

Minimum Boost EQBY = 1 1.5 dB Maximum Boost Maximum boost occurs at 1.875 GHz 22 dB Number of Equalization Settings 8 Gain Step Size 2.5 dB

INPUT CHARACTERISTICS

Input Voltage Swing Differential, V

Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.4 V p-p Single-ended absolute voltage level, VH maximum VCC + 0.5 V p-p Input Resistance Single-ended 45 50 55 Ω Input Return Loss Measured at 2.5 GHz 5 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing DC, differential, PE = 0, default, VCC = 1.8 V 635 740 870

DC, differential, PE = 0, default, VCC = 3.3 V 800

DC, differential, PE = 0, minimum output level,2 VCC = 1.8 V 100

DC, differential, PE = 0, minimum output level,2 VCC = 3.3 V 100

DC, differential, PE = 0, maximum output level,2 VCC = 1.8 V 1300

DC, differential, PE = 0, maximum output level,2 VCC = 3.3 V 1800

TTI

= V

= VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, 3.75 Gbps, PRBS 27 − 1,

TTO

−12

33 ps p-p

1

= VCC − 0.6 V 300 2000

ICM

mV pp

Rev. B | Page 3 of 36

ADN8102

Parameter Test Conditions/Comments Min Typ Max Unit

Output Voltage Range

Single-ended absolute voltage level, TxHeadroom = 0;

minimum

V

L

Single-ended absolute voltage level, TxHeadroom = 0;

V

VH maximum Single-ended absolute voltage level, TxHeadroom = 1;

minimum

V

L

Single-ended absolute voltage level, TxHeadroom = 1;

maximum

V

H

V

Output Current Minimum output current per channel 2 mA Maximum output current per channel, VCC = 1.8 V 21 mA Output Resistance Single-ended 43 50 57 Ω Output Return Loss Measured at 2.5 GHz 5 dB

LOS CHARACTERISTICS

Assert Level IN_A/IN_B LOS threshold = 0x0C 20 mV diff Deassert Level IN_A/IN_B LOS hysteresis = 0x0D 225 mV diff

POWER SUPPLY

Operating Range

VCC V DVCC V V

(VEE + 0.4 V + 0.5 × VID) < V

TTI

V

(VCC − 1.1 V + 0.5 × VOD) < V

TTO

= 0 V 1.7 1.8 3.6 V

EE

= 0 V, DVCC ≤ (VCC + 1.3 V) 3.0 3.3 3.6 V

EE

< (VCC + 0.5 V) VEE + 0.4 1.8 3.6 V

TTI

< (VCC + 0.5 V) VCC − 1.1 1.8 3.6 V

TTO

Supply Current

I

V

TTO

= 1.8 V, all outputs enabled 63 69 mA

TTO

ICC VCC = 1.8 V, all outputs enabled 460 565 mA

LOGIC CHARACTERISTICS

Input High, VIH DVCC = 3.3 V 2.5 V Input Low, VIL 1.0 V Output High, VOH 2.5 V Output Low, VOL 1.0 V

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C θJA 22 °C/W

1

V

is the input common-mode voltage.

ICM

2

Programmable via I2C.

− 1.1 V

CC

+ 0.6 V

CC

− 1.2 V

CC

+ 0.6 V

CC

Rev. B | Page 4 of 36

ADN8102

TIMING SPECIFICATIONS

Table 2. I2C Timing Parameters

Parameter Min Max Unit Description

f

0 400 kHz SCL clock frequency

SCL

t

0.6 Not applicable μs Hold time for a start condition

HD:STA

t

0.6 Not applicable μs Setup time for a repeated start condition

SU:STA

t

1.3 Not applicable μs Low period of the SCL clock

LOW

t

0.6 Not applicable μs High period of the SCL clock

HIGH

t

0 Not applicable μs Data hold time

HD:DAT

t

10 Not applicable ns Data setup time

SU:DAT

tR 1 300 ns Rise time for both SDA and SCL tF 1 300 ns Fall time for both SDA and SCL t

0.6 Not applicable μs Setup time for a stop condition

SU:STO

t

1 Not applicable ns Bus free time between a stop and a start condition

BUF

CIO 5 7 pF Capacitance for each I/O pin t

10 Not applicable ns Reset pulse width1

RESET

1

Reset pulse width is defined as the time

SDA

RESET

is held below the logic low threshold (VIL) listed in Table 1 while the DVCC supply is within the operating range in Table 1.

t

HD:DAT

SU:DAT

t

R

t

HIGH

t

F

Figure 2. I

t

SU:STA

2

C Timing Diagram

t

HD:STA

t

SU:STO

t

R

t

BUF

SPSrS

07060-010

SCL

t

F

t

LOW

t

HD:STA

4.0

DVCC MAX LIMIT

3.5

DVCC MIN LIMIT

3.0

2.5 DVCC (V)

2.0

VOLTAGE (V)

1.5

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 3. Reset Timing Diagram

RESET

TIME (ns)

t

RESET

07060-103

Rev. B | Page 5 of 36

ADN8102

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VCC to VEE 3.7 V V

V

TTI

V

TTO

Internal Power Dissipation 4.26 W Differential Input Voltage 2.0 V Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range −65°C to +125°C Lead Temperature 300°C Junction Temperature 125°C

+ 0.6 V

CC

+ 0.6 V

CC

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 6 of 36

ADN8102

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PE_A1

PE_A0

ENA

OP_A0

ON_A0

VCC

OP_A1

ON_A1

VTTO

OP_A2

ON_A2

VEE

OP_A3

ON_A3

ADDR1

646362616059585756555453525150

ADDR0

49

RESET LOS_

IN_A0 IP_A0

VCC IN_A1 IP_A1

VTTI IN_A2 IP_A2

VEE IN_A3 IP_A3 DVCC

EQ_A1 EQ_A0

PIN 1

1

INDICATO R

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

171819202122232425262728293031

VEE

NOTES

1. EXPOSE D PAD MUST BE CONNECT ED TO VEE.

LB

OP_B0

ON_B0

ADN8102

TOP VIEW

(Not to Scale)

VCC

VTTO

OP_B1

ON_B1

VEE

OP_B2

OP_B3

ON_B2

ON_B3

ENB

48

SCL

47

SDA

46

LOS_B

45

IP_B0

44

IN_B0

43

VCC

42

IP_B1

41

IN_B1

40

VTTI

39

IP_B2

38

IN_B2

37

VEE

36

IP_B3

35

IN_B3

34

EQ_B1

33

EQ_B0

32

PE_B1

PE_B0

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 2

RESET LOS_A

Control Reset Input, Active Low

Digital I/O Port A Loss of Signal Status, Active Low 3 IN_A0 I/O High Speed Input Complement 4 IP_A0 I/O High Speed Input 5 VCC Power Positive Supply 6 IN_A1 I/O High Speed Input Complement 7 IP_A1 I/O High Speed Input 8 VTTI Power Input Termination Supply 9 IN_A2 I/O High Speed Input Complement 10 IP_A2 I/O High Speed Input 11 VEE Power Negative Supply 12 IN_A3 I/O High Speed Input Complement 13 IP_A3 I/O High Speed Input 14 DVCC Power Digital Power Supply 15 EQ_A1 Control Port A Input Equalization MSB 16 EQ_A0 Control Port A Input Equalization LSB 17 VEE Power Negative Supply 18 LB Control Loopback Control 19 ON_B0 I/O High Speed Output Complement 20 OP_B0 I/O High Speed Output 21 VCC Power Positive Supply 22 ON_B1 I/O High Speed Output Complement 23 OP_B1 I/O High Speed Output 24 VTTO Power Output Termination Supply 25 ON_B2 I/O High Speed Output Complement 26 OP_B2 I/O High Speed Output 27 VEE Power Negative Supply

Rev. B | Page 7 of 36

7060-002

ADN8102

Pin No. Mnemonic Type Description

28 ON_B3 I/O High Speed Output Complement 29 OP_B3 I/O High Speed Output 30 ENB Control Port B Enable 31 PE_B1 Control Port B Output Pre-Emphasis MSB 32 PE_B0 Control Port B Output Pre-Emphasis LSB 33 EQ_B0 Control Port B Input Equalization LSB 34 EQ_B1 Control Port B Input Equalization MSB 35 IN_B3 I/O High Speed Input Complement 36 IP_B3 I/O High Speed Input 37 VEE Power Negative Supply 38 IN_B2 I/O High Speed Input Complement 39 IP_B2 I/O High Speed Input 40 VTTI Power Input Termination Supply 41 IN_B1 I/O High Speed Input Complement 42 IP_B1 I/O High Speed Input 43 VCC Power Positive Supply 44 IN_B0 I/O High Speed Input Complement 45 IP_B0 I/O High Speed Input 46 47 SDA Control I2C Control Interface Data Input/Output 48 SCL Control I2C Control Interface Clock Input 49 ADDR0 Control I2C Control Interface Address LSB 50 ADDR1 Control I2C Control Interface Address MSB 51 ON_A3 I/O High Speed Output Complement 52 OP_A3 I/O High Speed Output 53 VEE Power Negative Supply 54 ON_A2 I/O High Speed Output Complement 55 OP_A2 I/O High Speed Output 56 VTTO Power Output Termination Supply 57 ON_A1 I/O High Speed Output Complement 58 OP_A1 I/O High Speed Output 59 VCC Power Positive Supply 60 ON_A0 I/O High Speed Output Complement 61 OP_A0 I/O High Speed Output 62 ENA Control Port A Enable 63 PE_A0 Control Port A Output Pre-Emphasis LSB 64 PE_A1 Control Port A Output Pre-Emphasis MSB EP EPAD Power EPAD Must Be Connected to VEE

LOS_B

Digital I/O Port B Loss of Signal Status, Active Low

Rev. B | Page 8 of 36

ADN8102

V

TYPICAL PERFORMANCE CHARACTERISTICS

DATA OUT

PATTERN

GENERATOR

2 2

INPUT PIN

ADN8102

AC-COUPL ED EVALUATION

OUTPUT

BOARD

50Ω CABLES

Figure 5. Standard Test Circuit (No Channel)

50Ω CABLES

2 2

50Ω

TP2TP1

OSCILLOSCOPE

HIGH SPEED

SAMPLING

07060-011

200mV/DI

50ps/DIV

07060-012

200mV/DI

50ps/DIV

Figure 6. 3.25 Gbps Input Eye (TP1 from Figure 5) Figure 8. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 5)

200mV/DI

50ps/DIV

07060-013

200mV/DI

50ps/DIV

Figure 7. 3.75 Gbps Input Eye (TP1 from Figure 5) Figure 9. 3.75 Gbps Output Eye, No Channel (TP2 from Figure 5)

07060-014

07060-015

Rev. B | Page 9 of 36

ADN8102

V

50Ω CABLES

DATA OUT

PATTERN

200mV/DI

GENERATOR

2 2

FR4 TEST BACKPLANE

DIFFERENTIAL STRIPLINE TRACES

TP1

8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT

TRACE LENGT HS = 40''

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

ADN8102

AC-COUPLED

EVALUATION

BOARD

2 2

50Ω CABLES

50Ω

HIGH SPEED

TP3

SAMPLING

OSCILLOSCOPE

REFERENCE EYE DI AGRAM AT TP1

50ps/DIV

Figure 10. Input Equalization Test Circuit, FR4

200mV/DI

50ps/DIV

Figu re 11. 3. 25 Gbps I nput Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10)

07060-017

200mV/DI

50ps/DIV

07060-019

Figure 13. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 10)

07060-016

200mV/DI

50ps/DIV

07060-018

Figu re 12. 3.75 Gb ps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10)

200mV/DI

50ps/DIV

07060-020

Figure 14. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 10)

Rev. B | Page 10 of 36

ADN8102

V

50Ω CABLES

DATA OUT

PATTERN

200mV/DI

GENERATOR

2 2

30m CX4 CABLE

TP1

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

ADN8102

AC-COUPLED

EVALUATION

BOARD

2 2

50Ω CABLES

50Ω

HIGH SPEED

TP3

SAMPLING

OSCILLOSCOPE

REFERENCE EYE DI AGRAM AT TP1

50ps/DIV

Figure 15. Input Equalization Test Circuit, CX4

200mV/DI

50ps/DIV

Figure 16. 3.25 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15)

07060-021

200mV/DI

07060-022

50ps/DIV

07060-024

Figure 18. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting

(TP3 from Figure 15)

200mV/DI

50ps/DIV

07060-023

Figure 17. 3.75 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15)

200mV/DI

50ps/DIV

07060-025

Figure 19. 3.75 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting

(TP3 from Figure 15)

Rev. B | Page 11 of 36

ANALOG DEVICES ADN8102 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS