ANALOG DEVICES ADN4694E Service Manual
3.3 V, 100 Mbps, Half- and Full-Duplex,
V
V
Data Sheet
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 100 Mbps (50 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV
Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4690E/ADN4694E) and 14-lead
(ADN4692E/ADN4695E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
High Speed M-LVDS Transceivers
ADN4690E/ADN4692E/ADN4694E/ADN4695E
FUNCTIONAL BLOCK DIAGRAMS
CC
ADN4690E/
ADN4694E
RO R
RE
DE
D
DI
GND
Figure 1.
CC
ADN4692E/
ADN4695E
RO R
RE
DE
D
DI
GND
Figure 2.
A
B
10471-001
A
B
Z
Y
10471-102
GENERAL DESCRIPTION
The ADN4690E/ADN4692E/ADN4694E/ADN4695E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up
to 100 Mbps (50 MHz). Slew rate control is implemented on the
driver outputs. The receivers detect the bus state with a differential
input of as little as 50 mV over a common-mode voltage range of
−1 V to +3.4 V. ESD protection of up to ±15 kV is implemented
on the bus pins. The parts adhere to the TIA/EIA-899 standard for
M-LVDS and complement TIA/EIA-644 LVDS devices with
additional multipoint capabilities.
The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4694E/ADN4695E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the
inputs are open (open-circuit fail-safe).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4690E/ADN4694E) or as full-duplex in a 14-lead
SOIC package (the ADN4692E/ADN4695E). A selection table
for the ADN469xE parts is shown in Table 1.
Table 1. ADN469xE Selection Table
Part No. Receiver Data Rate SOIC Duplex
ADN4690E Type 1 100 Mbps 8-lead Half
ADN4691E Type 1 200 Mbps 8-lead Half
ADN4692E Type 1 100 Mbps 14-lead Full
ADN4693E Type 1 200 Mbps 14-lead Full
ADN4694E Type 2 100 Mbps 8-lead Half
ADN4695E Type 2 100 Mbps 14-lead Full
ADN4696E Type 2 200 Mbps 8-lead Half
ADN4697E Type 2 200 Mbps 14-lead Full
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits and Switching Characteristics ................................ 11
REVISION HISTORY
3/12—Rev. 0 to R e v. A
Added ADN4694E and ADN4695E ................................. Universal
Change to Features Section, General Description Section,
and Table 1 .......................................................................................... 1
Added Type 2 Receiver Parameters, Table 2 .................................. 3
Added Table 4, Renumbered Sequentially ..................................... 5
Added Type 2 Receiver Parameters, Table 5 .................................. 5
Driver Voltage and Current Measurements ............................ 11
Driver Timing Measurements .................................................. 12
Receiver Timing Measurements ............................................... 13
Theory of Operation ...................................................................... 14
Half-Duplex/Full-Duplex Operation ....................................... 14
Three-State Bus Connection ..................................................... 14
Tr u t h Ta b l es ................................................................................. 14
Glitch-Free Power-Up/Power-Down ....................................... 15
Fault Conditions ......................................................................... 15
Receiver Input Thresholds/Fail-Safe ........................................ 15
Applications Information .............................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
Changes to Table 8 ............................................................................. 7
Added Table 13 ................................................................................ 14
Changes to Receiver Input Thresholds/Fail-Safe Section
and Figure 35 .................................................................................... 15
Changes to Figure 36 and Figure 37 and Their Captions .......... 16
Changes to Ordering Guide ........................................................... 18
1/12—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 50 Ω; TA = T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage Magnitude |VOD| 480 650 mV See Figure 18
∆|VOD| for Complementary Output States ∆|VOD| −50 +50 mV See Figure 18
Common-Mode Output Voltage (Steady State) V
ΔV
for Complementary Output States ΔV
OC(SS)
Peak-to-Peak VOC V
Maximum Steady-State Open-Circuit Output
Voltage
Voltage Overshoot
Low to High VPH 1.2VSS V See Figure 23, Figure 26
High to Low VPL −0.2VSS V See Figure 23, Figure 26
Output Current
Short Circuit |IOS| 24 mA See Figure 21
High Impedance State, Driver Only IOZ −15 +10 μA
Power Off I
Output Capacitance CY or CZ 3 pF
Differential Output Capacitance CYZ 2.5 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
Output Capacitance Balance (CY/CZ) C
Logic Inputs (DI, DE)
Input High Voltage VIH 2 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH 0 10 μA VIH = 2 V to VCC
Input Low Current IIL 0 10 μA VIL = GND to 0.8 V
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver (ADN4690E, ADN4692E) VTH −50 +50 mV See Table 3, Figure 35
Type 2 Receiver (ADN4694E, ADN4695E) VTH 50 150 mV See Table 4, Figure 35
Input Hysteresis
Type 1 Receiver (ADN4690E, ADN4692E) V
Type 2 Receiver (ADN4694E, ADN4695E) V
Differential Input Voltage Magnitude |VID| 0.05 VCC V
Input Capacitance CA or CB 3 pF
Differential Input Capacitance CAB 2.5 pF VAB = 0.4 sin(30e6πt) V2
Input Capacitance Balance (CA/CB) C
Logic Output RO
Output High Voltage VOH 2.4 V IOH = –8 mA
Output Low Voltage VOL 0.4 V IOL = 8 mA
High Impedance Output Current IOZ −10 +15 μA VO = 0 V or 3.6 V
Logic Input RE
Input High Voltage VIH 2 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 0 μA VIH = 2 V to VCC
Input Low Current IIL −10 0 μA VIL = GND to 0.8 V
MIN
to T
, unless otherwise noted.1
MAX
0.8 1.2 V See Figure 19, Figure 22
OC(SS)
−50 +50 mV See Figure 19, Figure 22
OC(SS)
150 mV See Figure 19, Figure 22
OC(PP)
V
, V
,
A(O)
B(O)
, or V
V
Y(O)
O(OFF)
Y/Z
HYS
HYS
A/B
Z(O)
−10 +10 μA
0.99 1.01
25 mV
0 mV
0.99 1.01
0 2.4 V See Figure 20
–1.4 V ≤ (V
or VZ) ≤ 3.8 V,
Y
other output = 1.2 V
–1.4 V ≤ (V
or VZ) ≤ 3.8 V,
Y
other output = 1.2 V, 0 V ≤ V
= 0.4 sin(30e6πt) V + 0.5 V,2
V
I
other output = 1.2 V, DE = 0 V
= 0.4 sin(30e6πt) V + 0.5 V,2
V
I
other input = 1.2 V
≤ 1.5 V
CC
Rev. A | Page 3 of 20
ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet
−32 0
µA
VB = 1.2 V, VA = −1.4 V
Power-Off Input Current
0 V ≤ VCC ≤ 1.5 V
POWER SUPPLY
Parameter Symbol Min Ty p Max Unit Test Conditions/Comments
BUS INPUT/OUTPUT
Input Current
A (Receiver or Transceiver with Driver Disabled) IA 0 32 µA VB = 1.2 V, VA = 3.8 V
−20 +20 µA VB = 1.2 V, VA = 0 V or 2.4 V
B (Receiver or Transceiver with Driver Disabled) IB 0 32 µA VA = 1.2 V, VB = 3.8 V
−20 +20 µA VA = 1.2 V, VB = 0 V or 2.4 V
−32 0 µA VA = 1.2 V, VB = −1.4 V
−4 +4 µA VA = VB, 1.4 ≤ VA ≤ 3.8 V
Differential (Receiver or Transceiver with Driver
Disabled)
I
AB
A (Receiver or Transceiver) I
0 32 µA VB = 1.2 V, VA = 3.8 V
A(OFF)
−20 +20 µA VB = 1.2 V, VA = 0 V or 2.4 V
−32 0 µA VB = 1.2 V, VA = −1.4 V
B (Receiver or Transceiver) I
0 32 µA VA = 1.2 V, VB = 3.8 V
B(OFF)
−20 +20 µA VA = 1.2 V, VB = 0 V or 2.4 V
−32 0 µA VA = 1.2 V, VB = −1.4 V
Differential (Receiver or Transceiver) I
Input Capacitance (Transceiver with Driver Disabled) CA or CB 5 pF
−4 +4 µA VA = VB, 1.4 V ≤ VA ≤ 3.8 V
AB(OFF)
= 0.4 sin(30e6πt) V + 0.5 V,2
V
I
other input = 1.2 V, DE = 0 V
3 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
Differential Input Capacitance (Transceiver with
C
AB
Driver Disabled)
C
Input Capacitance Balance (CA/CB) (Transceiver
0.99 1.01 DE = 0 V
A/B
with Driver Disabled)
Supply Current ICC
Only Driver Enabled 13 22 mA
Both Driver and Receiver Disabled 1 4 mA
Both Driver and Receiver Enabled 16 24 mA
Only Receiver Enabled 4 13 mA
Total Power Dissipation PD 94 mW
RE
= VCC, RL = 50 Ω
DE,
RE
DE = 0 V,
DE = V
DE,
= 50 Ω, input (DI) = 50 MHz,
R
L
= VCC, RL = no load
, RE = 0 V, RL = 50 Ω
CC
RE
= 0 V, RL = 50 Ω
50% duty cycle square wave;
; RE = 0 V; TA = 85°C
CC
1
All typical values are given for VCC = 3.3 V and TA = 25°C.
2
HP4194A impedance analyzer (or equivalent).
DE = V
RECEIVER INPUT THRESHOLD TEST VOLTAGES
RE
= 0 V, H = high, L = low.
Table 3. Test Voltages for Type 1 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
VA (V) VB (V) VID (V) VIC (V) RO
2.4 0 2.4 1.2 H
0 2.4 −2.4 1.2 L
3.425 3.375 0.05 3.4 H
3.375 3.425 −0.05 3.4 L
−0.975 −1.025 0.05 −1 H
−1.025 −0.975 −0.05 −1 L
Rev. A | Page 4 of 20
Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E
Period Jitter, rms (One Standard Deviation)2
t
2 3 ps
50 MHz clock input3 (see Figure 25)
Enable Time to High Level
t
4 7 ns
See Figure 24, Figure 27
Propagation Delay
t
, t
2 6
ns
CL = 15 pF (see Figure 29, Figure 32)
Period Jitter, rms (One Standard Deviation)2
t
4 7 ps
50 MHz clock input3 (see Figure 31)
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
VA (V) VB (V) VID (V) VIC (V) RO
2.4 0 2.4 1.2 H
0 2.4 −2.4 1.2 L
3.475 3.325 0.15 3.4 H
3.425 3.375 0.05 3.4 L
−0.925 −1.075 0.15 −1 H
−0.975 −1.025 0.05 −1 L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = T
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 100 Mbps
Propagation Delay t
Differential Output Rise/Fall Time tR, tF 2 2.6 3.2 ns See Figure 23, Figure 26
Pulse Skew |t
PHL
− t
PLH
Part-to-Part Skew t
Peak-to-Peak Jitter
2, 4
Disable Time from High Level t
Disable Time from Low Level t
Enable Time to Low Level t
RECEIVER
Rise/Fall Time tR, tF 1 2.3 ns CL = 15 pF (see Figure 29, Figure 32)
Pulse Skew |t
RPHL
– t
Type 1 Receiver (ADN4690E, ADN4692E) tSK 100 300 ps
Type 2 Receiver (ADN4694E, ADN4695E) tSK 300 500 ps
Part-to-Part Skew6 t
Peak-to-Peak Jitter
2, 4
Type 1 Receiver (ADN4690E, ADN4692E) t
Type 2 Receiver (ADN4694E, ADN4695E) t
Disable Time from High Level t
Disable Time from Low Level t
Enable Time to High Level t
Enable Time to Low Level t
1
All typical values are given for VCC = 3.3 V and TA = 25°C.
2
Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3
tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
4
Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
5
tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
6
HP4194A impedance analyzer or equivalent.
to T
MIN
, unless otherwise noted.1
MAX
, t
PLH
PHL
2 2.5 3.5 ns See Figure 23, Figure 26
| tSK 30 150 ps See Figure 23, Figure 26
0.9 ns See Figure 23, Figure 26
SK(PP)
t
J(PER)
150 ps
J(PP)
100 Mbps 2
15
− 1 PRBS input5
(see Figure 28)
4 7 ns See Figure 24, Figure 27
PHZ
4 7 ns See Figure 24, Figure 27
PLZ
PZH
4 7 ns See Figure 24, Figure 27
PZL
RPLH
RPHL
| CL = 15 pF (see Figure 29, Figure 32)
RPLH
1 ns CL = 15 pF (see Figure 29, Figure 32)
SK(PP)
J(PER)
100 Mbps 2
15
− 1 PRBS input5
(see Figure 34)
200 700 ps
J(PP)
225 800 ps
J(PP)
6 10 ns See Figure 30, Figure 33
RPHZ
6 10 ns See Figure 30, Figure 33
RPLZ
10 15 ns See Figure 30, Figure 33
RPZH
10 15 ns See Figure 30, Figure 33
RPZL
Rev. A | Page 5 of 20
ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet
–0.5 V to +4 V
Driver Output (A, B, Y, Z) Voltage
–1.8 V to +4 V
IEC 61000-4-2, Air Discharge
±10 kV
Operating Temperature Range
−40°C to +85°C
Package Type
θJA
Unit
14-Lead SOIC
86
°C/W
ABSOLUTE MAXIMUM RATINGS
TA = T
MIN
to T
, unless otherwise noted.
MAX
Table 6.
Parameter Rating
VCC –0.5 V to +4 V
Digital Input Voltage (DE, , DI)
Receiver Input (A, B) Voltage
Half-Duplex (ADN4690E, ADN4694E) –1.8 V to +4 V
Full-Duplex (ADN4692E, ADN4695E) –4 V to +6 V
Receiver Output Voltage (RO) –0.3 V to +4 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
8-Lead SOIC 121 °C/W
ESD Rating (A, B, Y, Z Pins)
HBM (Human Body Model)
Air Discharge ±15 kV
Contact Discharge ±8 kV
IEC 61000-4-2, Contact Discharge ±8 kV
ESD Rating (Other Pins, HBM) ±4 kV
ESD Rating (All Pins)
FICDM ±1.25 kV
Machine Model ±400 V
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 20
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