ANALOG DEVICES ADN4693E Service Manual

3.3 V, 200 Mbps, Half- and Full-Duplex,

V

Data Sheet

ADN4691E/ADN4693E/ADN4696E/ADN4697E

FEATURES

Multipoint LVDS transceivers (low voltage differential

signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types

Type 1 ( ADN4691E/ADN4693E): hysteresis of 25 mV

Type 2 ( ADN4696E/ADN4697E): threshold offset of 100 mV

for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing

communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins

±15 kV HBM (human body model), air discharge

±8 kV HBM (human body model), contact discharge

±10 kV IEC 61000-4-2, air discharge

±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4691E/ADN4696E) and 14-lead

(ADN4693E/ADN4697E) SOIC packages

High Speed M-LVDS Transceivers

FUNCTIONAL BLOCK DIAGRAMS

CC

ADN4691E/

ADN4696E

RO R

RE

DE

D

DI

GND

Figure 1.

V

CC

ADN4693E/

ADN4697E

RO R

RE

DE

D

DI

GND

Figure 2.

A
B

10355-001

A
B

Z

Y

10355-002

APPLICATIONS

Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure

GENERAL DESCRIPTION

The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV
is implemented on the bus pins. The parts adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA­644 LVDS devices with additional multipoint capabilities.

The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4696E/ADN4697E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).

A

Rev.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4691E/ADN4696E) or as full-duplex in a 14-lead
SOIC package (the ADN4693E/ADN4697E). A selection table
for the ADN469xE parts is shown in Ta ble 1.

Table 1. ADN469xE Selection Table

Part No. Receiver Data Rate SOIC Duplex

ADN4690E Type 1 100 Mbps 8-lead Half
ADN4691E Type 1 200 Mbps 8-lead Half
ADN4692E Type 1 100 Mbps 14-lead Full
ADN4693E Type 1 200 Mbps 14-lead Full
ADN4694E Type 2 100 Mbps 8-lead Half
ADN4695E Type 2 100 Mbps 14-lead Full
ADN4696E Type 2 200 Mbps 8-lead Half
ADN4697E Type 2 200 Mbps 14-lead Full

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Revision History ........................................................................... 2

Specifications..................................................................................... 3

Receiver Input Threshold Test Voltages.................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Test Circuits and Switching Characteristics................................ 11

Driver Voltage and Current Measurements............................ 11

Driver Timing Measurements .................................................. 12

Receiver Timing Measurements............................................... 13

Theory of Operation ...................................................................... 14

Half-Duplex/Full-Duplex Operation....................................... 14

Three-State Bus Connection..................................................... 14

Truth Tables................................................................................. 14

Glitch-Free Power-Up/Power-Down....................................... 15

Fault Conditions......................................................................... 15

Receiver Input Thresholds/Fail-Safe........................................ 15

Applications Information.............................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

3/12—Rev. 0 to Rev. A

Added ADN4691E and ADN4693E................................. Universal

Changes to Features Section, General Description Section,

and Table 1..........................................................................................1

Added Type 1 Receiver Parameters, Table 2 ..................................3

Added Table 3, Renumbered Sequentially .....................................4

Added Type 1 Receiver Parameters, Table 5 ..................................5

Added Table 7.....................................................................................6

Changes to Table 8............................................................................. 7

Changes to Figure 33.......................................................................13

Added Table 12 ................................................................................14

Changes to Receiver Input Thresholds/Fail-Safe Section

and Figure 36....................................................................................15

Changes to Ordering Guide........................................................... 17

12/11—Revision 0: Initial Version

Rev. A | Page 2 of 20

Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E

SPECIFICATIONS

VCC = 3.0 V to 3.6 V; RL = 50 ; TA = T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Outputs

Differential Output Voltage Magnitude |VOD| 480 650 mV See Figure 19
∆|VOD| for Complementary Output States ∆|VOD| −50 +50 mV See Figure 19
Common-Mode Output Voltage (Steady State) V
ΔV

for Complementary Output States ΔV

OC(SS)

Peak-to-Peak VOC V
Maximum Steady-State Open-Circuit Output

Voltage

Voltage Overshoot

Low to High VPH 1.2VSS V See Figure 24, Figure 27
High to Low VPL −0.2VSS V See Figure 24, Figure 27

Output Current

Short Circuit |IOS| 24 mA See Figure 22
High Impedance State, Driver Only IOZ −15 +10 μA

Power Off I

Output Capacitance CY or CZ 3 pF

Differential Output Capacitance CYZ 2.5 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
Output Capacitance Balance (CY/CZ) C

Logic Inputs (DI, DE)

Input High Voltage VIH 2 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH 0 10 μA VIH = 2 V
Input Low Current IIL 0 10 μA VIL = 0.8 V

RECEIVER

Differential Inputs

Differential Input Threshold Voltage

Type 1 Receiver (ADN4691E, ADN4693E) VTH −50 +50 mV See Table 3, Figure 36
Type 2 Receiver (ADN4696E, ADN4697E) VTH 50 150 mV See Table 4 , Figure 36

Input Hysteresis

Type 1 Receiver (ADN4691E, ADN4693E) V

Type 2 Receiver (ADN4696E, ADN4697E) V
Differential Input Voltage Magnitude |VID| 0.05 VCC V
Input Capacitance CA or CB 3 pF

Differential Input Capacitance CAB 2.5 pF VAB = 0.4 sin(30e6πt) V2

Input Capacitance Balance (CA/CB) C

Logic Output RO

Output High Voltage VOH 2.4 V IOH = –8 mA
Output Low Voltage VOL 0.4 V IOL = 8 mA
High Impedance Output Current IOZ −10 +15 μA VO = 0 V or 3.6 V

Logic Input RE

Input High Voltage VIH 2 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 0 μA VIH = 2 V
Input Low Current IIL −10 0 μA VIL = 0.8 V

MIN

to T

, unless otherwise noted. 1

MAX

0.8 1.2 V See Figure 20, Figure 23

OC(SS)

−50 +50 mV See Figure 20, Figure 23

OC(SS)

150 mV See Figure 20, Figure 23

OC(PP)

V

, V

,

A(O)

B(O)

, or V

V

Y(O)

O(OFF)

Y/Z

HYS

HYS

A/B

Z(O)

−10 +10 μA

0.99 1.01

25 mV
0 mV

0.99 1.01

0 2.4 V See Figure 21

–1.4 V ≤ (V

or VZ) ≤ 3.8 V,

Y

other output = 1.2 V
–1.4 V ≤ (V

or VZ) ≤ 3.8 V,

Y

other output = 1.2 V, 0 V ≤ V

= 0.4 sin(30e6πt) V + 0.5 V,2

V

I

other output = 1.2 V, DE = 0 V

= 0.4 sin(30e6πt) V + 0.5 V,2

V

I

other input = 1.2 V

≤ 1.5 V

CC

Rev. A | Page 3 of 20

ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

BUS INPUT/OUTPUT

Input Current

A (Receiver or Transceiver with Driver Disabled) IA 0 32 μA VB = 1.2 V, VA = 3.8 V

−20 +20 μA VB = 1.2 V, VA = 0 V or 2.4 V

−32 0 μA VB = 1.2 V, VA = −1.4 V
B (Receiver or Transceiver with Driver Disabled) IB 0 32 μA VA = 1.2 V, VB = 3.8 V

−20 +20 μA VA = 1.2 V, VB = 0 V or 2.4 V

−32 0 μA VA = 1.2 V, VB = −1.4 V

−4 +4 μA VA = VB, 1.4 V ≤ VA ≤ 3.8 V

Differential (Receiver or Transceiver with Driver

Disabled)

Power-Off Input Current 0 V ≤ VCC ≤ 1.5 V

A (Receiver or Transceiver) I

−20 +20 μA VB = 1.2 V, VA = 0 V or 2.4 V

−32 0 μA VB = 1.2 V, VA = −1.4 V
B (Receiver or Transceiver) I

−20 +20 μA VA = 1.2 V, VB = 0 V or 2.4 V

−32 0 μA VA = 1.2 V, VB = −1.4 V
Differential (Receiver or Transceiver) I

Input Capacitance (Transceiver with Driver Disabled) CA or CB 5 pF

Differential Input Capacitance (Transceiver with

Driver Disabled)

Input Capacitance Balance (CA/CB) (Transceiver

with Driver Disabled)

POWER SUPPLY

Supply Current ICC

Only Driver Enabled 13 22 mA
Both Driver and Receiver Disabled 1 4 mA
Both Driver and Receiver Enabled 16 24 mA
Only Receiver Enabled 4 13 mA

1

All typical values are given for VCC = 3.3 V and TA = 25°C.

2

HP4194A impedance analyzer (or equivalent).

I

AB

0 32 μA VB = 1.2 V, VA = 3.8 V

A(OFF)

0 32 μA VA = 1.2 V, VB = 3.8 V

B(OFF)

−4 +4 μA VA = VB, 1.4 ≤ VA ≤ 3.8 V

AB(OFF)

= 0.4 sin(30e6πt) V + 0.5 V,2

V

I

other input = 1.2 V, DE = 0 V

3 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V

C

AB

C

0.99 1.01 DE = 0 V

A/B

= VCC, RL = 50 Ω

DE, RE
DE = 0 V, RE
DE = V
DE, RE

= VCC, RL = no load

, RE = 0 V, RL = 50 Ω

CC

= 0 V, RL = 50 Ω

RECEIVER INPUT THRESHOLD TEST VOLTAGES

RE

= 0 V, H = high, L = low

Table 3. Test Voltages for Type 1 Receiver

Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output

VA (V) VB (V) VID (V) VIC (V) RO (V)

2.4 0 2.4 1.2 H
0 2.4 −2.4 1.2 L

3.8 3.75 0.05 3.775 H

3.75 3.8 −0.05 3.775 L

−1.35 −1.4 0.05 −1.375 H

−1.4 −1.35 −0.05 −1.375 L

Rev. A | Page 4 of 20

Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E

Table 4. Test Voltages for Type 2 Receiver

Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output

VA (V) VB (V) VID (V) VIC (V) RO (V)

+2.4 0 +2.4 +1.2 H
0 +2.4 −2.4 +1.2 L
+3.8 +3.65 +0.15 +3.725 H
+3.8 +3.75 +0.05 +3.775 L

−1.25 −1.4 +0.15 −1.325 H

−1.35 −1.4 +0.05 −1.375 L

TIMING SPECIFICATIONS

VCC = 3.0 V to 3.6 V; TA = T

Table 5.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Maximum Data Rate 200 Mbps
Propagation Delay t
Differential Output Rise/Fall Time tR, tF 1 1.6 ns See Figure 24, Figure 27
Pulse Skew |t

PHL

– t

PLH

Part-to-Part Skew2 t
Period Jitter, RMS (1 Standard Deviation)3 t
Peak-to-Peak Jitter

3, 5

Disable Time from High Level t
Disable Time from Low Level t
Enable Time to High Level t
Enable Time to Low Level t

RECEIVER

Propagation Delay t
Rise/Fall Time tR, tF 1 2.3 ns CL = 15 pF (see Figure 30, Figure 33)
Pulse Skew |t

RPHL

– t

RPLH

Type 1 Receiver (ADN4691E,

ADN4693E)

Type 2 Receiver (ADN4696E,

ADN4697E)

Part-to-Part Skew2 t
Period Jitter, RMS (1 Standard Deviation)3 t
Peak-to-Peak Jitter

3, 5

Type 1 Receiver (ADN4691E,

ADN4693E)

Type 2 Receiver (ADN4696E,

ADN4697E)

Disable Time from High Level t
Disable Time from Low Level t
Enable Time to High Level t
Enable Time to Low Level t

1

All typical values are given for VCC = 3.3 V and TA = 25°C.

2

t

is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC

SK(PP)

and temperature, and with identical packages and test circuits.

3

Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.

4

tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.

5

Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).

6

tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.

7

|VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.

8

|VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.

to T

MIN

, unless otherwise noted.1

MAX

, t

1 1.5 2.4 ns See Figure 24, Figure 27

PLH

PHL

| tSK 0 100 ps See Figure 24, Figure 27

1 ns See Figure 24, Figure 27

SK(PP)

2 3 ps 100 MHz clock input4 (see Figure 26)

J(PER)

t

| tSK C

30 130 ps 200 Mbps 215 − 1 PRBS input6 (see Figure 29)

J(PP)

7 ns See Figure 25, Figure 28

PHZ

7 ns See Figure 25, Figure 28

PLZ

7 ns See Figure 25, Figure 28

PZH

7 ns See Figure 25, Figure 28

PZL

, t

RPLH

2 4 6 ns CL = 15 pF (see Figure 30, Figure 33)

RPHL

= 15 pF (see Figure 30, Figure 33)

L

100 300 ps

300 500 ps

1 ns CL = 15 pF (see Figure 30, Figure 33)

SK(PP)

4 7 ps 100 MHz clock input7 (see Figure 32)

J(PER)

t

200 Mbps 215 − 1 PRBS input8 (see Figure 35)

J(PP)

t

300 700 ps

J(PP)

450 800 ps

10 ns See Figure 31, Figure 34

RPHZ

10 ns See Figure 31, Figure 34

RPLZ

15 ns See Figure 31, Figure 34

RPZH

15 ns See Figure 31, Figure 34

RPZL

Rev. A | Page 5 of 20

ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet

ABSOLUTE MAXIMUM RATINGS

= T

MIN

to T

T

A

, unless otherwise noted.

MAX

Table 6.

Parameter Rating

VCC −0.5 V to +4 V
Digital Input Voltage (DE, RE, DI)
Receiver Input (A, B) Voltage

Half-Duplex (ADN4691E, ADN4696E) −1.8 V to +4 V

Full-Duplex (ADN4693E, ADN4697E) −4 V to +6 V
Receiver Output Voltage (RO) −0.3 V to +4 V
Driver Output (A, B, Y, Z) Voltage −1.8 V to +4 V
ESD Rating (A, B, Y, Z Pins)

HBM (Human Body Model)

Air Discharge ±15 kV

Contact Discharge ±8 kV
IEC 61000-4-2, Air Discharge ±10 kV
IEC 61000-4-2, Contact Discharge ±8 kV

ESD Rating (Other Pins, HBM) ±4 kV
ESD Rating (All Pins)

FICDM ±1.25 kV
Machine Model ±400 V

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

−0.5 V to +4 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA Unit

8-Lead SOIC 121 °C/W
14-Lead SOIC 86 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 6 of 20