ANALOG DEVICES ADN4668 Service Manual

3 V LVDS Quad CMOS

V

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FEATURES

±15 kV ESD protection on receiver input pins
400 Mbps (200 MHz) switching rates
Flow-through pin configuration simplifies PCB layout
150 ps channel-to-channel skew (typical)
100 ps differential skew (typical)

2.7 ns maximum propagation delay

3.3 V power supply
High impedance outputs on power-down
Low power design (3 mW quiescent typical)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential

input signal levels
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range of −40°C to +85°C
Available in 16-lead surface-mount SOIC and 16-lead low

profile TSSOP package

Differential Line Receiver

ADN4668

FUNCTIONAL BLOCK DIAGRAM

CC

ADN4668

R

IN1+

R

IN1–

R

IN2+

R

IN2–

R

IN3+

R

IN3–

R

IN4+

R

IN4–

EN

EN

Figure 1.

GND

R1

R2

R3

R4

R

R

R

R

OUT1

OUT2

OUT3

OUT4

07237-001

APPLICATIONS

Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers

GENERAL DESCRIPTION

The ADN4668 is a quad-channel CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption. It features a flow­through pin configuration for easy PCB layout and separation
of input and output signals.

The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.

The ADN4668 also offers active-high and active-low enable/disable
inputs (EN and

EN

) that control all four receivers. They disable

the receivers and switch the outputs to a high impedance state.

This high impedance state allows the outputs of one or more
ADN4668s to be multiplexed together and reduces the quies­cent power consumption to 3 mW typical.

The ADN4668 and its companion driver, the ADN4667, offer
a new solution to high speed, point-to-point data transmission
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADN4668

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

Test Circuits and Waveforms ...................................................... 4

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

7/08—Rev. 0 to Rev. A

Added 16-Lead SOIC_N .................................................... Universal

Changes to Table 1 ............................................................................ 3

Updated Outline Dimensions ....................................................... 12

Changes to Ordering Guide .......................................................... 12

3/08—Revision 0: Initial Version

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 11

Enable Inputs .............................................................................. 11

Applications Information .......................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

ADN4668

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SPECIFICATIONS

VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

LVDS INPUTS (R

Differential Input High Threshold, VTH at R

Differential Input Low Threshold, VTL at R

Common-Mode Voltage Range, V

Input Current, IIN at R

INx+

, R

)

INx−

INx+

INx+

at R

CMR

INx+

, R

−10 ±5 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V

INx−

3

INx+

, R

INx−

, R

INx−

, R

INx−

−35 0 mV VCM = 1.2 V, 0.05 V, 2.95 V

3

−100 −35 mV V

4

0.1 2.3 V VID = 200 mV p-p

−10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V

−20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V

LOGIC INPUTS

Input High Voltage, VIH 2.0 VCC V

Input Low Voltage, VIL GND 0.8 V

Input Current, IIN −10 ±5 +10 μA VIN = 0 V or VCC, other input = VCC or GND

Input Clamp Voltage, VCL −1.5 −0.8 V ICL = −18 mA

OUTPUTS (R

)

OUTx

Output High Voltage, VOH 2.7 3.3 V IOH = −0.4 mA, VID = 200 mV

2.7 3.3 V IOH = −0.4 mA, input terminated

2.7 3.3 V IOH = −0.4 mA, input shorted

Output Low Voltage, VOL 0.05 0.25 V IOL = 2 mA, VID = −200 mV

Output Short-Circuit Current, I

5

OS

−15 −47 −100 V Enabled, V

Output Off State Current, IOZ −10 ±1 +10 μA Disabled, V

POWER SUPPLY

No Load Supply, Current Receivers Enabled, ICC 12 15 mA EN = VCC, inputs open

No Load Supply, Current Receivers Disabled, I

1 5 mA EN = GND, inputs open

CCZ

ESD PROTECTION

R

, R

Pins ±15 kV Human body model

INx+

INx−

All Pins Except R

1

Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.

2

All typicals are given for VCC = 3.3 V and TA = 25°C.

3

VCC is always higher than the R

common voltage range is 0.1 V to 2.3 V.

4

V

is reduced for larger VID. For example, if VID = 400 mV, V

CMR

range of 0 V to 2.4 V but is supported only with inputs shorted and no external common-mode voltage applied. V
inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew
specifications apply for 200 mV ≤ V

5

Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Only one output should be shorted at a time; do not exceed the

maximum junction temperature specification.

INx+

, R

±3.5 kV Human body model

INx−

and R

INx+

voltage. R

INx−

≤ 800 mV over the common-mode range.

ID

and R

INx−

have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the

INx+

is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode

CMR

1, 2

= 1.2 V, 0.05 V, 2.95 V

CM

= 0 V

OUT

= 0 V or VCC

OUT

up to VCC − 0 V can be applied to the R

ID

INx+/RINx−

Rev. A | Page 3 of 12

ADN4668

V

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AC CHARACTERISTICS

VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.

MAX

1, 2, 3, 4

Table 2.

Parameter

Differential Propagation Delay, High-to-Low, t
Differential Propagation Delay, Low-to-High, t
Differential Pulse Skew |t
Differential Channel-to-Channel Skew, Same Device, t
Differential Part-to-Part Skew, t
Differential Part-to-Part Skew, t
Rise Time, t
Fall Time, t
Disable Time, High-to-Z, t
Disable Time, Low-to-Z, t
Enable Time, Z-to-High, t
Enable Time, Z-to-Low, t
Maximum Operating Frequency, f

1

All typicals are given for VCC = 3.3 V and TA = 25°C.

2

Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, and tR and tF (0% to 100%) ≤ 3 ns for R

3

Channel-to-channel skew, t

the inputs.

4

Part-to-part skew, t

each other within the operating temperature range.

5

AC parameters are guaranteed by design and characterization.

6

Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.

7

CL includes probe and jig capacitance.

8

t

SKD1

9

Part-to-part skew, t

operating temperature and voltage ranges and across process distribution. t

10

f

MAX

5

1.2 2.0 2.7 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

PHLD

1.2 1.9 2.7 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

PLHD

− t

PHLD

PLHD

SKD3

SKD4

0.5 1.0 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

TLH

0.35 1.0 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

THL

8 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PHZ

8 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PLZ

9 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PZH

9 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PZL

, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on

SKD2

, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of

SKD3

8

|, t

SKD1

4

1.0 ns C

9

10

MAX

Min Typ Max Unit Conditions/Comments

0 0.1 0.4 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

3

0 0.15 0.5 ns C

SKD2

= 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

L

= 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

L

1.5 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

200 250 MHz All channels switching

INx+/RINx−

is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.

, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended

SKD4

generator input conditions: f = 200 MHz, tR = tF < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V p-p to 1.35 V p-p). Output criteria: 60%/40% duty cycle,

is defined as |maximum − minimum| differential propagation delay.

SKD4

VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), CL = 15 pF (stray plus probes).

6

.

TEST CIRCUITS AND WAVEFORMS

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

R

INx–

R

INx+

R

OUTx

Figure 3. Receiver Propagation Delay and Transition Time Waveforms

R

SIGNAL

GENERATOR

50Ω 50Ω

CL= LOAD AND TEST JIG CAPACITANCE

0V (DIFFERENTIAL)

t

PLHD

1.5V

20%

t

TLH

INx+

R

INx–

RECEIVER

IS ENABLED

VID= 200mV

Rev. A | Page 4 of 12

CC

R

OUTx

C

L

07237-002

1.3V

1.2V

1.1V

t

PHLD

V

OH

80%80%

1.5V

20%

V

t

THL

OL

07237-003

ADN4668

V

V

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CC

R

INx+

R

INx–

EN

SIGNAL

GENERATOR

NOTES

INCLUDES L OAD AND TE ST JIG CAPACITANCE.

1. C

L

2. S1 CONNECTED TO V

3. S1 CONNECTED TO GND FO R

50Ω

EN

GND

FOR

t

AND

t

CC

PZL

t

PZH

AND

PLZ

t

PHZ

MEASUREMENTS.

MEASUREMENTS.

Figure 4. Test Circuit for Receiver Enable/Disable Delay

EN WITH EN = GND
OR OPEN CIRCUIT

1.5V

S1

R

L

R

OUTx

C

L

07237-004

3

1.5V

0V

EN WITH EN = V

WITH VID = +100mV

R

OUTx

WITH VID = –100mV

R

OUTx

1.5V

CC

t

PHZ

t

PLZ

0.5V

0.5V

Figure 5. Receiver Enable/Disable Delay Waveforms

1.5V

t

PZH

t

PZL

50%

50%

3V

0V

V

OH

GND

V

CC

V

OL

07237-005

Rev. A | Page 5 of 12

ADN4668

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VCC to GND −0.3 V to +4 V
Input Voltage (R
Enable Input Voltage (EN, EN) to GND
Output Voltage (R
Operating Temperature Range

Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (T

Power Dissipation (T
Thermal Impedance, θJA

TSSOP Package 150.4°C/W

SOIC Package 125°C/W ± 5°C
Reflow Soldering Peak Temperature

Pb-Free 260°C ± 5°C

, R

INx+

) to GND −0.3 V to VCC + 0.3 V

INx−

−0.3 V to V

) to GND −0.3 V to VCC + 0.3 V

OUTx

) 150°C

J MAX

− TA)/θJA

J MAX

+ 0.3 V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 12

ADN4668

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

R

IN1–

2

R

IN1+

3

R

IN2+

ADN4668

TOP VIEW

4

R

IN2–

(Not to Scale)

5

R

IN3–

6

R

IN3+

7

R

IN4+

8

R

IN4–

16

EN

15

R

OUT1

14

R

OUT2

13

V

CC

12

GND

11

R

OUT3

10

R

OUT4

9

EN

07237-006

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

2 R

3 R

4 R

5 R

6 R

7 R

8 R

9

10 R

IN1−

IN1+

IN2+

IN2−

IN3−

IN3+

IN4+

IN4−

Active-Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). When EN is held high, EN enables the

EN

OUT4

Receiver Channel 1 Inverting Input. When this input is more negative than R

, R

more positive than R

IN1+

OUT1

is low.

Receiver Channel 1 Noninverting Input. When this input is more positive than R
is more negative than R

IN1−

, R

OUT1

is low.

Receiver Channel 2 Noninverting Input. When this input is more positive than R

, R

is more negative than R

IN2−

OUT2

is low.

Receiver Channel 2 Inverting Input. When this input is more negative than R

, R

more positive than R

IN2+

OUT2

is low.

Receiver Channel 3 Inverting Input. When this input is more negative than R

, R

more positive than R

IN3+

OUT3

is low.

Receiver Channel 3 Noninverting Input. When this input is more positive than R

, R

is more negative than R

IN3−

OUT3

is low.

Receiver Channel 4 Noninverting Input. When this input is more positive than R
is more negative than R

IN4−

, R

OUT4

is low.

Receiver Channel 4 Inverting Input. When this input is more negative than R

, R

more positive than R

IN4+

receiver outputs when EN
powers down the device when EN

is low.

OUT4

is low or open circuit and puts the receiver outputs into a high impedance state and

is high.

Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between R
output is high. If the differential input voltage is negative, this output is low.

11 R

OUT3

Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between R

output is high. If the differential input voltage is negative, this output is low.
12 GND Ground Reference Point for All Circuitry on the Part.
13 VCC Power Supply Input. These parts can be operated from 3.0 V to 3.6 V.
14 R

OUT2

Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between R

output is high. If the differential input voltage is negative, this output is low.
15 R

OUT1

Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between R

output is high. If the differential input voltage is negative, this output is low.
16 EN

Active-High Enable and Power-Down Input (3 V TTL/CMOS). When EN

receiver outputs when EN is high and puts the receiver outputs into a high impedance state and powers down

the device when EN is low.

, R

IN1+

IN2+

IN3+

IN4+

is high. When this input is

OUT1

, R

IN1−

IN2−

, R

, R

IN3−

IN4−

, R

is high. When this input

OUT1

, R

is high. When this input

OUT2

is high. When this input is

OUT2

is high. When this input is

OUT3

, R

is high. When this input

OUT3

, R

is high. When this input

OUT4

is high. When this input is

OUT4

and R

IN4+

IN3+

IN2+

IN1+

and R

and R

and R

IN4−

IN3−

IN2−

IN1−

is positive, this

is positive, this

is positive, this

is positive, this

is held low or open circuit, EN enables the

Rev. A | Page 7 of 12

ADN4668

V

V

–

–

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TYPICAL PERFORMANCE CHARACTERISTICS

3.6

I

= –400µA

3.5

(V)

OH

3.4

3.3

3.2

3.1

OUTPUT HIGH VOLTAGE,

3.0

2.9

LOAD

T

= 25°C

A

V

= 200mV

ID

3.0 3.1 3.2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

Figure 7. Output High Voltage, VOH vs. Power Supply Voltage, VCC

07237-007

0.06

V

= 0V

–0.07

(nA)

–0.08

OS

–0.09

–0.10

–0.11

–0.12

–0.13

OUTPUT TRISTATE CURRENT, I

–0.14

–0.15

3.0 3.1 3.2 3.3 3.4 3.5 3.6

OUT

T

= 25°C

A

POWER SUPPLY VOLTAG E, VCC (V)

Figure 10. Output Tristate Current, IOS vs. Power Supply Voltage, V

07237-010

CC

33.60

I

= 2µA

LOAD

T

33.55

(mV)

33.50

OL

33.45

33.40

33.35

OUTPUT LOW VOLTAGE,

33.30

33.25

3.0 3.1 3.2 3.3 3.4 3.5 3.6

= 25°C

A

V

= –200mV

ID

POWER SUPPLY VOLTAG E, VCC (V)

Figure 8. Output Low Voltage, VOL vs. Power Supply Voltage, VCC

35

V

= 0V

–37

(mA)

OS

–39

–41

–43

–45

–47

–49

–51

–53

OUTPUT SHO RT-CIRCUIT CURRENT, I

–55

3.0 3.1 3.2 3.3 3.4 3.5 3.6

OUT

T

= 25°C

A

POWER SUPPLY VOLTAGE, VCC (V)

Figure 9. Output Short-Circuit Current, IOS vs. Power Supply Voltage, V

0

V

= 0V

–5

–10

(mV)

–15

TH

–20

–25

–30

–35

–40

THRESHOLD VOLTAGE,

–45

–50

07237-008

Figure 11. Threshold Voltage, V

100

90

80

(mA)

CC

70

60

50

40

30

20

POWER SUPPL Y CURRENT, I

10

07237-009

CC

OUT

T

= 25°C

A

3.0 3.1 3.2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

vs. Power Supply Voltage, V

TH

ALL CHANNELS SWI TCHING

ONE CHANNEL SW ITCHING

0

10k 100k 1M 10M 100M 1G

BIT RATE (bps)

Figure 12. Power Supply Current, ICC vs. Bit Rate

07237-011

CC

07237-012

Rev. A | Page 8 of 12

ADN4668

www.BDTIC.com/ADI

93.5

93.0

(mA)

CC

92.5

92.0

91.5

91.0

90.5

POWER SUPPL Y CURRENT, I

90.0
–40 –15 10 35 60 85

AMBIENT TEM PERATURE, TA (°C)

VCC= 3.3V
V

=200mV

ID

FREQ = 200MHz
ALL CHANNELS
SWITCHING

Figure 13. Power Supply Current, ICC vs. Ambient Temperature, TA

2.35

VCC= 3.3V
V

=200mV

ID

2.30
FREQ = 200MHz

C

=15pF

L

2.25

t

t

PLHD

t

PHLD

A

CM

PHLD

t

PLHD

, t

vs.

PLHD

PHLD

2.5

, t

vs.

PLHD

PHLD

(ns)

2.20

PHLD

t

,

2.15

PLHD

t

2.10

2.05

DIFFERENTIAL PROPAG ATION DEL AY,

2.00

–40 –15 10 35 8560

AMBIENT TEMPERATURE, TA (°C)

Figure 14. Differential Propagation Delay, t

Ambient Temperature, T

4.0

TA= 25°C
FREQ = 200M Hz
V

=200mV

ID

3.5
C

=15pF

L

3.0

(ns)

PHLD

t

,

2.5

PLHD

t

2.0

DIFFERENTIAL PROPAGATION DELAY,

1.5

0 0.5 1.0 1.5 3.02.0

COMMON-MODE VOLTAGE, VCM (V)

Figure 15. Differential Propagation Delay, t

Common-Mode Voltage, V

07237-022

07237-014

07237-015

2.40

2.35

2.30

2.25

(ns)

2.20

PHLD

t

,

2.15

PLHD

t

2.10

2.05

DIFFERENTIAL PROPAG ATION DEL AY,

2.00

1.95

3.03.13.23.3 33.4 .6

POWER SUPPLY VOLTAGE, VCC (V)

Figure 16. Differential Propagation Delay, t

Power Supply Voltage, V

8

TA= 25°C

7

FREQ = 200MHz
V

= 1.2V

CM

C

=15pF

6

L

5

(ns)

PHLD

4

t

,

3

PLHD

t

2

DIFFERENTIAL PROPAG ATION DEL AY,

1

0

0 500 1000 1500 30002000

t

PLHD

t

PHLD

DIFFERENTIAL INPUT VOLTAGE, VID (mV)

Figure 17. Differential Propagation Delay, t

Differential Input Voltage, V

200

TA=25°C
V

=200mV

ID

150

FREQ = 200M Hz
C

=15pF

(ps)

SKD

t

–100

DIFFERENTIAL SKEW,

–150

–200

Figure 18. Differential Skew, t

L

100

50

0

–50

3.0 3.1 3.2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

vs. Power Supply Voltage, V

SKD

TA= 25°C
V

ID

FREQ = 200MHz
C

=15pF

L

PLHD

CC

PLHD

ID

=200mV

3.5

, t

PHLD

2500

, t

PHLD

t

PHLD

t

PLHD

vs.

vs.

07237-016

07237-017

07237-018

CC

Rev. A | Page 9 of 12

ADN4668

www.BDTIC.com/ADI

80

VCC= 3.3V
V

=200mV

ID

60

FREQ = 200MHz
C

=15pF

(ps)

SKD

t

DIFFERENTIAL SKEW,

L

40

20

0

–20

–40

–60

–80

–40 –15 10 35 60 85

Figure 19. Differential Skew, t

AMBIENT TEM PERATURE, TA (°C)

vs. Ambient Temperature, TA Figure 21. Transition Time, t

SKD

07237-019

560

VCC= 3.3V

550

V

= 200mV

ID

FREQ = 25M Hz
C

=15pF

L

t

TLH

t

THL

–40 –15 10 35 60 80

AMBIENT TEMPERATURE, TA (°C)

, t

vs. Ambient Temperature, TA

TLH

THL

(ps)

t

,

t

TRANSITIO N TIME,

THL

TLH

540

530

520

510

500

490

480

470

460

450

07237-021

550

540

530

(ps)

THL

t

520

,

TLH

t

510

500

490

480

TRANSITION TIME,

470

460

3.03.13.23.3 3.3.4 6

Figure 20. Transition Time, t

t

TLH

t

THL

POWER SUPPLY VOLTAGE, VCC (V)

, t

vs. Power Supply Voltage, VCC

TLH

THL

TA= 25°C
V

= 200mV

ID

FREQ = 25MHz
C

=15pF

L

3.5

07237-020

Rev. A | Page 10 of 12

ADN4668

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADN4668 is a quad-channel line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typical and converts it into a single-ended 3 V TTL/
CMOS logic signal.

A differential current input signal, received via a transmission
medium such as a twisted pair cable, develops a voltage across
a terminating resistor, R

. This resistor is chosen to match the

T

characteristic impedance of the medium, typically around 100 Ω.
The differential voltage is detected by the receiver and converted
back into a single-ended logic signal.

When the noninverting receiver input, R
respect to the inverting input, R
from R
input, R
(current flows through R

to R

), R

INx+

INx−

, is negative with respect to the inverting input, R

IN+

is high. When the noninverting receiver

OUTx

from R

T

(current flows through RT

INx−

INx−

, is positive with

INx+

to R

INx+

), R

OUTx

INx−

is low.

Using the ADN4667 as a driver, the received differential current
is between ±2.5 mA and ±4.5 mA (±3.1 mA typical), developing
between ±250 mV and ±450 mV across a 100 Ω termination
resistor. The received voltage is centered on the receiver offset
of 1.2 V. The noninverting receiver input is typically
(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
is (1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note
that because the differential voltage reverses polarity, the peak-to­peak voltage swing across R

is twice the differential voltage.

T

Current-mode signaling offers considerable advantages over
voltage-mode signaling, such as the RS-422. The operating
current remains fairly constant with increased switching
frequency, whereas the operating current of voltage-mode
drivers increases exponentially in most cases. This increase is
caused by the overlap as internal gates switch between high and
low, causing currents to flow from V

to ground. A current-

CC

mode device reverses a constant current between its two outputs,
with no significant overlap currents.

This is similar to emitter-coupled logic (ECL) and positive emitter­coupled logic (PECL), but without the high quiescent current of
ECL and PECL.

ENABLE INPUTS

The ADN4668 has active-high and active-low enable inputs that
put all the logic outputs into a high impedance state when disabled,
reducing device current consumption from 9 mA typical to 1 mA
typical. See Tab l e 5 for a truth table of the enable inputs.

Table 5. Enable Inputs Truth Table

EN

EN

R

R

INx+

R

INx−

OUTx

High Low or Open 1.045 V 1.355 V 0
High Low or Open 1.355 V 1.045 V 1
Any other combination

of EN and EN

X X High-Z

APPLICATIONS INFORMATION

Figure 22 shows a typical application for point-to-point data
transmission using the ADN4667 as the driver and the ADN4668
as the receiver.

EN

EN

D

IN

GND

D

OUTy+

D

OUTy–

Figure 22. Typical Application Circuit

Rev. A | Page 11 of 12

R

R

T

100Ω

R

1/4 ADN46681/4 ADN4667

INx+

INx–

GND

EN

EN

D

OUT

07237-023

ADN4668

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; I NCH DIMENSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

Figure 23. 16-Lead Standard Small Outline Package [SOIC_N]

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

16

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADN4668ARZ
ADN4668ARZ-REEL7
ADN4668ARUZ
ADN4668ARUZ-REEL7

1

Z = RoHS Compliant Part.

1

1

−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

(R-16)

9

6.40
BSC

81

1.20
MAX

0.30

0.19

SEATING
PLANE

0.20

0.09

(RU-16)

Dimensions shown in millimeters

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

8°
0°

0.75

0.60

0.45

45°

060606-A

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07237-0-7/08(A)

Rev. A | Page 12 of 12