ANALOG DEVICES ADN4668 Service Manual

3 V LVDS Quad CMOS

V

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FEATURES

±15 kV ESD protection on receiver input pins
400 Mbps (200 MHz) switching rates
Flow-through pin configuration simplifies PCB layout
150 ps channel-to-channel skew (typical)
100 ps differential skew (typical)

2.7 ns maximum propagation delay

3.3 V power supply
High impedance outputs on power-down
Low power design (3 mW quiescent typical)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential

input signal levels
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range of −40°C to +85°C
Available in 16-lead surface-mount SOIC and 16-lead low

profile TSSOP package

Differential Line Receiver

ADN4668

FUNCTIONAL BLOCK DIAGRAM

CC

ADN4668

R

IN1+

R

IN1–

R

IN2+

R

IN2–

R

IN3+

R

IN3–

R

IN4+

R

IN4–

EN

EN

Figure 1.

GND

R1

R2

R3

R4

R

R

R

R

OUT1

OUT2

OUT3

OUT4

07237-001

APPLICATIONS

Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers

GENERAL DESCRIPTION

The ADN4668 is a quad-channel CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption. It features a flow­through pin configuration for easy PCB layout and separation
of input and output signals.

The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.

The ADN4668 also offers active-high and active-low enable/disable
inputs (EN and

EN

) that control all four receivers. They disable

the receivers and switch the outputs to a high impedance state.

This high impedance state allows the outputs of one or more
ADN4668s to be multiplexed together and reduces the quies­cent power consumption to 3 mW typical.

The ADN4668 and its companion driver, the ADN4667, offer
a new solution to high speed, point-to-point data transmission
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADN4668

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

Test Circuits and Waveforms ...................................................... 4

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

7/08—Rev. 0 to Rev. A

Added 16-Lead SOIC_N .................................................... Universal

Changes to Table 1 ............................................................................ 3

Updated Outline Dimensions ....................................................... 12

Changes to Ordering Guide .......................................................... 12

3/08—Revision 0: Initial Version

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 11

Enable Inputs .............................................................................. 11

Applications Information .......................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

ADN4668

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SPECIFICATIONS

VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

LVDS INPUTS (R

Differential Input High Threshold, VTH at R

Differential Input Low Threshold, VTL at R

Common-Mode Voltage Range, V

Input Current, IIN at R

INx+

, R

)

INx−

INx+

INx+

at R

CMR

INx+

, R

−10 ±5 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V

INx−

3

INx+

, R

INx−

, R

INx−

, R

INx−

−35 0 mV VCM = 1.2 V, 0.05 V, 2.95 V

3

−100 −35 mV V

4

0.1 2.3 V VID = 200 mV p-p

−10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V

−20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V

LOGIC INPUTS

Input High Voltage, VIH 2.0 VCC V

Input Low Voltage, VIL GND 0.8 V

Input Current, IIN −10 ±5 +10 μA VIN = 0 V or VCC, other input = VCC or GND

Input Clamp Voltage, VCL −1.5 −0.8 V ICL = −18 mA

OUTPUTS (R

)

OUTx

Output High Voltage, VOH 2.7 3.3 V IOH = −0.4 mA, VID = 200 mV

2.7 3.3 V IOH = −0.4 mA, input terminated

2.7 3.3 V IOH = −0.4 mA, input shorted

Output Low Voltage, VOL 0.05 0.25 V IOL = 2 mA, VID = −200 mV

Output Short-Circuit Current, I

5

OS

−15 −47 −100 V Enabled, V

Output Off State Current, IOZ −10 ±1 +10 μA Disabled, V

POWER SUPPLY

No Load Supply, Current Receivers Enabled, ICC 12 15 mA EN = VCC, inputs open

No Load Supply, Current Receivers Disabled, I

1 5 mA EN = GND, inputs open

CCZ

ESD PROTECTION

R

, R

Pins ±15 kV Human body model

INx+

INx−

All Pins Except R

1

Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.

2

All typicals are given for VCC = 3.3 V and TA = 25°C.

3

VCC is always higher than the R

common voltage range is 0.1 V to 2.3 V.

4

V

is reduced for larger VID. For example, if VID = 400 mV, V

CMR

range of 0 V to 2.4 V but is supported only with inputs shorted and no external common-mode voltage applied. V
inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew
specifications apply for 200 mV ≤ V

5

Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Only one output should be shorted at a time; do not exceed the

maximum junction temperature specification.

INx+

, R

±3.5 kV Human body model

INx−

and R

INx+

voltage. R

INx−

≤ 800 mV over the common-mode range.

ID

and R

INx−

have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the

INx+

is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode

CMR

1, 2

= 1.2 V, 0.05 V, 2.95 V

CM

= 0 V

OUT

= 0 V or VCC

OUT

up to VCC − 0 V can be applied to the R

ID

INx+/RINx−

Rev. A | Page 3 of 12

ADN4668

V

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AC CHARACTERISTICS

VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.

MAX

1, 2, 3, 4

Table 2.

Parameter

Differential Propagation Delay, High-to-Low, t
Differential Propagation Delay, Low-to-High, t
Differential Pulse Skew |t
Differential Channel-to-Channel Skew, Same Device, t
Differential Part-to-Part Skew, t
Differential Part-to-Part Skew, t
Rise Time, t
Fall Time, t
Disable Time, High-to-Z, t
Disable Time, Low-to-Z, t
Enable Time, Z-to-High, t
Enable Time, Z-to-Low, t
Maximum Operating Frequency, f

1

All typicals are given for VCC = 3.3 V and TA = 25°C.

2

Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, and tR and tF (0% to 100%) ≤ 3 ns for R

3

Channel-to-channel skew, t

the inputs.

4

Part-to-part skew, t

each other within the operating temperature range.

5

AC parameters are guaranteed by design and characterization.

6

Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.

7

CL includes probe and jig capacitance.

8

t

SKD1

9

Part-to-part skew, t

operating temperature and voltage ranges and across process distribution. t

10

f

MAX

5

1.2 2.0 2.7 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

PHLD

1.2 1.9 2.7 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

PLHD

− t

PHLD

PLHD

SKD3

SKD4

0.5 1.0 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

TLH

0.35 1.0 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

THL

8 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PHZ

8 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PLZ

9 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PZH

9 14 ns RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5

PZL

, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on

SKD2

, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of

SKD3

8

|, t

SKD1

4

1.0 ns C

9

10

MAX

Min Typ Max Unit Conditions/Comments

0 0.1 0.4 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

3

0 0.15 0.5 ns C

SKD2

= 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

L

= 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

L

1.5 ns CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3

200 250 MHz All channels switching

INx+/RINx−

is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.

, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended

SKD4

generator input conditions: f = 200 MHz, tR = tF < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V p-p to 1.35 V p-p). Output criteria: 60%/40% duty cycle,

is defined as |maximum − minimum| differential propagation delay.

SKD4

VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), CL = 15 pF (stray plus probes).

6

.

TEST CIRCUITS AND WAVEFORMS

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

R

INx–

R

INx+

R

OUTx

Figure 3. Receiver Propagation Delay and Transition Time Waveforms

R

SIGNAL

GENERATOR

50Ω 50Ω

CL= LOAD AND TEST JIG CAPACITANCE

0V (DIFFERENTIAL)

t

PLHD

1.5V

20%

t

TLH

INx+

R

INx–

RECEIVER

IS ENABLED

VID= 200mV

Rev. A | Page 4 of 12

CC

R

OUTx

C

L

07237-002

1.3V

1.2V

1.1V

t

PHLD

V

OH

80%80%

1.5V

20%

V

t

THL

OL

07237-003