ANALOG DEVICES ADN4667 Service Manual
Differential Line Driver
ADN4667
Rev. B
by Analog Devices is believed to be accurate and reliable. However, no
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
07032-001
ADN4667
D
OUT1+
D
OUT1–
D
IN1
D
OUT2+
D
OUT2–
D
IN2
D
OUT3+
D
OUT3–
D
IN3
D
OUT4+
D
OUT4–
D
IN4
EN
EN
GND
D4
D3
D2
D1
V
CC
Data Sheet
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
Flow through pinout simplifies PCB layout
300 ps typical differential skew
400 ps maximum differential skew
1.7 ns maximum propagation delay
3.3 V power supply
±310 mV differential signaling
Low power dissipation (10 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) and low profile
TSSOP package
Qualified for automotive applications
3 V LVDS Quad CMOS
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4667 is a quad, CMOS, low voltage differential signaling
(LVDS) line driver offering data rates of over 400 Mbps (200 MHz)
and ultralow power consumption. It features a flow through
pinout for easy PCB layout and separation of input and output
signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.1 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typically ±310 mV across a termination resistor at the receiving end.
This is converted back to a TTL/CMOS logic level by an LVD S
receiver, such as the ADN4668.
Information furnished
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without noti ce. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADN4667 also offers active high and active low enable/
disable inputs (EN and
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The ADN4667 and its companion LVDS receiver, the ADN4668,
offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic
(ECL) or positive emitter-coupled logic (PECL).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
EN
). These inputs control all four drivers
www.analog.com
ADN4667 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
REVISION HISTORY
3/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 13
Added Automotive Products Section........................................... 13
5/08—Rev. 0 to Rev. A
Added 16-Lead SOIC_N Package .................................... Universal
Changes to Table 3 ............................................................................ 6
Changes to Applications Information section ............................ 11
Updated Outline Dimensions ...................................................... 11
Changes to Ordering Guide .......................................................... 12
1/08—Revision 0: Initial Version
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Enable Inputs .............................................................................. 11
Applications Information .......................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
Automotive Products ................................................................. 13
Rev. B | Page 2 of 16
Data Sheet ADN4667
1, 2
LVDS OUTPUTS (D
OUT+
, D
OUT−
)
Output High Voltage
VOH 1.33
1.6 V See Figure 2 and Figure 4
Input High Voltage
VIH
2.0 VCC V
OUT+
OUT−
IN
OUT−
OSD
OUT+
OUT−
CC
CC
OUT+
OUT−
OUT+
OUT−
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications T
for V
= +3.3 V, TA = +25°C.
CC
Table 1.
Parameter Symbol Min Typ Max Unit Conditions/Comments
MIN
to T
, unless otherwise noted. All typical values are given
MAX
Differential Output Voltage
VOD 250 310 450 mV See Figure 2 and Figure 4
Change in Magnitude of VOD for Complementary Output States ΔVOD 1 35 |mV| See Figure 2 and Figure 4
Offset Voltage VOS 1.125 1.17 1.375 V See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary Output States ΔVOS 1 25 |mV| See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.02 V See Figure 2 and Figure 4
INPUTS (DIN, EN, EN)
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 +2 +10 μA VIN = VCC or 2.5 V
Input Low Current IIL −10 +2 +10 μA VIN = GND or 0.4 V
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current
, D
3
)
IOS −4.2 −9.0 mA Enabled, DIN = VCC, D
OUT+
or
Differential Output Short-Circuit Current3 I
LVDS OUTPUT LEAKAGE (D
, D
)
Power-Off Leakage I
= GND, D
D
−4.2 −9.0 mA Enabled, VOD = 0 V
−20 ±1 +20 μA V
OFF
= 0 V or 3.6 V, VCC = 0 V or
OUT
= 0 V
open
Output Three-State Current IOZ −10 ±1 +10 μA EN = 0.8 V and EN = 2.0 V, V
= 0 V
or V
POWER SUPPLY
No Load Supply Current, Drivers Enabled
Loaded Supply Current, Drivers Enabled I
ICC 4.0 8.0 mA DIN = VCC or GND
20 30 mA RL = 100 Ω all channels, DIN =
CCL
V
CC
or GND (all inputs)
No Load Supply Current, Drivers Disabled I
2.2 6.0 mA DIN = VCC or GND, EN = GND, EN
CCZ
= V
ESD PROTECTION
D
, D
±15 kV Human body model
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4667 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
, D
±4 kV Human body model
= 0 V
OUT
Rev. B | Page 3 of 16
ADN4667 Data Sheet
3, 4
PHLD
PLHD
PHLD
PLHD
SKD1
SKD2
SKD3
SKD4
8
PHZ
PLZ
Enable Time Inactive to High, t
PZH
3 7
ns
See Figure 5 and Figure 6
PZL
MAX
9
07032-002
R
L
/2
R
L
/2
D
IN
D
OUT+
D
OUT–
V
CC
V
OSVOD
DRIVER IS ENABLED
V
V
07032-003
C
L
C
L
D
IN
D
OUT+
D
OUT–
DRIVER IS
ENABLED
NOTES
1. C
L
INCLUDES LOAD AND TEST JI G CAPACITANCE.
SIGNAL
GENERATOR
V
CC
50Ω
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; C
for V
= +3.3 V, TA = +25°C.
CC
Table 2.
Parameter2 Min Typ Max Unit Conditions/Comments
Differential Propagation Delay, High to Low, t
Differential Propagation Delay, Low to High, t
Differential Pulse Skew |t
Channel-to-Channel Skew, t
Differential Part-to-Part Skew, t
Differential Part-to-Part Skew, t
Rise Time, tr 0.5 1.5 ns See Figure 3 and Figure 4
Fall Time, tf 0.5 1.5 ns See Figure 3 and Figure 4
Disable Time High to Inactive, t
Disable Time Low to Inactive, t
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted. All typical values are given
MAX
0.5 0.9 1.7 ns See Figure 3 and Figure 4
0.5 1.2 1.7 ns See Figure 3 and Figure 4
− t
6
0 0.4 0.5 ns See Figure 3 and Figure 4
5
|, t
0 0.3 0.4 ns See Figure 3 and Figure 4
7
0 1.0 ns See Figure 3 and Figure 4
0 1.2 ns See Figure 3 and Figure 4
2 5 ns See Figure 5 and Figure 6
2 5 ns See Figure 5 and Figure 6
Enable Time Inactive to Low, t
Maximum Operating Frequency, f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
is the differential channel-to-channel skew of any event on the same device.
SKD2
7
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same V
8
t
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
SKD4
temperatures and voltage ranges, and across process distribution. t
9
f
generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
MAX
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
PLHD
3 7 ns See Figure 5 and Figure 6
200 250 MHz See Figure 5 and Figure 6
and within 5°C of each other within the operating temperature range.
CC
is defined as |maximum − minimum| differential propagation delay.
SKD4
Test Circuits and Timing Diagrams
Figure 2. Test Circuit for Driver V
OD
and V
OS
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
Rev. B | Page 4 of 16
Data Sheet ADN4667
V
V
D
IN
3
1.5V
0V
D
D
OUT–
OUT+
V
DIFF
t
PLHD
V
OD
V
= D
DIFF
OUT+–DOUT–
t
TLH
t
PHLD
V
OH
0V (DIFFERENTIAL)
V
OL
80%
0V
20%
t
THL
7032-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
D
1.2V
D
OUT+
OUT–
07032-005
SIGNAL
GENERATOR
50Ω
C
L
V
CC
D
IN
EN
EN
50Ω
50Ω
C
L
Figure 5. Test Circuit for Driver Three-State Delay
EN WITH EN = GND
OR OPEN CIRCUIT
3
1.5V
0V
3V
EN WITH EN = V
CC
1.5V
0V
t
PZH
V
OH
50%
OR D
D
WITH DIN = V
OUT+
WITH DIN = GND
OUT–
t
PHZ
CC
1.2V
1.2V
OR D
D
OUT+
OUT–
WITH DIN= GND
WITH DIN= V
CC
t
PLZ
50%
V
t
PZL
OL
07032-006
Figure 6. Driver Three-State Delay Waveforms
Rev. B | Page 5 of 16
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