Differential Line Driver
ADN4667
Rev. B
by Analog Devices is believed to be accurate and reliable. However, no
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
07032-001
ADN4667
D
OUT1+
D
OUT1–
D
IN1
D
OUT2+
D
OUT2–
D
IN2
D
OUT3+
D
OUT3–
D
IN3
D
OUT4+
D
OUT4–
D
IN4
EN
EN
GND
D4
D3
D2
D1
V
CC
Data Sheet
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
Flow through pinout simplifies PCB layout
300 ps typical differential skew
400 ps maximum differential skew
1.7 ns maximum propagation delay
3.3 V power supply
±310 mV differential signaling
Low power dissipation (10 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) and low profile
TSSOP package
Qualified for automotive applications
3 V LVDS Quad CMOS
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4667 is a quad, CMOS, low voltage differential signaling
(LVDS) line driver offering data rates of over 400 Mbps (200 MHz)
and ultralow power consumption. It features a flow through
pinout for easy PCB layout and separation of input and output
signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.1 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typically ±310 mV across a termination resistor at the receiving end.
This is converted back to a TTL/CMOS logic level by an LVD S
receiver, such as the ADN4668.
Information furnished
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without noti ce. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADN4667 also offers active high and active low enable/
disable inputs (EN and
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The ADN4667 and its companion LVDS receiver, the ADN4668,
offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic
(ECL) or positive emitter-coupled logic (PECL).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
EN
). These inputs control all four drivers
www.analog.com
ADN4667 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
REVISION HISTORY
3/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 13
Added Automotive Products Section........................................... 13
5/08—Rev. 0 to Rev. A
Added 16-Lead SOIC_N Package .................................... Universal
Changes to Table 3 ............................................................................ 6
Changes to Applications Information section ............................ 11
Updated Outline Dimensions ...................................................... 11
Changes to Ordering Guide .......................................................... 12
1/08—Revision 0: Initial Version
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Enable Inputs .............................................................................. 11
Applications Information .......................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
Automotive Products ................................................................. 13
Rev. B | Page 2 of 16
Data Sheet ADN4667
1, 2
LVDS OUTPUTS (D
OUT+
, D
OUT−
)
Output High Voltage
VOH 1.33
1.6 V See Figure 2 and Figure 4
Input High Voltage
VIH
2.0 VCC V
OUT+
OUT−
IN
OUT−
OSD
OUT+
OUT−
CC
CC
OUT+
OUT−
OUT+
OUT−
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications T
for V
= +3.3 V, TA = +25°C.
CC
Table 1.
Parameter Symbol Min Typ Max Unit Conditions/Comments
MIN
to T
, unless otherwise noted. All typical values are given
MAX
Differential Output Voltage
VOD 250 310 450 mV See Figure 2 and Figure 4
Change in Magnitude of VOD for Complementary Output States ΔVOD 1 35 |mV| See Figure 2 and Figure 4
Offset Voltage VOS 1.125 1.17 1.375 V See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary Output States ΔVOS 1 25 |mV| See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.02 V See Figure 2 and Figure 4
INPUTS (DIN, EN, EN)
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 +2 +10 μA VIN = VCC or 2.5 V
Input Low Current IIL −10 +2 +10 μA VIN = GND or 0.4 V
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current
, D
3
)
IOS −4.2 −9.0 mA Enabled, DIN = VCC, D
OUT+
or
Differential Output Short-Circuit Current3 I
LVDS OUTPUT LEAKAGE (D
, D
)
Power-Off Leakage I
= GND, D
D
−4.2 −9.0 mA Enabled, VOD = 0 V
−20 ±1 +20 μA V
OFF
= 0 V or 3.6 V, VCC = 0 V or
OUT
= 0 V
open
Output Three-State Current IOZ −10 ±1 +10 μA EN = 0.8 V and EN = 2.0 V, V
= 0 V
or V
POWER SUPPLY
No Load Supply Current, Drivers Enabled
Loaded Supply Current, Drivers Enabled I
ICC 4.0 8.0 mA DIN = VCC or GND
20 30 mA RL = 100 Ω all channels, DIN =
CCL
V
CC
or GND (all inputs)
No Load Supply Current, Drivers Disabled I
2.2 6.0 mA DIN = VCC or GND, EN = GND, EN
CCZ
= V
ESD PROTECTION
D
, D
±15 kV Human body model
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4667 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
, D
±4 kV Human body model
= 0 V
OUT
Rev. B | Page 3 of 16
ADN4667 Data Sheet
3, 4
PHLD
PLHD
PHLD
PLHD
SKD1
SKD2
SKD3
SKD4
8
PHZ
PLZ
Enable Time Inactive to High, t
PZH
3 7
ns
See Figure 5 and Figure 6
PZL
MAX
9
07032-002
R
L
/2
R
L
/2
D
IN
D
OUT+
D
OUT–
V
CC
V
OSVOD
DRIVER IS ENABLED
V
V
07032-003
C
L
C
L
D
IN
D
OUT+
D
OUT–
DRIVER IS
ENABLED
NOTES
1. C
L
INCLUDES LOAD AND TEST JI G CAPACITANCE.
SIGNAL
GENERATOR
V
CC
50Ω
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; C
for V
= +3.3 V, TA = +25°C.
CC
Table 2.
Parameter2 Min Typ Max Unit Conditions/Comments
Differential Propagation Delay, High to Low, t
Differential Propagation Delay, Low to High, t
Differential Pulse Skew |t
Channel-to-Channel Skew, t
Differential Part-to-Part Skew, t
Differential Part-to-Part Skew, t
Rise Time, tr 0.5 1.5 ns See Figure 3 and Figure 4
Fall Time, tf 0.5 1.5 ns See Figure 3 and Figure 4
Disable Time High to Inactive, t
Disable Time Low to Inactive, t
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted. All typical values are given
MAX
0.5 0.9 1.7 ns See Figure 3 and Figure 4
0.5 1.2 1.7 ns See Figure 3 and Figure 4
− t
6
0 0.4 0.5 ns See Figure 3 and Figure 4
5
|, t
0 0.3 0.4 ns See Figure 3 and Figure 4
7
0 1.0 ns See Figure 3 and Figure 4
0 1.2 ns See Figure 3 and Figure 4
2 5 ns See Figure 5 and Figure 6
2 5 ns See Figure 5 and Figure 6
Enable Time Inactive to Low, t
Maximum Operating Frequency, f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
is the differential channel-to-channel skew of any event on the same device.
SKD2
7
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same V
8
t
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
SKD4
temperatures and voltage ranges, and across process distribution. t
9
f
generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
MAX
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
PLHD
3 7 ns See Figure 5 and Figure 6
200 250 MHz See Figure 5 and Figure 6
and within 5°C of each other within the operating temperature range.
CC
is defined as |maximum − minimum| differential propagation delay.
SKD4
Test Circuits and Timing Diagrams
Figure 2. Test Circuit for Driver V
OD
and V
OS
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
Rev. B | Page 4 of 16
Data Sheet ADN4667
V
V
D
IN
3
1.5V
0V
D
D
OUT–
OUT+
V
DIFF
t
PLHD
V
OD
V
= D
DIFF
OUT+–DOUT–
t
TLH
t
PHLD
V
OH
0V (DIFFERENTIAL)
V
OL
80%
0V
20%
t
THL
7032-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
D
1.2V
D
OUT+
OUT–
07032-005
SIGNAL
GENERATOR
50Ω
C
L
V
CC
D
IN
EN
EN
50Ω
50Ω
C
L
Figure 5. Test Circuit for Driver Three-State Delay
EN WITH EN = GND
OR OPEN CIRCUIT
3
1.5V
0V
3V
EN WITH EN = V
CC
1.5V
0V
t
PZH
V
OH
50%
OR D
D
WITH DIN = V
OUT+
WITH DIN = GND
OUT–
t
PHZ
CC
1.2V
1.2V
OR D
D
OUT+
OUT–
WITH DIN= GND
WITH DIN= V
CC
t
PLZ
50%
V
t
PZL
OL
07032-006
Figure 6. Driver Three-State Delay Waveforms
Rev. B | Page 5 of 16
ADN4667 Data Sheet
OUT+
OUT−
OUT+
OUT−
Industrial Operating Temperature Range
−40°C to +85°C
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC to GND −0.3 V to +4 V
Input Voltage (DIN) to GND −0.3 V to VCC + 0.3 V
Enable Input Voltage (EN, EN) to GND −0.3 V to VCC + 0.3 V
Output Voltage (D
Short-Circuit Duration (D
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance
TSSOP Package 150.4°C/W
SOIC Package 125°C/W
Reflow Soldering Peak Temperature (10sec) 260°C max
, D
) to GND −0.3 V to VCC + 0.3 V
, D
) to GND Continuous
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 16
Data Sheet ADN4667
IN1
IN2
6
D
IN3
Driver Channel 3 Logic Input.
IN4
OUT4−
OUT4+
OUT3+
OUT3−
OUT2−
OUT2+
OUT1+
OUT1−
07032-007
NC = NO CONNECT
1
2
3
4
5
6
7
8
D
IN1
D
IN2
V
CC
D
IN4
D
IN3
GND
EN
EN
16
15
14
13
12
11
10
9
D
OUT1+
D
OUT2+
D
OUT2–
D
OUT4+
D
OUT4–
D
OUT3+
D
OUT3–
D
OUT1–
ADN4667
TOP VIEW
(Not to S cale)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 7. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Active High Enable and Power-Down Input (3 V TTL/CMOS). If EN is held low or open circuit, EN enables the
drivers when high and disables the drivers when low.
2 D
3 D
Driver Channel 1 Logic Input.
Driver Channel 2 Logic Input.
4 VCC Power Supply Input. These parts can be operated from 3.0 V to 3.6 V. The supply should be decoupled with a
10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
5 GND Ground Reference Point for All Circuitry on the Part.
7 D
8
Driver Channel 4 Logic Input.
Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). If EN is held high, EN enables the
EN
drivers when low or open circuit and disables the drivers and powers down the device when high.
9 D
10 D
11 D
12 D
13 D
14 D
15 D
16 D
Channel 4 Inverting Output Current Driver. When D
OUT4−
Channel 4 Noninverting Output Current Driver. When D
OUT4+
Channel 3 Noninverting Output Current Driver. When D
OUT3+
Channel 3 Inverting Output Current Driver. When D
OUT3−
Channel 2 Inverting Output Current Driver. When D
OUT2−
Channel 2 Noninverting Output Current Driver. When D
OUT2+
Channel 1 Noninverting Output Current Driver. When D
OUT1+
Channel 1 Inverting Output Current Driver. When D
OUT1−
flows out of D
current flows into D
current flows into D
flows out of D
flows out of D
current flows into D
current flows into D
flows out of D
.
.
.
.
.
.
.
.
is high, current flows into D
IN4
is high, current flows out of D
IN4
is high, current flows out of D
IN3
is high, current flows into D
IN3
is high, current flows into D
IN2
is high, current flows out of D
IN2
is high, current flows out of D
IN1
is high, current flows into D
IN1
OUT4−
OUT3−
OUT2−
OUT1−
. When D
. When D
OUT4+
. When D
OUT3+
.When D
. When D
. When D
OUT2+
. When D
OUT1+
. When D
is low, current
IN4
is low,
IN4
is low,
IN3
is low, current
IN3
is low, current
IN2
is low,
IN2
is low,
IN1
is low, current
IN1
Rev. B | Page 7 of 16
ADN4667 Data Sheet
07032-008
1.415
1.414
1.413
1.412
3.0 3.1 3.2 3.3 3.4 3.5 3.6
OUTPUT HIGH VOLTAGE, V
OH
(V)
POWER SUPPLY VOLTAGE, VCC (V)
T
A
= 25°C
R
L
= 100Ω
07032-009
1.090
1.089
1.088
1.087
3.0 3.1 3.2 3.3 3.4 3.5 3.6
OUTPUT LOW VOLTAGE, V
OL
(V)
POWER SUPPLY VOLTAGE, VCC (V)
TA = 25°C
R
L
= 100Ω
07032-010
–3.9
–4.0
–4.1
–4.2
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SHORT-CI RCUIT CURRENT, I
OS
(mA)
POWER SUPPLY VOLTAGE, VCC (V)
TA = 25°C
V
IN
= GND OR V
CC
V
OUT
= 0V
07032-011
440
360
380
400
420
340
3.0 3.1 3.2 3.3 3.4 3.5 3.6
OUTPUT THREE-STAT E CURRE NT, I
OZ
(pA)
POWER SUPPLY VOLTAGE, V
CC
(V)
T
A
= 25°C
V
IN
= GND OR V
CC
07032-012
325.0
324.2
324.4
324.6
324.8
324.0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
DIFFERENTIAL OUTPUT VOLTAGE, V
OD
(mV)
POWER SUPPLY VOLTAGE, VCC (V)
TA = 25°C
R
L
= 100Ω
07032-013
500
300
350
400
450
250
90 100 110 120 130 140 150
DIFFERENTIAL OUTPUT VOLTAGE, V
OD
(mV)
LOAD RESISTOR, RL (Ω)
TA = 25°C
V
CC
= 3.3V
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Output High Voltage vs. Power Supply Voltage
Figure 9. Output Low Voltage vs. Power Supply Voltage
Figure 11. Output Three-State Current vs. Power Supply Voltage
Figure 12. Differential Output Voltage vs. Power Supply Voltage
Figure 10. Output Short-Circuit Current vs. Power Supply Voltage
Figure 13. Differential Output Voltage vs. Load Resistor
Rev. B | Page 8 of 16
Data Sheet ADN4667
07032-014
1.252
1.250
1.251
1.249
3.0 3.1 3.2 3.3 3.4 3.5 3.6
OFFSET VOLTAGE, V
OS
(mV)
POWER SUPPLY VOLTAGE, VCC (V)
TA = 25°C
R
L
= 100Ω
07032-015
26
16
18
20
22
24
14
0.1 1 10 100 500
POWER SUP P LY CURRENT, I
CC
(mA)
SWITCHING FREQUE NCY (MHz)
TA = 25°C
C
L
= 15pF
V
CC
= 3.3V
V
IN
= 0V TO 3V
R
L
= 100Ω PER DRIVER
ALL CHANNELS S WITCHING
ONE CHANNEL SWITCHING
07032-016
14.925
14.915
14.920
14.910
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUP P LY CURRENT, I
CC
(mA)
POWER SUPPLY VOLTAGE, VCC (V)
TA = 25°C
f = 1MHz
C
L
= 15pF
V
IN
= 0V TO 3V
R
L
= 100Ω PER DRIVER
07032-017
14.92
14.89
14.90
14.91
14.88
–40 –20 0 20 40 60 80 100
POWER SUP P LY CURRENT, I
CC
(mA)
AMBIENT T E M P E RATURE, T
A
(°C)
V
CC
= 3.3V
f = 1MHz
C
L
= 15pF
V
IN
= 0V TO 3V
R
L
= 100Ω PER DRIVER
07032-018
1200
1000
1100
900
3.0 3.1 3.2 3.3 3.4 3.5 3.6
DIFFERENTIAL PROPAGATION DELAY (ns)
POWER SUPPLY VOLTAGE, VCC (V)
t
PHLD
t
PLHD
TA = 25°C
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
07032-019
1200
1000
1100
900
DIFFERENTIAL PROPAGATION DELAY (ns)
AMBIENT T E M P E RATURE, TA (°C)
t
PHLD
t
PLHD
–40 –20 0 20 40 60 80 100
VCC = 3.3V
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
Figure 14. Offset Voltage vs. Power Supply Voltage
Figure 15.Power Supply Current vs. Switching Frequency
Figure 17. Power Supply Current vs. Ambient Temperature
Figure 18. Differential Propagation Delay vs. Power Supply Voltage
Figure 16. Power Supply Current vs. Power Supply Voltage
Figure 19. Differential Propagation Delay vs. Ambient Temperature
Rev. B | Page 9 of 16
ADN4667 Data Sheet
07032-020
100
20
40
60
80
0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
DIFFERENTIAL SKEW, t
SKD
(ps)
POWER SUPPLY VOLTAGE, V
CC
(V)
TA = 25°C
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
07032-021
50
10
20
30
40
0
DIFFERENTIAL SKEW, t
SKD
(ps)
AMBIENT T E M P E RATURE, TA (°C)
–40 –20 0 20 40 60 80 100
VCC = 3.3V
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
07032-022
400
340
360
380
320
3.0 3.1 3.2 3.3 3.4 3.5 3.6
TRANSITION TIME (ps)
POWER SUPPLY VOLTAGE, V
CC
(V)
T
A
= 25°C
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
t
TLH
t
THL
07032-023
400
340
360
380
320
TRANSITION TIME (ps)
AMBIENT T E M P E RATURE, TA (°C)
–40 –20 0 20 40 60 80 100
t
TLH
t
THL
V
CC
= 3.3V
f = 1MHz
C
L
= 15pF
R
L
= 100Ω PER DRIVER
Figure 20. Differential Skew vs. Supply Voltage
Figure 21. Differential Skew vs. Ambient Temperature
Figure 22. Transition Time vs. Supply Voltage
Figure 23. Transition Time vs. Ambient Temperature
Rev. B | Page 10 of 16
Data Sheet ADN4667
THEORY OF OPERATION
The ADN4667 is a quad line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted pair
cable or PCB backplane, to an LVDS receiver like the ADN4668,
where it develops a voltage across a terminating resistor, R
. This
T
resistor is chosen to match the characteristic impedance of the
medium, typically around 100 Ω. The differential voltage is
detected by the receiver and converted back into a single-ended
logic signal.
When D
pin (current source) through R
is high (Logic 1), current flows out of the D
IN
and back into the D
T
OUT−
OUT+
pin
(current sink). At the receiver, this current develops a positive
differential voltage across R
and gives a Logic 1 at the receiver output. When D
sinks current and D
D
OUT+
tial voltage across R
(with respect to the inverting input)
T
is low,
IN
sources current; a negative differen-
OUT−
gives a Logic 0 at the receiver output.
T
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.1 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor. The received voltage is centered
around the receiver offset of 1.2 V. Therefore, the noninverting
receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the
inverting receiver input is (1.2 V − [310 mV/2]) = 1.045 V for
Logic 1. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across R
is
T
twice the differential voltage.
Current mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas that of voltage mode drivers increase
exponentially in most cases. This is caused by the overlap as
internal gates switch between high and low, which causes
currents to flow from the device power supply to ground.
A current mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
ENABLE INPUTS
The active high and active low enable inputs deactivate all the
current drivers when in the disabled state. This also powers
down the device and reduces the current consumption from
typically 20 mA to typically 2.2 mA. A truth table for the enable
inputs is shown in Table 5.
Table 5. Enable Inputs Truth Table
EN
H L or open L I
H L or open H I
Any other combination of EN and EN
D
EN
D
IN
SINK
SOURCE
D
OUT+
I
I
X Inactive Inactive
OUT−
SOURCE
SINK
APPLICATIONS INFORMATION
Figure 24 shows a typical application for point-to-point data
transmission using the ADN4667 as the driver and the
ADN4668 as the receiver.
EN
EN
D
IN
1/4 ADN4667
Figure 24. Typical Application Circuit
D
D
OUT+
OUT–
R
R
T
100Ω
R
IN+
IN–
1/4 ADN4668
GNDGND
EN
EN
D
OUT
07032-024
Rev. B | Page 11 of 16
ADN4667 Data Sheet
CONTROLLING DIMENSIONSARE IN MILLIM E TERS; INCH DIM E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE O NLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16
9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
16
9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLI ANT TO JEDEC STANDARDS MO-153-AB
OUTLINE DIMENSIONS
Figure 25. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. B | Page 12 of 16
Data Sheet ADN4667
Model
1, 2
Temperature Range
Package Description
Package Option
ORDERING GUIDE
ADN4667ARZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADN4667ARZ-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADN4667ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADN4667ARUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADN4667WARZ-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications
AUTOMOTIVE PRODUCTS
The ADN4667W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
Rev. B | Page 13 of 16
ADN4667 Data Sheet
NOTES
Rev. B | Page 14 of 16
Data Sheet ADN4667
NOTES
Rev. B | Page 15 of 16
ADN4667 Data Sheet
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
NOTES
registered trademarks are the property of their respective owners.
D07032-0-3/12(B)
Rev. B | Page 16 of 16
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