ANALOG DEVICES ADN4666 Service Manual

3 V, LVDS, Quad CMOS

FEATURES

±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins
400 Mbps (200 MHz) switching rates
100 ps channel-to-channel skew (typical)
100 ps differential skew (typical)

3.3 ns propagation delay (maximum)

3.3 V power supply
High impedance outputs on power-down
Low power design (10 mW quiescent typical)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (350 mV typical) differential

input signal levels
Supports open, short, and terminated input fail-safe
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range of −40°C to +85°C
Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers

Differential Line Receiver

ADN4666

FUNCTIONAL BLOCK DIAGRAM

V
R

R

R

EN

R

R
R

CC

IN4–
IN4+

OUT4

OUT3

IN3+
IN3–

08097-001

ADN4666

R

IN1–

R

IN1+

R4

R1

R

OUT1

EN

R

OUT2

R3

R2

R

IN2+

R

IN2–

GND

Figure 1.

GENERAL DESCRIPTION

The ADN4666 is a quad-channel, CMOS low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.

The device accepts low voltage (350 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.

The ADN4666 also offers active high and active low enable/disable
inputs (EN and

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

EN

) that control all four receivers. These inputs

disable the receivers and switch the outputs to a high impedance
state. Consequently, the outputs of one or more ADN4666
devices can be multiplexed together to reduce the quiescent
power consumption to 10 mW typical.

The ADN4666 and its companion driver, the ADN4665, offer
a new solution to high speed, point-to-point data transmission
and offer a low power alternative to emitter-coupled logic (ECL)
or positive emitter-coupled logic (PECL).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADN4666

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

6/09—Revision 0: Initial Version

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation .........................................................................9

Enable Inputs .................................................................................9

Applications Information .............................................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. 0 | Page 2 of 12

ADN4666

SPECIFICATIONS

VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

LVDS INPUTS (R

Differential Input High Threshold at R

Differential Input Low Threshold at R

Common-Mode Voltage Range at R

Input Current at R

INx+

, R

INx−

INx+

)

, R

INx+

, R

INx+

, R

INx+

INx−

, R

IIN −10 ±5 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V

INx−

3

VTH 20 100 mV VCM = 1.2 V, 0.05 V, 2.95 V

INx−

3

V

INx−

4

−100 −20 mV VCM = 1.2 V, 0.05 V, 2.95 V

TL

V

0.1 2.3 V VID = 200 mV p-p

CMR

−10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V

−20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input Current IIN −10 ±1 +10 μA VIN = 0 V or VCC, other input = VCC or GND
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA

OUTPUTS (R

)

OUTx

Output High Voltage VOH 2.7 3.0 V IOH = −0.4 mA, VID = 200 mV

2.7 3.0 V IOH = −0.4 mA, input terminated

2.7 3.0 V IOH = −0.4 mA, input shorted
Output Low Voltage VOL 0.1 0.25 V IOL = 2 mA, VID = −200 mV
Output Short-Circuit Current

5

IOS −15 −48 −120 mA Outputs enabled, V

Output Off State Current IOZ −10 ±1 +10 μA Outputs disabled, V

POWER SUPPLY

No Load Supply, Current Receivers Enabled ICC 10 15 mA
No Load Supply, Current Receivers Disabled I

3 5 mA

CCZ

ESD PROTECTION

R

, R

INx+

Pins ±8 kV IEC 61000-4-2 contact discharge

INx−

±15 kV Human body model
All Pins Except R

1

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.

2

All typical values are given for VCC = 3.3 V and TA = 25°C.

3

VCC is always higher than the R

common-mode voltage range is 0.1 V to 2.3 V.

4

V

is reduced for larger input differential voltage (VID). For example, if VID is 400 mV, V

CMR

over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external common-mode voltage applied. VID up to VCC − 0 V can be
applied to the R
400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common-mode range.

5

Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Note that only one output should be shorted at a time; do not

exceed the maximum junction temperature specification (150°C).

, R

INx+

INx+/RINx−

±4 kV Human body model

INx−

and R

INx+

inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to

voltage. R

INx−

INx−

and R

have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the

INx+

is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported

CMR

1, 2

EN and EN
EN = GND and EN

= 0 V

OUT

= 0 V or VCC

OUT

= VCC or GND, inputs open

= VCC, inputs open

Rev. 0 | Page 3 of 12

ADN4666

V

TIMING SPECIFICATIONS

VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications T

MIN

to T

, unless otherwise noted.1

MAX

Table 2.

Parameter

2

Symbol Min Typ3Max Unit Test Conditions/Comments

4, 5

AC CHARACTERISTICS

Differential Propagation Delay, High to Low t
Differential Propagation Delay, Low to High t
Differential Pulse Skew6 |t
Differential Channel-to-Channel Skew

(Same Device)

7

Differential Part-to-Part Skew
Differential Part-to-Part Skew

PHLD

− t

8

9

| t

PLHD

Rise Time t
Fall Time t
Disable Time, High to Z t
Disable Time, Low to Z t
Enable Time, Z to High t
Enable Time, Z to Low t
Maximum Operating Frequency

1

Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, t

2

AC parameters are guaranteed by design and characterization.

3

All typical values are given for VCC = 3.3 V and TA = 25°C.

4

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.

5

CL includes load and jig capacitance.

6

t

is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.

SKD1

7

Channel-to-channel skew, t

the inputs.

8

t

part-to-part skew is the differential channel-to-channel skew of any event between devices. The t

SKD3

5°C of each other within the operating temperature range.

9

t

part-to-part skew is the differential channel-to-channel skew of any event between devices. The t

SKD4

operating temperature and voltage ranges and across process distribution. t

10

f

generator input conditions: f = 200 MHz, t

MAX

duty cycle, VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), and load = 15 pF (stray plus probes).

SKD2

10

, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on

= t

TLH

THL

1.8 3.3 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

PHLD

1.8 3.3 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

PLHD

0 0.1 0.35 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

SKD1

t

0 0.1 0.5 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

SKD2

t

1.0 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

SKD3

t

1.5 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

SKD4

0.35 1.2 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

TLH

0.35 1.2 ns CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

THL

8 12 ns RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

PHZ

8 12 ns RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

PLZ

11 17 ns RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

PZH

11 17 ns RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

PZL

f

200 250 MHz All channels switching

MAX

and t

TLH

is defined as |maximum − minimum| differential propagation delay.

SKD4

(0% to 100%) ≤ 3 ns for R

THL

specification applies to devices at the same VCC and within

SKD3

specification applies to devices over the recommended

SKD4

< 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V p-p). f

INx+/RINx−

.

generator output criteria: 60%/40%

MAX

Test Circuits and Timing Diagrams

CC

R

SIGNAL

GENERATOR

50Ω 50Ω

NOTES

= LOAD AND TEST JIG CAPACITANCE.

1. C

L

INx+

R

INx–

RECEIVER

IS ENABLED

R

OUTx

C

L

08097-002

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

Rev. 0 | Page 4 of 12