ANALOG DEVICES ADN4665 Service Manual
3 V, LVDS, Quad, CMOS
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
100 ps typical differential skew
400 ps maximum differential skew
2 ns maximum propagation delay
3.3 V power supply
±350 mV differential signaling
Low power dissipation (13 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
Differential Line Driver
ADN4665
FUNCTIONAL BLOCK DIAGRAM
V
D
D
D
EN
D
D
D
CC
IN4
OUT4+
OUT4–
OUT3–
OUT3+
IN3
08085-001
D
D
D
D
D
OUT1+
OUT1–
OUT2–
OUT2+
D
GND
IN1
EN
IN2
ADN4665
D4
D1
D3
D2
Figure 1.
GENERAL DESCRIPTION
The ADN4665 is a quad-channel, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.5 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typically ±350 mV across a termination resistor at the receiving end.
This voltage is converted back to a TTL/CMOS logic level by an
LVDS rec e iver.
The ADN4665 also offers active high and active low enable/
disable inputs (EN and
EN
). These inputs control all four drivers
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The ADN4665 offers a new solution to high speed, point-to-point
data transmission and offers a low power alternative to emittercoupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADN4665
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 6
REVISION HISTORY
5/09—Revision 0: Initial Version
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation .........................................................................9
Enable Inputs .................................................................................9
Applications Information .............................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
Rev. 0 | Page 2 of 12
ADN4665
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL = 15 pF to GND, all specifications T
for V
= 3.3 V, TA = 25°C.
CC
MIN
to T
, unless otherwise noted. All typical values are given
MAX
Table 1.
Parameter Symbol Min Typ Max Unit Conditions/Comments
LVDS OUT PUTS (D
OUTx+
, D
)
OUTx−
Differential Output Voltage VOD 250 350 450 mV See Figure 2 and Figure 4
Change in Magnitude of VOD for Complementary Output States ΔVOD 4 35 |mV| See Figure 2 and Figure 4
Offset Voltage VOS 1.125 1.25 1.375 V See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary Output States ΔVOS 5 25 |mV| See Figure 2 and Figure 4
Output High Voltage VOH 1.38 1.6 V See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.03 V See Figure 2 and Figure 4
INPUTS (D
, EN, EN)
INx
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 +1 +10 μA VIN = VCC or 2.5 V
Input Low Current IIL −10 +1 +10 μA VIN = GND or 0.4 V
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current
Differential Output Short-Circuit Current
LVDS OUTPUT LEAKAGE (D
Power-Off Leakage I
OUTx+
, D
OUTx+
3
, D
)
OUTx−
IOS −6.0 −9.0 mA
3
I
)
OUTx−
−6.0 −9.0 mA Enabled, VOD = 0 V
OSD
−20 ±1 +20 μA
OFF
Enabled, D
or D
INx
= 0 V or 3.6 V, VCC = 0 V or
V
OUT
= VCC, D
INx
= GND, D
OUTx−
OUTx+
= 0 V
open
Output Three-State Current IOZ −10 ±1 +10 μA
EN = 0.8 V, EN
V
= 0 V or VCC
OUT
= 2.0 V,
POWER SUPPLY
No Load Supply Current, Drivers Enabled ICC 5.0 8.0 mA D
Loaded Supply Current, Drivers Enabled I
No Load Supply Current, Drivers Disabled I
23 30 mA
CCL
2.6 6.0 mA
CCZ
= VCC or GND
INx
= 100 Ω all channels,
R
L
= VCC or GND (all inputs)
D
INx
= VCC or GND, EN = GND,
D
INx
= VCC
EN
ESD PROTECTION
D
, D
OUTx+
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4665 is a current-mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Pins ±15 kV Human body model
OUTx−
, D
OUTx+
±4.5 kV Human body model
OUTx−
1, 2
= 0 V
Rev. 0 | Page 3 of 12
ADN4665
V
TIMING CHARACTERISTICS
VCC = 3.0 V to 3.6 V, RL = 100 Ω, C
for V
= 3.3 V, TA = 25°C.
CC
1
= 15 pF to GND, all specifications T
L
MIN
to T
, unless otherwise noted. All typical values are given
MAX
Table 2.
Parameter
2
Symbol Min Typ Max Unit Conditions/Comments
3, 4
AC CHARACTERISTICS
Differential Propagation Delay, High to Low t
Differential Propagation Delay, Low to High t
Differential Pulse Skew |t
PHLD
− t
PLHD
| t
Channel-to-Channel Skew t
Differential Part-to-Part Skew t
Differential Part-to-Part Skew t
Rise Time t
Fall Time t
Disable Time High to Inactive t
Disable Time Low to Inactive t
Enable Time Inactive to High t
Enable Time Inactive to Low t
Maximum Operating Frequency f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4
All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
is the differential channel-to-channel skew of any event on the same device.
SKD2
7
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8
t
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating
SKD4
temperature and voltage ranges, and across process distribution. t
9
f
generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
MAX
| is the magnitude difference in differential propagation delay time between the positive-going edge and the negative-going edge of the
PLHD
0.8 1.18 2.0 ns See Figure 3 and Figure 4
PHLD
0.8 1.25 2.0 ns See Figure 3 and Figure 4
PLHD
5
SKD1
SKD2
SKD3
SKD4
TLH
THL
PHZ
PLZ
PZH
PZL
MAX
0 0.07 0.4 ns See Figure 3 and Figure 4
6
0 0.1 0.5 ns See Figure 3 and Figure 4
7
0 1.0 ns See Figure 3 and Figure 4
8
0 1.2 ns See Figure 3 and Figure 4
0.38 1.5 ns See Figure 3 and Figure 4
0.4 1.5 ns See Figure 3 and Figure 4
5 ns See Figure 5 and Figure 6
5 ns See Figure 5 and Figure 6
7 ns See Figure 5 and Figure 6
7 ns See Figure 5 and Figure 6
9
200 250 MHz See Figure 5 and Figure 6
is defined as |maximum − minimum| differential propagation delay.
SKD4
Test Circuits and Timing Diagrams
D
OUTx+
V
CC
D
INx
RL/2
R
L
V
V
V
/2
OSVOD
D
NOTES
1. DRIVER IS E NABL E D.
Figure 2. Test Circuit for Driver V
OUTx–
and VOS
OD
08085-002
CC
C
D
SIGNAL
GENERATOR
NOTES
INCLUDES PROBE AND JIG CAPACITANCE.
1. C
L
INx
50Ω
DRIVER IS
ENABLED
L
C
L
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
Rev. 0 | Page 4 of 12
D
OUTx+
D
OUTx–
8085-003
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