ANALOG DEVICES ADN4665 Service Manual

3 V, LVDS, Quad, CMOS

FEATURES

±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
100 ps typical differential skew
400 ps maximum differential skew
2 ns maximum propagation delay

3.3 V power supply
±350 mV differential signaling
Low power dissipation (13 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Backplane data transmission
Cable data transmission
Clock distribution

Differential Line Driver

ADN4665

FUNCTIONAL BLOCK DIAGRAM

V

D

D

D

EN

D

D

D

CC

IN4

OUT4+

OUT4–

OUT3–

OUT3+

IN3

08085-001

D

D

D

D

D

OUT1+

OUT1–

OUT2–

OUT2+

D

GND

IN1

EN

IN2

ADN4665

D4

D1

D3

D2

Figure 1.

GENERAL DESCRIPTION

The ADN4665 is a quad-channel, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.

The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.5 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typi­cally ±350 mV across a termination resistor at the receiving end.
This voltage is converted back to a TTL/CMOS logic level by an
LVDS rec e iver.

The ADN4665 also offers active high and active low enable/
disable inputs (EN and

EN

). These inputs control all four drivers
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.

The ADN4665 offers a new solution to high speed, point-to-point
data transmission and offers a low power alternative to emitter­coupled logic (ECL) or positive emitter-coupled logic (PECL).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADN4665

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

5/09—Revision 0: Initial Version

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation .........................................................................9

Enable Inputs .................................................................................9

Applications Information .............................................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. 0 | Page 2 of 12

ADN4665

SPECIFICATIONS

VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL = 15 pF to GND, all specifications T
for V

= 3.3 V, TA = 25°C.

CC

MIN

to T

, unless otherwise noted. All typical values are given

MAX

Table 1.

Parameter Symbol Min Typ Max Unit Conditions/Comments

LVDS OUT PUTS (D

OUTx+

, D

)

OUTx−

Differential Output Voltage VOD 250 350 450 mV See Figure 2 and Figure 4
Change in Magnitude of VOD for Complementary Output States ΔVOD 4 35 |mV| See Figure 2 and Figure 4
Offset Voltage VOS 1.125 1.25 1.375 V See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary Output States ΔVOS 5 25 |mV| See Figure 2 and Figure 4
Output High Voltage VOH 1.38 1.6 V See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.03 V See Figure 2 and Figure 4

INPUTS (D

, EN, EN)

INx

Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 +1 +10 μA VIN = VCC or 2.5 V
Input Low Current IIL −10 +1 +10 μA VIN = GND or 0.4 V
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA

LVDS OUTPUT PROTECTION (D

Output Short-Circuit Current

Differential Output Short-Circuit Current

LVDS OUTPUT LEAKAGE (D

Power-Off Leakage I

OUTx+

, D

OUTx+

3

, D

)

OUTx−

IOS −6.0 −9.0 mA

3

I

)

OUTx−

−6.0 −9.0 mA Enabled, VOD = 0 V

OSD

−20 ±1 +20 μA

OFF

Enabled, D
or D

INx

= 0 V or 3.6 V, VCC = 0 V or

V

OUT

= VCC, D

INx

= GND, D

OUTx−

OUTx+

= 0 V

open

Output Three-State Current IOZ −10 ±1 +10 μA

EN = 0.8 V, EN
V

= 0 V or VCC

OUT

= 2.0 V,

POWER SUPPLY

No Load Supply Current, Drivers Enabled ICC 5.0 8.0 mA D
Loaded Supply Current, Drivers Enabled I

No Load Supply Current, Drivers Disabled I

23 30 mA

CCL

2.6 6.0 mA

CCZ

= VCC or GND

INx

= 100 Ω all channels,

R

L

= VCC or GND (all inputs)

D

INx

= VCC or GND, EN = GND,

D

INx

= VCC

EN

ESD PROTECTION

D

, D

OUTx+

All Pins Except D

1

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.

2

The ADN4665 is a current-mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is

90 Ω to 110 Ω.

3

Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.

Pins ±15 kV Human body model

OUTx−

, D

OUTx+

±4.5 kV Human body model

OUTx−

1, 2

= 0 V

Rev. 0 | Page 3 of 12

ADN4665

V

TIMING CHARACTERISTICS

VCC = 3.0 V to 3.6 V, RL = 100 Ω, C
for V

= 3.3 V, TA = 25°C.

CC

1

= 15 pF to GND, all specifications T

L

MIN

to T

, unless otherwise noted. All typical values are given

MAX

Table 2.

Parameter

2

Symbol Min Typ Max Unit Conditions/Comments

3, 4

AC CHARACTERISTICS

Differential Propagation Delay, High to Low t
Differential Propagation Delay, Low to High t
Differential Pulse Skew |t

PHLD

− t

PLHD

| t
Channel-to-Channel Skew t
Differential Part-to-Part Skew t
Differential Part-to-Part Skew t
Rise Time t
Fall Time t
Disable Time High to Inactive t
Disable Time Low to Inactive t
Enable Time Inactive to High t
Enable Time Inactive to Low t
Maximum Operating Frequency f

1

CL includes probe and jig capacitance.

2

AC parameters are guaranteed by design and characterization.

3

Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.

4

All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.

5

t

= |t

− t

SKD1

PHLD

same channel.

6

t

is the differential channel-to-channel skew of any event on the same device.

SKD2

7

t

, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

SKD3

applies to devices at the same VCC and within 5°C of each other within the operating temperature range.

8

t

, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating

SKD4

temperature and voltage ranges, and across process distribution. t

9

f

generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.

MAX

| is the magnitude difference in differential propagation delay time between the positive-going edge and the negative-going edge of the

PLHD

0.8 1.18 2.0 ns See Figure 3 and Figure 4

PHLD

0.8 1.25 2.0 ns See Figure 3 and Figure 4

PLHD

5

SKD1

SKD2

SKD3

SKD4

TLH

THL

PHZ

PLZ

PZH

PZL

MAX

0 0.07 0.4 ns See Figure 3 and Figure 4

6

0 0.1 0.5 ns See Figure 3 and Figure 4

7

0 1.0 ns See Figure 3 and Figure 4

8

0 1.2 ns See Figure 3 and Figure 4

0.38 1.5 ns See Figure 3 and Figure 4

0.4 1.5 ns See Figure 3 and Figure 4
5 ns See Figure 5 and Figure 6
5 ns See Figure 5 and Figure 6
7 ns See Figure 5 and Figure 6
7 ns See Figure 5 and Figure 6

9

200 250 MHz See Figure 5 and Figure 6

is defined as |maximum − minimum| differential propagation delay.

SKD4

Test Circuits and Timing Diagrams

D

OUTx+

V

CC

D

INx

RL/2

R

L

V

V

V

/2

OSVOD

D

NOTES

1. DRIVER IS E NABL E D.

Figure 2. Test Circuit for Driver V

OUTx–

and VOS

OD

08085-002

CC

C

D

SIGNAL

GENERATOR

NOTES

INCLUDES PROBE AND JIG CAPACITANCE.

1. C

L

INx

50Ω

DRIVER IS

ENABLED

L

C

L

Figure 3. Test Circuit for Driver Propagation Delay and Transition Time

Rev. 0 | Page 4 of 12

D

OUTx+

D

OUTx–

8085-003

ADN4665

V

C

V

V

D

INx

D

D

OUTx–

OUTx+

V

DIFF

t

PLHD

V

DIFF

t

TLH

V

OD

= D

OUTx+–DOUTx–

t

PHLD

t

THL

3

1.5V
0V

V

OH

0V (DIFFERENTIAL)

V

OL

80%

0V

20%

08085-004

Figure 4. Driver Propagation Delay and Transition Time Waveforms

CC

D

50Ω

50Ω

D

OUTx+

1.2V

OUTx–

SIGNAL

GENERATOR

S1

50Ω

C

V

CC

D

INx

EN

EN

L

C

L

NOTES

INCLUDES LOAD AND TEST JI G CAPACITANCE.

1.

L

2. S1 CONN E CTED TO V

3. S1 CONN E CTED TO GND FOR

FOR

t

AND

t

CC

PHZ

t

PLZ

AND

PZH

t

PZL

TEST.

TEST.

08085-005

Figure 5. Test Circuit for Driver Three-State Delay

1.5V

1.5V

50%

50%

3

0V

3V

0V

V

OH

1.2V

1.2V

V

OL

8085-006

OR D

OR D

D

D

OUTx+

OUTx–

OUTx+

OUTx–

EN WITH EN = GND

OR OPEN CIRCUIT

EN WITH EN = V

WITH D

WITH D

WITH D

WITH D

INx

INx

INx

INx

= V

= GND

= GND

= V

Figure 6. Driver Three-State Delay Waveforms

CC

t

PHZ

CC

CC

t

PLZ

t

PZH

t

PZL

Rev. 0 | Page 5 of 12

ADN4665

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VCC to GND −0.3 V to +4 V
Input Voltage (D
Enable Input Voltage (EN, EN) to GND
Output Voltage (D
Short-Circuit Duration (D

) to GND −0.3 V to VCC + 0.3 V

INx

OUTx+

−0.3 V to V

, D

) to GND −0.3 V to VCC + 0.3 V

OUTx−

, D

OUTx+

) to GND Continuous

OUTx−

+ 0.3 V

CC

Industrial Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance

TSSOP Package 150.4°C/W
SOIC Package 125°C/W

Reflow Soldering Peak Temperature (10 sec) 260°C max

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 12

ADN4665

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D
D
D

D
D

OUT1+
OUT1–

EN

OUT2–
OUT2+

D

GND

IN1

IN2

1
2
3

ADN4665

4

TOP VIEW

(Not to S cale)

5
6
7
8

16
15
14
13
12
11
10

9

Figure 7. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 D
2 D

3 D

4 EN

Driver Channel 1 Logic Input.

IN1

OUT1+

OUT1−

Channel 1 Noninverting Output Current Driver. When D
current flows into D

OUT1+

Channel 1 Inverting Output Current Driver. When D
flows out of D

OUT1−

.

Active High Enable and Power-Down Input (3 V TTL/CMOS). If EN

.

drivers when high and disables the drivers when low.

5 D

6 D

7 D

OUT2−

OUT2+

Driver Channel 2 Logic Input.

IN2

Channel 2 Inverting Output Current Driver. When D
flows out of D

OUT2−

.

Channel 2 Noninverting Output Current Driver. When D
current flows into D

OUT2+

.

8 GND Ground Reference Point for All Circuitry on the Part.
9 D
10 D

11 D

12

Driver Channel 3 Logic Input.

IN3

OUT3+

OUT3−

Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). If EN is held high, EN enables the

EN

Channel 3 Noninverting Output Current Driver. When D
current flows into D

OUT3+

.

Channel 3 Inverting Output Current Driver. When D
flows out of D

OUT3−

.

drivers when low or open circuit and disables the drivers and powers down the device when high.

13 D

14 D

15 D
16 VCC

OUT4−

OUT4+

Driver Channel 4 Logic Input.

IN4

Channel 4 Inverting Output Current Driver. When D
flows out of D

OUT4−

.

Channel 4 Noninverting Output Current Driver. When D
current flows into D

OUT4+

Power Supply Input. This part can be operated from 3.0 V to 3.6 V. The supply should be decoupled with a 10 μF

.

solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.

V

CC

D

IN4

D

OUT4+

D

OUT4–

EN
D

OUT3–

D

OUT3+

D

IN3

08085-007

is high, current flows out of D

IN1

is high, current flows into D

IN1

is held low or open circuit, EN enables the

is high, current flows into D

IN2

is high, current flows out of D

IN2

is high, current flows out of D

IN3

is high, current flows into D

IN3

is high, current flows into D

IN4

is high, current flows out of D

IN4

OUT1−

OUT2−

OUT3−

OUT4−

. When D

OUT1+

. When D

. When D

. When D

OUT2+

. When D

OUT3+

. When D

. When D

. When D

OUT4+

is low,

IN1

is low, current

IN1

is low, current

IN2

is low,

IN2

is low,

IN3

is low, current

IN3

is low, current

IN4

is low,

IN4

Rev. 0 | Page 7 of 12

ADN4665

TYPICAL PERFORMANCE CHARACTERISTICS

3.0

D

2.5

2.0

(V)

1.5

OUT

D

1.0

OUTx+

= +3.3V

V

CC

T

A

= 3.3V

= 25°C

2.0

= 3.0V TO 3.6V

V

1.8

1.6

1.4

(V)

OUT

D

1.2

1.0

CC

TA = 25°C

D

D

OUTx+

OUTx–

D
D
D
D
D
D

OUT
OUT
OUT
OUT
OUT
OUT

= +3.0V
= +3.3V
= +3.6V
= –3.0V
= –3.3V
= –3.6V

0.5

0

01234567

D

OUTx–

= –3.3V

RL (kΩ)

Figure 8. Single-Ended Driver Output Voltage vs. Load Resistance

0.8

0.6
010050 150 200 250 300 350 400

8085-008

RL (Ω)

8085-009

Figure 9. Driver Output vs. Load Resistance

Rev. 0 | Page 8 of 12

ADN4665

THEORY OF OPERATION

The ADN4665 is a quad line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be trans­mitted for considerable distances, over media such as a twisted pair
cable or PCB backplane, to an LVDS receiver such as the ADN4666,
where it develops a voltage across a termination resistor, R

. This

T

resistor is chosen to match the characteristic impedance of the
medium, typically around 100 . The differential voltage is
detected by the receiver and converted back into a single-ended
logic signal.

When D
pin (current source) through R

is high (Logic 1), current flows out of the D

INx

and back into the D

T

OUTx−

OUTx+

pin
(current sink). At the receiver, this current develops a positive
differential voltage across R
and results in a Logic 1 at the receiver output. When D
D

sinks current and D

OUTx+

ferential voltage across R

(with respect to the inverting input)

T

is low,

INx

sources current; a negative dif-

OUTx−

results in a Logic 0 at the receiver output.

T

The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.5 mA), developing between ±250 mV and ±450 mV
across a 100  termination resistor. The received voltage is centered
around the receiver offset of 1.25 V. Therefore, the noninverting
receiver input is typically 1.375 V (that is, 1.2 V + [350 mV/2]) and
the inverting receiver input is 1.025 V (that is, 1.2 V − [350 mV/2])
for Logic 1. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across R

is

T

twice the differential voltage.

Current-mode drivers offer considerable advantages over voltage­mode drivers such as RS-422 drivers. The operating current
remains fairly constant with increased switching frequency,
whereas the operating current of voltage-mode drivers increases
exponentially in most cases. This is caused by the overlap current as
internal gates switch between high and low, which causes currents
to flow from the device power supply to ground. A current-mode
device simply reverses a constant current between its two outputs,
with no significant overlap currents.

This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.

ENABLE INPUTS

The active high and active low enable inputs deactivate all the
current drivers when the drivers are in the disabled state. This
also powers down the device and reduces the current consumption
from typically 23 mA to typically 2.6 mA. A truth table for the
enable inputs is shown in Tab l e 5 .

Table 5. Enable Inputs Truth Table

Pin Logic Level

EN

EN

Low High X
Low Low Low I
Low Low High I
High Low Low I
High Low High I

1

X = don’t care.

D

D

INx

1

Inactive Inactive

D

OUTx+

I

SINK

I

SOURCE

I

SINK

I

SOURCE

OUTx−

SOURCE

SINK

SOURCE

SINK

APPLICATIONS INFORMATION

Figure 10 shows a typical application for point-to-point data
transmission using the ADN4665 as the driver.

GNDGND

RECEIVER

EN
EN

R

OUTy

EN
EN

D

INx

1/4 ADN4665

Figure 10. Typical Application Circuit

D

D

OUTx+

OUTx–

R

R

T

100Ω

R

INy+

INy–

08085-010

Rev. 0 | Page 9 of 12

ADN4665

OUTLINE DIMENSIONS

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

COMPLI ANT TO JE DE C S TANDARDS MS-012-AC

CONTROLLING DIM E NSIONS ARE IN MILLIM E TERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE I N DESI G N.

060606-A

Figure 11. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-16)

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

16

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

Figure 12. 16-Lead Thin Shrink Small Outline Package [TSSOP]

9

6.40

BSC

81

1.20
MAX

0.20

SEATING
PLANE

0.09

0.30

0.19

0.10

(RU-16)

Dimensions shown in millimeters

8°
0°

0.75

0.60

0.45

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADN4665ARZ
ADN4665ARZ-REEL7
ADN4665ARUZ
ADN4665ARUZ-REEL7

1

Z = RoHS Compliant Part.

1

1

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

Rev. 0 | Page 10 of 12

ADN4665

NOTES

Rev. 0 | Page 11 of 12

ADN4665

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08085-0-5/09(0)

Rev. 0 | Page 12 of 12