ANALOG DEVICES ADN4664 Service Manual
Dual, 3 V, CMOS, LVDS
V
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout
100 ps channel-to-channel skew (typical)
2.5 ns maximum propagation delay
3.3 V power supply
High impedance outputs on power-down
Low power design: typically 3 mW (quiescent)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential signal
levels
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) package
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
Differential Line Receiver
ADN4664
FUNCTIONAL BLOCK DIAGRAM
CC
ADN4664
R
IN1+
R
IN1–
R
IN2+
R
IN2–
GND
Figure 1.
R
R
OUT1
OUT2
07961-001
GENERAL DESCRIPTION
The ADN4664 is a dual, CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over
400 Mbps (200 MHz) and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended 3 V TTL/
CMOS logic level.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADN4664 and its companion driver, the ADN4663, offer a
new solution to high speed, point-to-point data transmission,
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADN4664
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 6
REVISION HISTORY
1/09—Revision 0: Initial Version
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Applications Information .......................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
ADN4664
SPECIFICATIONS
VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications T
Table 1.
1
Parameter
Symbol Min Typ
LVDS INPUT
High Threshold at R
Low Threshold at R
Input Current at R
INx+
INx+
INx+
3
, R
INx−
3
, R
V
INx−
, R
I
INx−
VTH +100 mV VCM = 1.2 V, 0.05 V, 2.95 V
−100 mV VCM = 1.2 V, 0.05 V, 2.95 V
TL
−10 ±1 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V
IN
−10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V
−20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V
OUTPUT
Output High Voltage VOH 2.7 3.1 V IOH = −0.4 mA, VID = +200 mV
2.7 3.1 V IOH = −0.4 mA, input terminated
2.7 3.1 V IOH = −0.4 mA, input shorted
Output Low Voltage VOL 0.3 0.5 V IOL = 2 mA, VID = −200 mV
Output Short-Circuit Current
4
I
−15 −47 −100 mA Enabled, V
OS
Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA
POWER SUPPLY
No Load Supply Current ICC 5.4 9 mA Inputs open
ESD PROTECTION
R
, R
INx+
All Pins Except R
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified.
2
All typicals are given for: VCC = 3.3 V, TA = 25°C.
3
VCC is always higher than R
specifications, the common voltage range is 0.1 V to 2.3 V.
4
Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed
maximum junction temperature specification.
Pins ±15 kV Human body model
INx−
, R
INx+
±4 kV Human body model
INx−
and R
INx+
voltage. R
INx−
INx−
and R
are allowed to have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac
INx+
MIN
to T
, unless otherwise noted.
MAX
2
Max Unit Conditions/Comments
OUT
= 0 V
Rev. 0 | Page 3 of 12
ADN4664
AC CHARACTERISTICS
VDD = 3.0 V to 3.6 V; C
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Parameter Symbol Min Typ2Max Unit Conditions/Comments
Differential Propagation Delay High to Low t
Differential Propagation Delay Low to High t
Differential Pulse Skew |t
Differential Channel-to-Channel Skew
(Same Device)
PHLD
5
Differential Part-to-Part Skew
Differential Part-to-Part Skew
4
− t
|
t
PLHD
6
t
7
t
Rise Time t
Fall Time t
Maximum Operating Frequency
1
CL includes probe and jig capacitance.
2
All typicals are given for VCC = 3.3 V, TA = 25°C.
3
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, t
4
t
is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
SKD1
5
Channel-to-channel skew, t
same chip with any event on the inputs.
6
t
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of
SKD3
each other within the operating temperature range.
7
t
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
SKD4
temperature and voltage ranges, and across process distribution. t
8
f
generator input conditions: f = 200 MHz, t
MAX
cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), load = 15 pF (stray plus probes).
SKD2
8
f
, is the defined as the difference between the propagation delay of one channel and the propagation delay of the other channel on the
= t
TLH
1.0 2.15 2.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
PHLD
1.0 2.03 2.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
PLHD
0 80 400 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
SKD1
t
0 100 500 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
SKD2
1.0 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
SKD3
1.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
SKD4
510 800 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
TLH
445 800 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
THL
200 250 MHz All channels switching
MAX
is defined as |maximum − minimum| differential propagation delay.
< 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty
THL
SKD4
and t
TLH
(0% to 100%) ≤ 3 ns for R
THL
INx+
, R
INx−
3
.
Rev. 0 | Page 4 of 12
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