Dual, 3 V, CMOS, LVDS
FEATURES
±15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
±355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
High Speed Differential Driver
ADN4663
FUNCTIONAL BLOCK DIAGRAM
V
CC
ADN4663
D
IN1
D
IN2
GND
Figure 1.
D
D
D
D
OUT1+
OUT1–
OUT2+
OUT2–
07927-001
GENERAL DESCRIPTION
The ADN4663 is a dual, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
±3.1 mA for driving a transmission medium such as a
twisted-pair cable. The transmitted signal develops a differential
voltage of typically ±355 mV across a termination resistor at the
receiving end, and this is converted back to a TTL/CMOS logic
level by a line receiver.
The ADN4663 and a companion receiver offer a new solution
to high speed point-to-point data transmission, and a low
power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADN4663
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 6
REVISION HISTORY
1/09—Revision 0: Initial Version
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Applications Information .......................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
ADN4663
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications T
Table 1.
Parameter
LVDS OUT PUTS (D
1, 2
OUTx+
Symbol Min Typ Max Unit Test Conditions
, D
)
OUTx−
Differential Output Voltage VOD 250 355 450 mV See Figure 2 and Figure 4
ΔV
Change in Magnitude of VOD for
1 35 |mV| See Figure 2 and Figure 4
OD
Complementary Output States
Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 and Figure 4
3 25 |mV| See Figure 2 and Figure 4
Change in Magnitude of VOS for
ΔV
OS
Complementary Output States
Output High Voltage VOH 1.4 1.6 V See Figure 2 and Figure 4
Output Low Voltage V
INPUTS (D
, D
)
IN1
IN2
0.90 1.1 V See Figure 2 and Figure 4
OL
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 ±2 +10 μA VIN = 3.3 V or 2.4 V
Input Low Current IIL −10 ±1 +10 μA VIN = GND or 0.5 V
Input Clamp Voltage VCL −1.5 −0.6 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current3 I
LVDS OUTPUT LEAKAGE (D
Power-Off Leakage I
OUTx+
, D
OUTx+
, D
)
OUTx−
−5.7 −8.0 mA D
OS
)
OUTx−
−10 ±1 +10 μA V
OFF
POWER SUPPLY
Supply Current, Unloaded ICC 8 14 mA No load, D
Supply Current, Loaded I
10 20 mA D
CCL
ESD PROTECTION
D
, D
OUTx+
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Pins ±15 kV Human body model
OUTx−
, D
OUTx+
±4 kV Human body model
OUTx−
MIN
to T
, unless otherwise noted.
MAX
= VCC, D
INx
= VCC or GND, VCC = 0 V
OUT
= VCC or GND
INx
= 0 V or D
OUTx+
= VCC or GND
INx
= GND, D
INx
OUTx−
= 0 V
Rev. 0 | Page 3 of 12
ADN4663
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; C
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Parameter2 Symbol Min Typ Max Unit Conditions/Comments
Differential Propagation Delay High to Low t
Differential Propagation Delay Low to High t
Differential Pulse Skew |t
PHLD
− t
|5 t
PLHD
Channel-to-Channel Skew6 t
Differential Part-to-Part Skew7 t
Differential Part-to-Part Skew8 t
Rise Time t
Fall Time t
Maximum Operating Frequency9 f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, t
4
All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
is the differential channel-to-channel skew of any event on the same device.
SKD2
7
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8
t
, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
SKD4
operating temperatures and voltage ranges, and across process distribution. t
9
f
generator input conditions: t
MAX
switching.
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
PLHD
= t
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
TLH
THL
0.3 0.8 1.5 ns See Figure 3 and Figure 4
PHLD
0.3 1.1 1.5 ns See Figure 3 and Figure 4
PLHD
0 0.3 0.7 ns See Figure 3 and Figure 4
SKD1
0 0.4 0.8 ns See Figure 3 and Figure 4
SKD2
0 1.0 ns See Figure 3 and Figure 4
SKD3
0 1.2 ns See Figure 3 and Figure 4
SKD4
0.2 0.5 1.0 ns See Figure 3 and Figure 4
TLH
0.2 0.5 1.0 ns See Figure 3 and Figure 4
THL
350 MHz See Figure 3
MAX
≤ 1 ns, and t
TLH
is defined as |maximum − minimum| differential propagation delay.
SKD4
≤ 1 ns.
THL
3, 4
Rev. 0 | Page 4 of 12
ADN4663
V
V
Test Circuits and Timing Diagrams
D
V
V
CC
CC
D
INx
Figure 2. Test Circuit for Driver V
D
SIGNAL
GENERATOR
C
INCLUDES LO AD AND TEST JIG CAPACITANCE.
L
INx
50Ω
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
D
D
D
OUTx–
OUTx+
1.5V
INx
t
PLHD
0V (DIFFERENTIAL)
OUTx+
RL/2
VOSV
OD
OD
C
L
C
L
VV
and VOS
R
L
1.5V
t
PHLD
0V
D
D
07927-002
OUTx+
OUTx–
07927-003
3
0V
V
OH
V
OL
/2
R
L
D
OUTx–
CC
V
OD
80%
V
DIFF
20%
0V
t
THL
V
= D
DIFF
OUT+
– D
OUT–
80%
0V
20%
t
THL
07927-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 5 of 12
ADN4663
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 3.
Parameter Rating
VCC to GND −0.3 V to +4 V
Input Voltage (D
Output Voltage (D
Short-Circuit Duration (D
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θJA
SOIC Package
θJA Thermal Impedance 149.5°C/W
Reflow Soldering Peak Temperature
Pb-Free 260°C ± 5°C
) to GND −0.3 V to VCC + 0.3 V
INx
, D
OUTx+
) to GND −0.3 V to VCC + 0.3 V
OUTx−
, D
OUTx+
) to GND Continuous
OUTx−
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 12
ADN4663
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
V
1
CC
IN1
IN2
ADN4663
2
TOP VIEW
3
(Not to Scale)
4
D
D
GND
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC
Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a
10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
2 D
3 D
Driver Channel 1 Logic Input.
IN1
Driver Channel 2 Logic Input.
IN2
4 GND Ground reference point for all circuitry on the part.
5 D
6 D
7 D
8 D
OUT2−
OUT2+
OUT1+
OUT1−
Channel 2 Inverting Output Current Driver. When D
flows out of D
OUT2−
.
Channel 2 Noninverting Output Current Driver. When D
current flows into D
OUT2+
.
Channel 1 Noninverting Output Current Driver. When D
current flows into D
OUT1+
.
Channel 1 Inverting Output Current Driver. When D
flows out of D
OUT1−
.
D
OUT1–
D
7
OUT1+
D
6
OUT2+
5
D
OUT2–
7927-005
is high, current flows into D
IN2
is high, current flows out of D
IN2
is high, current flows out of D
IN1
is high, current flows into D
IN1
OUT2−
OUT1−
. When D
. When D
OUT2+
. When D
OUT1+
. When D
is low, current
IN2
is low,
IN2
is low,
IN1
is low, current
IN1
Rev. 0 | Page 7 of 12
ADN4663
(
(
–
TYPICAL PERFORMANCE CHARACTERISTICS
1.415
TA = 25°C
R
= 100Ω
L
V)
OH
1.414
1.413
OUTPUT HIGH VOLTAGE, V
1.412
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 6. Output High Voltage vs. Power Supply Voltage
1.090
TA = 25°C
R
= 100Ω
L
V)
OL
1.089
1.088
325.0
TA = 25°C
= 100Ω
R
(mV)
OD
DIFFERENTIAL OUTP UT VOLTAGE, V
07927-006
L
324.8
324.6
324.4
324.2
324.0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
07927-009
Figure 9. Differential Output Voltage vs. Power Supply Voltage
500
TA = 25°C
V
= 3.3V
(mV)
OD
CC
450
400
350
OUTPUT LOW VOLTAGE, V
1.087
3.03.13.23.33.43.53.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 7. Output Low Voltage vs. Power Supply Voltage
3.9
(mA)
OS
–4.0
–4.1
SHORT-CIRCUIT CURRENT, I
–4.2
3.0 3.1 3.2 3.3 3.4 3.5 3. 6
POWER SUPPLY VOLTAGE, VCC (V)
= GND OR V
V
IN
TA = 25°C
V
= 0V
OUT
Figure 8. Output Short-Circuit Current vs. Power Supply Voltage
300
DIFFERENTIAL OUTPUT VOLTAGE, V
250
90 100 110 120 130 140 150
07927-007
LOAD RESIST OR, RL (Ω)
07927-010
Figure 10. Differential Output Voltage vs. Load Resistor
1.252
TA = 25°C
R
= 100Ω
CC
(mV)
OS
OFFSET VOLTAGE, V
07927-008
L
1.251
1.250
1.249
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
07927-011
Figure 11. Offset Voltage vs. Power Supply Voltage
Rev. 0 | Page 8 of 12
ADN4663
TA = 25°C
19
C
= 15pF
L
V
= 3.3V
CC
V
= 0V TO 3. 3V
IN
17
(mA)
R
= 100Ω PER DRIVER
L
CC
15
BOTH CHANNELS SW ITCHING
13
11
ONE CHANNEL SWITCHING
9
POWER SUPPL Y CURRENT, I
7
5
0.01 0.1 1 10 100 1k
SWITCHING FREQUENCY (MHz)
Figure 12. Power Supply Current vs. Switching Frequency
12.5
TA = 25°C
f = 1MHz
C
= 15pF
L
V
= 0V TO 3. 3V
IN
12.0
(mA)
R
= 100Ω PER DRIVER
CC
L
11.5
11.0
1200
1100
t
PLHD
t
PHLD
R
= 100Ω PER DRIVER
L
TA = 25°C
f = 1MHz
C
= 15pF
L
1000
DIFFERENT IAL PROPAGATION DELAY (ns)
900
3.0 3.1 3.2 3. 3 3.4 3.5 3. 6
07927-012
POWER SUPPLY VOLTAGE, VCC (V)
07927-015
Figure 15. Differential Propagation Delay vs. Power Supply Voltage
1200
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω PER DRIVER
L
1100
1000
t
PHLD
t
PLHD
10.5
POWER SUPPL Y CURRENT, I
10.0
3.0 3.1 3.2 3.3 3.4 3. 5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 13. Power Supply Current vs. Power Supply Voltage
15
VCC = 3.3V
f = 1MHz
= 15pF
C
L
= 0V TO 3V
V
14
(mA)
CC
IN
= 100Ω PER DRIVER
R
L
13
12
11
POWER SUPPL Y CURRENT, I
10
–40 –15 10 35 60 85
TEMPERATURE (°C)
Figure 14. Power Supply Current vs. Ambient Temperature
DIFFERENT IAL PROPAGATION DELAY (ns)
900
–40–200 20406080100
07927-013
AMBIENT TEMPERATURE, TA (°C)
07927-016
Figure 16. Differential Propagation Delay vs. Ambient Temperature
100
TA = 25°C
f = 1MHz
C
= 15pF
L
R
= 100Ω PER DRIVER
80
(ps)
L
SKD1
60
40
20
DIFFERENTIAL SKEW , t
0
3.03.13.23.33.43.53.6
07927-014
POWER SUPPLY VOLTAGE, VCC (V)
07927-017
Figure 17. Differential Skew vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
ADN4663
50
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω PER DRIVER
L
40
(ps)
SKD1
30
20
10
DIFFERENTIAL SKEW, t
0
–40 –20 0 20 40 60 80 100
AMBIENT TEMPERATURE, TA (°C)
Figure 18. Differential Skew vs. Ambient Temperature
400
R
= 100Ω PER DRIVER
380
360
t
TLH
t
THL
L
TA = 25°C
f = 1MHz
C
= 15pF
L
400
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω PER DRIVER
L
380
t
TLH
360
TRANSITION TIME (ps)
340
320
–40 –20 0 20 40 60 80 100
07927-018
AMBIENT TEMPERATURE, TA (°C)
t
THL
07927-020
Figure 20. Transition Time vs. Ambient Temperature
TRANSITION TIME (ps)
340
320
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
07927-019
Figure 19. Transition Time vs. Power Supply Voltage
Rev. 0 | Page 10 of 12
ADN4663
V
V
THEORY OF OPERATION
The ADN4663 is a dual line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted
for considerable distances, over media such as a twisted-pair cable
or PCB backplane, to an LVDS receiver, where it develops a voltage
across a terminating resistor, R
. This resistor is chosen to match
T
the characteristic impedance of the medium, typically around
100 . The differential voltage is detected by the receiver and
converted back into a single-ended logic signal.
When D
(current source) through R
is high (Logic 1), current flows out of the D
INx
and back into the D
T
OUTx−
pin
OUTx+
pin (current
sink). At the receiver, this current develops a positive differential
voltage across R
in a Logic 1 at the receiver output. When D
sinks current and D
voltage across R
(with respect to the inverting input) and results
T
is low, D
INx
sources current; a negative differential
OUTx−
results in a Logic 0 at the receiver output.
T
OUTx+
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.55 mA), developing between ±250 mV and ±450 mV
across a 100 termination resistor. The received voltage is centered
around the receiver offset of 1.2 V. Therefore, the noninverting
receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and
the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V
for Logic 1. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across R
is
T
twice the differential voltage.
Current mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas that of voltage mode drivers increase
exponentially in most cases. This is caused by the overlap
as internal gates switch between high and low, which causes
currents to flow from the device power supply to ground.
A current mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 21 shows a typical application for point-to-point data
transmission using the ADN4663 as the driver and a LVDS
receiver.
+3.3
+
GND
10µF
TANTALUM
D
OUTx+
R
T
100Ω
D
OUTx–
LVDS RECEIVER
D
IN+
D
IN–
V
CC
0.1µF
V
CC
ADN4663
D
INx
Figure 21. Typical Application Circuit
GND
+3.3
+
D
OUT
07927-021
Rev. 0 | Page 11 of 12
ADN4663
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIG N.
85
1
1.27 (0.0500)
BSC
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)]
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN4663BRZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8
ADN4663BRZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8
1
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07927-0-1/09(0)
Rev. 0 | Page 12 of 12
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