Datasheet ADN4662 Datasheet (ANALOG DEVICES)

Single, 3 V, CMOS, LVDS

V

FEATURES

±15 kV ESD protection on input pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout

2.5 ns maximum propagation delay

3.3 V power supply
High impedance outputs on power-down
Low power design: typically 3 mW (quiescent)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential signal

levels
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) package

APPLICATIONS

Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers

Differential Line Receiver

ADN4662

FUNCTIONAL BLOCK DIAGRAM

CC

R

IN+

R

IN–

ADN4662

GNDNCNC

Figure 1.

NC

R

OUT

07960-001

GENERAL DESCRIPTION

The ADN4662 is a single, CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over
400 Mbps (200 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.

The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended 3 V TTL/
CMOS logic level.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADN4662 and its companion driver, the ADN4661, offer a
new solution to high speed, point-to-point data transmission,
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADN4662

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

1/09—Revision 0: Initial Version

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 11

Applications Information .......................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. 0 | Page 2 of 12

ADN4662

SPECIFICATIONS

VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications T

Table 1.

1

Parameter

Symbol Min Typ

LVDS INPUT

High Threshold at R

Low Threshold at R

Input Current at R

IN+

3

V

IN+, RIN−

3

, R

V

IN+

IN−

, R

I

IN−

+100 mV VCM = 1.2 V, 0.05 V, 2.95 V

TH

−100 mV VCM = 1.2 V, 0.05 V, 2.95 V

TL

−10 ±1 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V

IN

−10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V

−20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V
OUTPUT

Output High Voltage VOH 2.7 3.1 V IOH = −0.4 mA, VID = +200 mV

2.7 3.1 V IOH = −0.4 mA, input terminated

2.7 3.1 V IOH = −0.4 mA, input shorted

Output Low Voltage VOL 0.3 0.5 V IOL = 2 mA, VID = −200 mV

Output Short-Circuit Current

4

I

−15 −47 −100 mA Enabled, V

OS

Input Clamp Voltage VCL −1.5 −0.8 V ICL = −18 mA

POWER SUPPLY

No Load Supply Current ICC 5.4 9 mA Inputs open

ESD PROTECTION

R

, R

Pins ±15 kV Human body model

IN+

IN−

All Pins Except R

1

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.

2

All typicals are given for: VCC = +3.3 V, TA = 25°C.

3

VCC is always higher than R

the common voltage range is 0.1 V to 2.3 V.

4

Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed

maximum junction temperature specification.

, R

±4 kV Human body model

IN+

IN−

and R

IN+

voltage. R

IN−

IN−

and R

are allowed to have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications,

IN+

MIN

to T

, unless otherwise noted.

MAX

2

Max Unit Conditions/Comments

OUT

= 0 V

Rev. 0 | Page 3 of 12

ADN4662

AC CHARACTERISTICS

VDD = 3.0 V to 3.6 V; C

1

= 15 pF to GND; all specifications T

L

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter Symbol Min Typ2Max Unit Conditions/Comments

Differential Propagation Delay High to Low t
Differential Propagation Delay Low to High t
Differential Pulse Skew |t

PHLD

Differential Part-to-Part Skew
Differential Part-to-Part Skew

4

− t

|

t

PLHD

5

t

6

t

Rise Time t
Fall Time t
Maximum Operating Frequency

1

CL includes probe and jig capacitance.

2

All typicals are given for VCC = 3.3 V, TA = 25°C.

3

Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, t

4

t

is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.

SKD1

5

t

, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C

SKD3

of each other within the operating temperature range.

6

t

, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating

SKD4

temperature and voltage ranges, and across process distribution. t

7

f

generator input conditions: f = 200 MHz, t

MAX

cycle, V

(maximum 0.4 V), VOH (minimum 2.7 V), load = 15 pF (stray plus probes).

OL

7

f

= t

TLH

1.0 2.15 2.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

PHLD

1.0 2.03 2.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

PLHD

0 80 400 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

SKD1

1.0 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

SKD3

1.5 ns CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

SKD4

510 800 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

TLH

445 800 ps CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)

THL

200 250 MHz All channels switching

MAX

is defined as |maximum − minimum| differential propagation delay.

< 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty

THL

SKD4

and t

TLH

(0% to 100%) ≤ 3 ns for R

THL

IN+/RIN−

3

.

Rev. 0 | Page 4 of 12

ADN4662

V

Test Circuits and Timing Diagrams

SIGNAL

GENERATOR

R

R

50Ω 50Ω

IN+

CC

R

IN–

OUT

C

L

CL = LOAD AND TEST JIG CAPACIT ANCE

07960-002

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

R

IN–

0V (DIFFERENT IAL)

R

IN+

t

PLHD

80%

R

OUT

20%

1.5V

t

TLH

VID= 200mV

80%

t

PHLD

1.2V

1.5V

t

THL

20%

1.3V

1.1V

V

V

OH

OL

07960-003

Figure 3. Receiver Propagation Delay and Transition Time Waveforms

Rev. 0 | Page 5 of 12

ADN4662

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VCC to GND −0.3 V to +4 V
Input Voltage (R
Output Voltage (R
Operating Temperature Range

Industrial Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA

SOIC Package

θJA Thermal Impedance 149.5°C/W

Reflow Soldering Peak Temperature

Pb-Free 260°C ± 5°C

, R

) to GND −0.3 V to V

IN+

IN−

) to GND −0.3 V to VCC + 0.3 V

OUT

+ 3.9 V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 12

ADN4662

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

R

1

IN–

ADN4662

2

R

IN+

3

NC

(Not to Scale)

NC

4

NC = NO CONNECT

TOP VIEW

V

8

CC

7

R

OUT

6

NC

GND

5

07960-004

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

2 R

IN−

IN+

Receiver Channel 1 Inverting Input. When this input is more negative than R
more positive than R

IN+

, R

OUT

is low.

Receiver Channel 1 Noninverting Input. When this input is more positive than R

, R

more negative than R

IN−

OUT

is low.
3 NC No Connect.
4 NC No Connect.
5 GND Ground reference point for all circuitry on the part.
6 NC No Connect.
7 R

OUT

Receiver Output (3 V TTL/CMOS). If the differential input voltage between R
high. If the differential input voltage is negative, this output is low.

8 VCC Power Supply Input. This part can be operated from 3.0 V to 3.6 V.

, R

is high. When this input is

IN+

OUT

, R

is high. When this input is

IN−

OUT

IN+

and R

is positive, this output is

IN−

Rev. 0 | Page 7 of 12

ADN4662

–

V

TYPICAL PERFORMANCE CHARACTERISTICS

3.6

I

= –400µA

3.5

(V)

OH

3.4

3.3

3.2

3.1

OUTPUT HIGH VOLTAGE, V

3.0

2.9

LOAD

T

= 25°C

A

V

= 200mV

ID

3.0 3. 1 3.2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

Figure 5. Output High Voltage vs. Power Supply Voltage

07960-007

0

V

= 0V

OUT

–5

T

= 25°C

= 25°C

A

–10

(mV)

–15

TH

–20

–25

–30

–35

–40

THRESHOLD VO LTAGE,

–45

–50

A

3.0 3. 1 3.2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

Figure 8. Threshold Voltage vs. Power Supply Voltage

07237-011

33.60

I

= 2mA

LOAD

T

33.55

(mV)

33.50

OL

33.45

33.40

33.35

OUTPUT LOW VOLTAGE, V

33.30

33.25

3.0 3. 1 3.2 3.3 3.4 3.5 3.6

= 25°C

A

V

= –200mV

ID

POWER SUPPLY VOLTAGE, VCC (V)

07960-008

Figure 6. Output Low Voltage vs. Power Supply Voltage

35

V

= 0V

–37

(mA)

OS

–39

–41

–43

–45

–47

–49

–51

–53

OUTPUT SHO RT-CIRCUIT CURRENT, I

–55

3.0 3. 1 3.2 3.3 3.4 3.5 3.6

Figure 7. Output Short-Circuit Current vs. Power Supply Voltage

OUT

T

= 25°C

A

POWER SUPPLY VOLTAGE, VCC (V)

07960-009

50

TA = 25°C

45

40

(mA)

CC

35

30

25

20

15

10

POWER SUPPL Y CURRENT, I

= 3.3V

V

CC

= 200mV

V

ID

CL = 15pF

5

0

0.01 0.1 1 10 100 1000
FREQUENCY (MHz )

Figure 9. Power Supply Current vs. Frequency

10

9

VCC = 3.3V
V

= 200mV

ID

C

= 15pF

8

(mA)

POWER SUPPL Y CURRENT, I

L

FREQUENCY = 1MHz

CC

7

6

5

4

3

2

1

0

–40 –15 10 35 60 85

AMBIENT TEMPERATURE (°C)

Figure 10. Power Supply Current vs. Ambient Temperature

07960-023

07960-024

Rev. 0 | Page 8 of 12

ADN4662

2.5

VCC= 3.3V

= 200mV

V

ID

2.4
FREQUENCY = 200MHz

= 15pF

C

L

2.3

(ns)

2.2

PHLD

t

,

2.1

PLHD

t

2.0

1.9

DIFFERENTIAL PROPAGATION DELAY,

1.8

–40 –15 10 35 8560

AMBIENT TEM PERATURE, TA (°C)

t

t

PHLD

PLHD

Figure 11. Differential Propagation Delay vs. Ambient Temperature

4.0

TA= 25°C

FREQUENCY = 200MHz
V

= 200mV

ID

3.5
C

= 15pF

L

3.0

(ns)

PHLD

t

,

2.5

PLHD

t

2.0

DIFFERENTIAL PROPAGATION DELAY,

1.5

00.51.01.5 32.0 .0

COMMON-MODE VOLTAGE, VCM (V)

t

PLHD

t

PHLD

2.5

Figure 12. Differential Propagation Delay vs. Common-Mode Voltage

6.0

VCC = 3.3V

5.5
C

= 15pF

L

FREQUENCY = 200M Hz

5.0
V

= 1.2V

CM

4.5

(ps)

4.0

3.5

PHLD

, t

3.0

PLHD

t

2.5

2.0

DIFFERENT IAL PROPAG ATION DEL AY,

1.5

07960-014

1.0

0 0.5 1.0 1.5 2.0 2.5 3.0

DIFFERENTIAL INPUT VOLTAGE, V

t

PLHD

t

PHLD

(V)

ID

7960-025

Figure 14. Differential Propagation Delay vs. Differential Input Voltage

250

TA= 25°C
V

= 200mV

ID

200

FREQUENCY = 200MHz
C

= 15pF

(ps)

t

DIFFERENTIAL SKEW,

07960-015

L

150

SKEW

100

50

0

–50

–100

3.0 3.1 3. 2 3.3 3.4 3.5 3.6

POWER SUPPLY VOLTAGE, VCC (V)

07960-018

Figure 15. Differential Skew vs. Power Supply Voltage

2.30

2.25

2.20

2.15

(ns)

2.10

PHLD

t

,

2.05

PLHD

t

2.00

1.95

DIFFERENTIAL PROPAG ATION DEL AY,

1.90

1.85

3.0 3.1 3.2 3. 3 3.63.4

POWER SUPPLY VOLTAGE, VCC (V)

TA= 25°C
V

= 200mV

ID

FREQUENCY = 200MHz
C

= 15pF

L

t

PHLD

t

PLHD

3.5

Figure 13. Differential Propagation Delay vs. Power Supply Voltage

07960-016

Rev. 0 | Page 9 of 12

160

V

= 3.3V

CC

VID= 200mV

140

FREQUENCY = 200MHz
C

= 15pF

(ps)

SKEW

t

DIFFERENTIAL SKEW,

L

120

100

80

60

40

20

0

–40 –15 10 35 60 85

AMBIENT TEMPERATURE, TA (°C)

Figure 16. Differential Skew vs. Ambient Temperature

07960-019

ADN4662

600

580

560

(ps)

540

THL

t

,

520

TLH

t

500

480

460

440

TRANSITION TIME,

420

400

3.0 3. 1 3.2 3.3 3.63.4

t

TLH

t

THL

POWER SUPPLY VOLTAGE, VCC (V)

VCC= 3.3V

= 200mV

V

ID

FREQUENCY = 25MHz

= 15pF

C

L

Figure 17. Transition Time vs. Power Supply Voltage

600

VCC= 3.3V

= 200mV

V

ID

FREQUENCY = 200MHz

550

(ps)

t

,

t

TRANSITIO N TIME,

THL

TLH

500

450

400

350

= 15pF

C

L

t

TLH

t

THL

–40 –15 10 35 60 85

AMBIENT TEMPERATURE, TA (°C)

Figure 18. Transition Time vs. Ambient Temperature

3.5

07960-020

07960-021

1800

TA = 25°C

1600

V

= 3.3V

CC

V

= 200mV

(ps)

1400

THL

t

,

1200

TLH

t

1000

TRANSITION TIME,

ID

FREQUENCY = 1MHz

t

800

600

400

200

10 15 20 25 30 35 40 45

TLH

t

THL

LOAD (pF)

Figure 20. Transition Time vs. Load

2.9

2.7

2.5

(ns)

2.3

PHLD

t

,

2.1

PLHD

t

1.9
TA = 25°C

V

CC

V

ID

1.7

DIFFERENT IALPROPAG ATIONDEL AY,

FREQUENCY = 200MHz

1.5

10 15 20 25 30 35 40 45

= 3.3V
= 200mV

t

PHLD

t

PLHD

LOAD (pF)

Figure 21. Differential Propagation Delay vs. Load at 200 MHz

07960-027

07960-028

3.1

2.9

2.7

2.5

(ns)

2.3

PHLD

t

,

2.1

PLHD

t

TA = 25°C

1.9
V

= 3.3V

CC

V

= 200mV

DIFFERENT IALPROPAG ATIONDEL AY,

ID

1.7
FREQUENCY = 1MHz

1.5

10 15 20 25 30 35 40 45

t

PHLD

t

PLHD

LOAD (pF)

Figure 19. Differential Propagation Delay vs. Load at 1 MHz

07960-026

Rev. 0 | Page 10 of 12

1800

TA = 25°C

1600

V

= 3.3V

CC

V

= 200mV

ID

FREQUENCY = 200MHz

1400

(ps)

THL

t

1200

,

TLH

t

1000

800

600

400

TRANSITION TIME,

200

0

10 15 20 25 30 35 40 45

t

TLH

t

THL

LOAD (pF)

Figure 22. Transition Time vs. Load at 200 MHz

07960-029

ADN4662

V

V

THEORY OF OPERATION

The ADN4662 is a single line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typically and converts it into a single-ended 3 V
TTL/CMOS logic signal.

A differential current input signal, received via a transmission
medium, such as a twisted pair cable, develops a voltage across
a terminating resistor, R

. This resistor is chosen to match the

T

characteristic impedance of the medium, typically around
100

Ω. The differential voltage is detected by the receiver and

converted back into a single-ended logic signal.

When the noninverting receiver input, R
respect to the inverting input R
from R
receiver input R
input R
R

OUT

to R

IN+

IN−

), then R

IN−

IN+

OUT

is negative with respect to the inverting

(current flows through RT from R

is low.

(current flows through RT

IN−

is high. When the noninverting

, is positive with

IN+

to R

IN−

IN+

), then

The ADN4662 differential line receiver is capable of receiving
signals of 100 mV over a ±1 V common-mode range centered
around 1.2 V. This relates to the typical driver offset voltage
value of 1.2 V. The signal originating from the driver is centered
around 1.2 V and may shift ±1 V around this center point. This
±1 V shifting may be caused by a difference in the ground
potential of the driver and receiver, the common-mode effect of
coupled noise, or both.

Using the ADN4663 as a driver, the received differential current
is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing
between 250 mV and 450 mV across a 100

Ω termination resis-

tor. The received voltage is centered around the receiver offset of

1.2 V. In other words, the noninverting receiver input is typically

(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
(1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note that
because the differential voltage reverses polarity, the peak-to-peak
voltage swing across R

is twice the differential voltage.

T

Current mode signalling offers considerable advantages over
voltage mode signalling, such as RS-422. The operating current
remains fairly constant with increased switching frequency,
whereas with voltage mode drivers the current increases
exponentially in most cases. This is caused by the overlap as
internal gates switch between high and low, which causes currents
to flow from V

to ground. A current mode device simply reverses

CC

a constant current between its two outputs, with no significant
overlap currents.

This is similar to emitter-coupled logic (ECL) and positive emitter­coupled logic (PECL), but without the high quiescent current of
ECL and PECL.

APPLICATIONS INFORMATION

Figure 23 shows a typical application for point-to-point data

transmission using the ADN4663 as the driver.

3.3

+

GND

10µF
TANTALUM

D

OUT+

R

D

OUT–

0.1µF

V

CC

IN+

IN–

ADN4662

R

100Ω

T

R

0.1µF

V

CC

ADN4661

D

IN

Figure 23. Typical Application Circuit

GND

3.3

+

10µF
TANTALUM

R

OUT

07960-119

Rev. 0 | Page 11 of 12

ADN4662

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10
SEATING

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIG N.

85

1

1.27 (0.0500)
BSC

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADN4662BRZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADN4662BRZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

Z = RoHS Compliant Part.

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07960-0-1/09(0)

Rev. 0 | Page 12 of 12