Single, 3 V, CMOS, LVDS,
V
FEATURES
±15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
±355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
High Speed Differential Driver
ADN4661
FUNCTIONAL BLOCK DIAGRAM
CC
ADN4661
D
D
IN
NC = NO CONNECT
GNDNC NC NC
Figure 1.
D
OUT+
OUT–
07876-001
GENERAL DESCRIPTION
The ADN4661 is a single, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz) and ultra-low power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
±3.1 mA for driving a transmission medium such as a twistedpair cable. The transmitted signal develops a differential voltage
of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level
by a line receiver.
The ADN4661 and a companion LVDS receiver offer a new
solution to high speed point-to-point data transmission, and a
low power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADN4661
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
REVISION HISTORY
12/08—Revision 0: Initial Version
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 10
Applications Information .......................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Rev. 0 | Page 2 of 12
ADN4661
SPECIFICATIONS
VCC = 3 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications T
Table 1.
Parameter
LVDS OUT PUTS (D
1, 2
OUT+
Symbol Min Typ Max Unit Test Conditions
, D
)
OUT−
Differential Output Voltage VOD 250 355 450 mV See Figure 2 and Figure 4
ΔV
Change in Magnitude of VOD for Complementary
1 35 |mV| See Figure 2 and Figure 4
OD
Output States
Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 and Figure 4
3 25 |mV| See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary
ΔV
OS
Output States
Output High Voltage VOH 1.4 1.6 V See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.1 V See Figure 2 and Figure 4
INPUTS (DIN, VCC)
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 ±2 +10 μA VIN = 3.3 V or 2.4 V
Input Low Current IIL −10 ±1 +10 μA VIN = GND or 0.5 V
Input Clamp Voltage VCL −1.5 −0.6 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current3 I
LVDS OUTPUT LEAKAGE (D
Power-Off Leakage I
OUT+
, D
OUT+
, D
)
OUT−
−5.7 −8.0 mA DIN = VCC, D
OS
)
OUT−
−10 ±1 +10 μA V
OFF
POWER SUPPLY
Supply Current, Unloaded ICC 4.0 8.0 mA No load, DIN = VCC or GND
Supply Current, Loaded I
7 10 mA DIN = VCC or GND
CCL
ESD PROTECTION
D
, D
OUT+
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4661 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Pins ±15 kV Human body model
OUT−
, D
OUT+
±4 kV Human body model
OUT−
MIN
to T
, unless otherwise noted.
MAX
= 0 V or DIN = GND, D
OUT+
= VCC or GND, VCC = 0 V
OUT
OUT−
= 0 V
Rev. 0 | Page 3 of 12
ADN4661
V
V
V
AC CHARACTERISTICS
VCC = 3 V to 3.6 V; RL = 100 Ω; C
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Parameter2 Symbol Min Typ Max Unit Conditions/Comments
Differential Propagation Delay High to Low t
Differential Propagation Delay Low to High t
Differential Pulse Skew |t
PHLD
− t
|5 t
PLHD
Differential Part-to-Part Skew6 t
Differential Part-to-Part Skew7 t
Rise Time t
Fall Time t
Maximum Operating Frequency8 f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, t
4
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
7
t
, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
SKD4
operating temperatures and voltage ranges, and across process distribution. t
8
f
generator input conditions: t
MAX
switching.
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
PLHD
= t
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
TLH
THL
0.3 0.8 1.5 ns See Figure 3 and Figure 4
PHLD
0.3 1.1 1.5 ns See Figure 3 and Figure 4
PLHD
0 0.3 0.7 ns See Figure 3 and Figure 4
SKD1
0 1.0 ns See Figure 3 and Figure 4
SKD3
0 1.2 Ns See Figure 3 and Figure 4
SKD4
0.2 0.5 1.0 ns See Figure 3 and Figure 4
TLH
0.2 0.5 1.0 ns See Figure 3 and Figure 4
THL
350 MHz See Figure 3
MAX
≤ 1 ns, and t
TLH
is defined as |maximum − minimum| differential propagation delay.
SKD4
≤ 1 ns.
THL
Test Circuits and Timing Diagrams
D
RL/2
R
L
/2
OUT+
V
VV
OSVOD
V
CC
CC
D
IN
3, 4
D
OUT–
Figure 2. Test Circuit for Driver V
CC
D
SIGNAL
GENERATOR
NOTES
INCLUDES PROBE AND JIG CAPACIT ANCE.
1. C
L
IN
50Ω
OD
C
L
C
L
and VOS
D
D
OUT+
OUT–
07876-002
07876-003
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
3
D
D
OUT–
OUT+
V
D
DIFF
IN
t
PLHD
V
OD
V
= D
DIFF
OUT+–DOUT–
t
TLH
t
PHLD
t
THL
1.5V
0V
V
OH
0V (DIFFERENTIAL)
V
OL
80%
0V
20%
07876-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 4 of 12
ADN4661
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 3.
Parameter Rating
VCC to GND −0.3 V to +4 V
Input Voltage (DIN) to GND −0.3 V to VCC + 0.3 V
Output Voltage (D
Short-Circuit Duration (D
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θJA
SOIC Package
θJA Thermal Impedance 149.5°C/W
Reflow Soldering Peak Temperature
Pb-Free 260°C ± 5°C
OUT+
, D
) to GND −0.3 V to VCC + 0.3 V
OUT−
, D
OUT+
) to GND Continuous
OUT−
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 12
ADN4661
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
CC
D
2
IN
NC
3
(Not to Scale)
4
GND
NC = NO CONNECT
ADN4661
TOP VIEW
8
7
6
5
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC
Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a
10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
2 DIN Driver Logic Input.
3 NC No Connect. This pin should be left unconnected.
4 GND Ground. Reference point for all circuitry on the part.
5 NC No Connect. This pin should be left unconnected.
6 NC No Connect. This pin should be left unconnected.
7 D
8 D
Noninverting Output Current Driver. When DIN is high, current flows out of D
OUT+
Inverting Output Current Driver. When DIN is high, current flows into D
OUT−
D
D
NC
NC
OUT–
OUT+
07876-005
. When DIN is low, current flows into D
OUT+
. When DIN is low, current flows out of D
OUT−
OUT−
.
OUT+
.
Rev. 0 | Page 6 of 12
ADN4661
(
(
–
m
TYPICAL PERFORMANCE CHARACTERISTICS
1.415
TA = 25°C
R
= 100Ω
L
V)
OH
1.414
1.413
OUTPUT HIGH VOLTAGE, V
1.412
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 6. Output High Voltage vs. Power Supply Voltage
1.090
TA = 25°C
R
= 100Ω
L
V)
OL
1.089
325.0
TA = 25°C
R
= 100Ω
(mV)
OD
DIFFERENTIAL OUTPUT VOLTAGE, V
07876-006
L
324.8
324.6
324.4
324.2
324.0
3.03.13.23.33.43.53.6
POWER SUPPLY VOLTAGE, VCC (V)
07876-009
Figure 9. Differential Output Voltage vs. Power Supply Voltage
500
TA = 25°C
V
= 3.3V
(mV)
OD
CC
450
400
1.088
OUTPUT LOW VOLTAGE, V
1.087
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 7. Output Low Voltage vs. Power Supply Voltage
3.9
A)
(
OS
–4.0
–4.1
SHORT-CIRCUIT CURRENT, I
–4.2
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
V
= GND OR V
IN
TA = 25°C
V
= 0V
OUT
Figure 8. Output Short-Circuit Current vs. Power Supply Voltage
350
300
DIFFERENTIAL OUTPUT VOLTAGE, V
250
90 100 110 120 130 140 150
07876-007
LOAD RESISTOR, RL (Ω)
07876-010
Figure 10. Differential Output Voltage vs. Load Resistor
1.252
TA = 25°C
R
= 100Ω
CC
(mV)
OS
OFFSET VOLTAGE, V
07876-008
L
1.251
1.250
1.249
3.03.13.23.33.43.53.6
POWER SUPPLY VOLTAGE, VCC (V)
07876-011
Figure 11. Offset Voltage vs. Power Supply Voltage
Rev. 0 | Page 7 of 12
ADN4661
TA = 25°C
19
V
= 3.3V
CC
V
= 0V TO 3V
IN
17
C
= 15pF
(mA)
L
R
= 100Ω
CC
L
15
13
11
9
POWER SUPPL Y CURRENT, I
7
5
0.01 0. 1 1 10 100 1k
SWITCHING FREQUENCY (MHz)
Figure 12. Power Supply Current vs. Switching Frequency
10.0
TA = 25°C
f = 1MHz
9.5
V
= 0V TO 3V
IN
(mA)
C
= 15pF
L
CC
9.0
R
= 100Ω
L
8.5
1200
1100
t
PLHD
t
PHLD
TA = 25°C
f = 1MHz
C
= 15pF
L
R
= 100Ω
L
1000
DIFFERENT IAL PROPAGATION DELAY (ns)
900
3.0 3.1 3.2 3.3 3.4 3.5 3.6
07876-012
POWER SUPPLY VOLTAGE, VCC (V)
07876-015
Figure 15. Differential Propagation Delay vs. Power Supply Voltage
1200
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω
L
1100
t
PLHD
8.0
7.5
7.0
POWER SUPPL Y CURRENT, I
6.5
3.0 3.3 3.6
POWER SUPPLY VOLTAGE, V
(V)
CC
Figure 13. Power Supply Current vs. Power Supply Voltage
9
(mA)
8
CC
7
6
POWER SUPPL Y CURRENT, I
5
–40 –15 10 35 60 85
AMBIENT TEMPERATURE, T
A
(°C)
VCC = 3.3V
f = 1MHz
V
= 0V
IN
C
= 15pF
L
R
= 100Ω
L
Figure 14. Power Supply Current vs. Ambient Temperature
t
PHLD
1000
DIFFERENT IAL PROPAGATION DELAY (ns)
900
–40 –20 0 20 40 60 80 100
07876-013
AMBIENT TEMPERATURE, TA (°C)
07876-016
Figure 16. Differential Propagation Delay vs. Ambient Temperature
100
TA = 25°C
f = 1MHz
C
= 15pF
L
R
= 100Ω
80
(ps)
SKD1
L
60
40
20
DIFFERENTIAL SKEW , t
0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
07876-014
POWER SUPPLY VOLTAGE, VCC (V)
07876-017
Figure 17. Differential Skew vs. Power Supply Voltage
Rev. 0 | Page 8 of 12
ADN4661
50
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω
L
40
(ps)
SKD1
30
20
10
DIFFERENTIAL SKEW , t
0
–40 –20 0 20 40 60 80 100
AMBIENT TEM PERATURE, TA (°C)
Figure 18. Differential Skew vs. Ambient Temperature
400
380
360
t
THL
t
TLH
TA = 25°C
f = 1MHz
C
L
R
L
= 15pF
= 100Ω
400
VCC = 3.3V
f = 1MHz
C
= 15pF
L
R
= 100Ω
L
380
t
TLH
360
TRANSITION TIME (ps)
340
320
–40 –20 0 20 40 60 80 100
07876-018
AMBIENT TEMPERATURE, TA (°C)
t
THL
07876-020
Figure 20. Transition Time vs. Ambient Temperature
TRANSITION TIME (ps)
340
320
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER SUPPLY VOLTAGE, VCC (V)
07876-019
Figure 19. Transition Time vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
ADN4661
V
V
THEORY OF OPERATION
The ADN4661 is a single line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twistedpair cable or PCB backplane, to an LVDS receiver, where it
develops a voltage across a terminating resistor, R
. This resistor
T
is chosen to match the characteristic impedance of the medium,
typically around 100 . The differential voltage is detected by
the receiver and converted back into a single-ended logic signal.
When D
(current source) through R
is high (Logic 1), current flows out of the D
IN
and back to the D
T
OUT−
pin
OUT+
pin (current
sink). At the receiver, this current develops a positive differential
voltage across R
in a Logic 1 at the receiver output. When D
D
sinks current and D
OUT+
tial voltage across R
(with respect to the inverting input) and results
T
is low (Logic 0),
IN
sources current. A negative differen-
OUT−
results in a Logic 0 at the receiver output.
T
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.55 mA), developing between ±250 mV and ±450 mV
across a 100 termination resistor. The received voltage is centered
around the receiver offset of 1.2 V. Therefore, the noninverting
receiver input for Logic 1 is typically (1.2 V + [355 mV/2]) =
1.377 V, and the inverting receiver input is (1.2 V − [355 mV/2])
= 1.023 V. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across R
is
T
twice the differential voltage.
Current-mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas the current of voltage mode drivers
increases exponentially in most cases. This is caused by the
overlap as internal gates switch between high and low, which
causes currents to flow from the device power supply to ground.
A current-mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 21 shows a typical application for point-to-point data
transmission using the ADN4661 as the driver and the LVDS
receiver.
+3.3
+
0.1µF
V
CC
ADN4661 LVDS RECEIVER
D
IN
10µF
TANTALUM
D
OUT+
RT100Ω
D
OUT–
Figure 21. Typical Application Circuit
0.1µF
V
CC
D
IN+
D
IN–
GNDGND
+
10µF
TANTALUM
+3.3
D
OUT
07876-021
Rev. 0 | Page 10 of 12
ADN4661
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIG N.
85
1
1.27 (0.0500)
BSC
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 22. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN4661BRZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8
ADN4661BRZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8
1
Z = RoHS Compliant Part.
Rev. 0 | Page 11 of 12
ADN4661
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07876-0-12/08(0)
Rev. 0 | Page 12 of 12
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