ANALOG DEVICES ADN4661 Service Manual
Single, 3 V, CMOS, LVDS,
V
FEATURES
±15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
±355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
High Speed Differential Driver
ADN4661
FUNCTIONAL BLOCK DIAGRAM
CC
ADN4661
D
D
IN
NC = NO CONNECT
GNDNC NC NC
Figure 1.
D
OUT+
OUT–
07876-001
GENERAL DESCRIPTION
The ADN4661 is a single, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz) and ultra-low power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
±3.1 mA for driving a transmission medium such as a twistedpair cable. The transmitted signal develops a differential voltage
of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level
by a line receiver.
The ADN4661 and a companion LVDS receiver offer a new
solution to high speed point-to-point data transmission, and a
low power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADN4661
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
REVISION HISTORY
12/08—Revision 0: Initial Version
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 10
Applications Information .......................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Rev. 0 | Page 2 of 12
ADN4661
SPECIFICATIONS
VCC = 3 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications T
Table 1.
Parameter
LVDS OUT PUTS (D
1, 2
OUT+
Symbol Min Typ Max Unit Test Conditions
, D
)
OUT−
Differential Output Voltage VOD 250 355 450 mV See Figure 2 and Figure 4
ΔV
Change in Magnitude of VOD for Complementary
1 35 |mV| See Figure 2 and Figure 4
OD
Output States
Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 and Figure 4
3 25 |mV| See Figure 2 and Figure 4
Change in Magnitude of VOS for Complementary
ΔV
OS
Output States
Output High Voltage VOH 1.4 1.6 V See Figure 2 and Figure 4
Output Low Voltage VOL 0.90 1.1 V See Figure 2 and Figure 4
INPUTS (DIN, VCC)
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH −10 ±2 +10 μA VIN = 3.3 V or 2.4 V
Input Low Current IIL −10 ±1 +10 μA VIN = GND or 0.5 V
Input Clamp Voltage VCL −1.5 −0.6 V ICL = −18 mA
LVDS OUTPUT PROTECTION (D
Output Short-Circuit Current3 I
LVDS OUTPUT LEAKAGE (D
Power-Off Leakage I
OUT+
, D
OUT+
, D
)
OUT−
−5.7 −8.0 mA DIN = VCC, D
OS
)
OUT−
−10 ±1 +10 μA V
OFF
POWER SUPPLY
Supply Current, Unloaded ICC 4.0 8.0 mA No load, DIN = VCC or GND
Supply Current, Loaded I
7 10 mA DIN = VCC or GND
CCL
ESD PROTECTION
D
, D
OUT+
All Pins Except D
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
2
The ADN4661 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Pins ±15 kV Human body model
OUT−
, D
OUT+
±4 kV Human body model
OUT−
MIN
to T
, unless otherwise noted.
MAX
= 0 V or DIN = GND, D
OUT+
= VCC or GND, VCC = 0 V
OUT
OUT−
= 0 V
Rev. 0 | Page 3 of 12
ADN4661
V
V
V
AC CHARACTERISTICS
VCC = 3 V to 3.6 V; RL = 100 Ω; C
1
= 15 pF to GND; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Parameter2 Symbol Min Typ Max Unit Conditions/Comments
Differential Propagation Delay High to Low t
Differential Propagation Delay Low to High t
Differential Pulse Skew |t
PHLD
− t
|5 t
PLHD
Differential Part-to-Part Skew6 t
Differential Part-to-Part Skew7 t
Rise Time t
Fall Time t
Maximum Operating Frequency8 f
1
CL includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, t
4
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5
t
= |t
− t
SKD1
PHLD
same channel.
6
t
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
7
t
, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
SKD4
operating temperatures and voltage ranges, and across process distribution. t
8
f
generator input conditions: t
MAX
switching.
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
PLHD
= t
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
TLH
THL
0.3 0.8 1.5 ns See Figure 3 and Figure 4
PHLD
0.3 1.1 1.5 ns See Figure 3 and Figure 4
PLHD
0 0.3 0.7 ns See Figure 3 and Figure 4
SKD1
0 1.0 ns See Figure 3 and Figure 4
SKD3
0 1.2 Ns See Figure 3 and Figure 4
SKD4
0.2 0.5 1.0 ns See Figure 3 and Figure 4
TLH
0.2 0.5 1.0 ns See Figure 3 and Figure 4
THL
350 MHz See Figure 3
MAX
≤ 1 ns, and t
TLH
is defined as |maximum − minimum| differential propagation delay.
SKD4
≤ 1 ns.
THL
Test Circuits and Timing Diagrams
D
RL/2
R
L
/2
OUT+
V
VV
OSVOD
V
CC
CC
D
IN
3, 4
D
OUT–
Figure 2. Test Circuit for Driver V
CC
D
SIGNAL
GENERATOR
NOTES
INCLUDES PROBE AND JIG CAPACIT ANCE.
1. C
L
IN
50Ω
OD
C
L
C
L
and VOS
D
D
OUT+
OUT–
07876-002
07876-003
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
3
D
D
OUT–
OUT+
V
D
DIFF
IN
t
PLHD
V
OD
V
= D
DIFF
OUT+–DOUT–
t
TLH
t
PHLD
t
THL
1.5V
0V
V
OH
0V (DIFFERENTIAL)
V
OL
80%
0V
20%
07876-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 4 of 12
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