ANALOG DEVICES ADN4605 Service Manual
Crosspoint Switch
ADN4605
EQ
Rx Tx
PRE-
EMPHASIS
40 × 40
SWITCH
MATRIX
CONNECTION
MAP 1
CONNECTION
MAP 0
PARALLEL/SERIA L CONTROL
LOGIC INTERFACE
PRE-
EMPHASIS
LEVEL
SETTINGS
OUTPUT
LEVEL
SETTINGS
ADN4605
V
CC
V
EE
DV
CC
OP[39:0]
V
TTOA
,
V
TTOB
ON[39:0]
IP[39:0]
V
TTIA
,
V
TTIB
IN[39:0]
I
2
C/SPI
(UPDATE)
SDI/RE
SCL/SCK/
WE
RESET
SER/PAR
CS
EQUALIZATION
SETTINGS
DATA[1]
(UPDATE)
DATA[0]/
SDA/SDO
DATA[7:2]
ADDR[7:0]
09796-001
Rev. A
rights of third parties that may result from its use. Specifications subject to change without notice. No
Trademarks and registered trademarks are the propert y of their respective owners.
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
Data Sheet
FEATURES
DC to 4.25 Gbps per port NRZ data rate
Adjustable receive equalization
3 dB, 6 dB, or 12 dB boost
Compensates over 40 inches of FR4 at 4.25 Gbps
Adjustable transmit preemphasis/deemphasis
Programmable boost and output level
Compensates over 40 inches of FR4 at 4.25 Gbps
Low power
105 mW per channel at 2.5 V (400 mV p-p differential
output level swing)
40 × 40, fully differential, nonblocking array
Double rank connection programming with dual maps
Low jitter, typically <25 ps
Flexible 2.5 V to 3.3 V supply range
DC- or ac-coupled differential PECL/CML inputs
Differential CML outputs
Per-lane polarity inversion for routing ease
50 Ω on-chip I/O termination with disable feature
Supports 8b10b, scrambled or uncoded NRZ data
Serial (IC slave or SPI) control interface
Parallel control interface
4.25 Gbps 40 × 40 Digital
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI)
Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI, 4x Fibre Channel, Infiniband®, and GbE over backplane
Data storage networks
GENERAL DESCRIPTION
The ADN4605 is a 40 × 40 asynchronous, protocol agnostic,
digital crosspoint switch, with 40 differential PECL/CMLcompatible inputs and 40 differential programmable CML
outputs.
The ADN4605 is optimized for NRZ signaling with data rates of
up to 4.25 Gbps per port. Each port offers adjustable levels of
input equalization, programmable output swing, and output
preemphasis/deemphasis.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADN4605 nonblocking switch core implements a 40 × 40
crossbar and supports independent channel switching through
serial and parallel control interfaces. The ADN4605 has low
latency and very low channel-to-channel skew.
An I
the device for control of connectivity and other features.
The ADN4605 is assembled in a 35 mm × 35 mm, 352 BGA
package and operates over a temperature range of −40°C
to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
2
C, SPI, or parallel interface is used to communicate with
ADN4605 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
I2C Timing Specifications ............................................................ 5
SPI Timing Specifications ........................................................... 5
Parallel Mode Specifications ....................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 18
Theory of Operation ...................................................................... 24
Introduction ................................................................................ 24
Receivers ...................................................................................... 25
Polarity Inversion ....................................................................... 26
Switch Core ................................................................................. 27
Reset ............................................................................................. 28
Transmitters ................................................................................ 29
Termination ................................................................................. 32
I2C Serial Control Interface ........................................................... 33
I2C Dat a Write ............................................................................. 33
I2C Data Read .............................................................................. 34
SPI Serial Control Interface .......................................................... 35
Parallel Control Interface .............................................................. 38
Address Inputs: ADDR[7:0] ...................................................... 38
Data Inputs/Outputs: DATA[7:0]............................................. 38
Write Operation.......................................................................... 38
Read Operation........................................................................... 38
Register Map ................................................................................... 39
Applications Information .............................................................. 49
Supply Sequencing ..................................................................... 51
Power Dissipation....................................................................... 51
Output Compliance ................................................................... 51
TX/XPT HEADROOM ............................................................. 51
Printed Circuit Board (PCB) Layout Guidelines ................... 54
Outline Dimensions ....................................................................... 55
Ordering Guide ............................................................................... 55
REVISION HISTORY
11/11—Rev. 0 to Rev. A
Changes to Printed Circuit Board (PCB) Layout
Guidelines ........................................................................................ 54
Removed Figure 55, Renumbered Sequentially.......................... 54
6/11—Revision 0: Initial Version
Rev. A | Page 2 of 56
Data Sheet ADN4605
Deterministic Jitter
20 ps p-p
Residual Deterministic Jitter with
Data rate = 4.25 Gbps, 20 in. FR4, PE boost = 5.6 dB
22 ps p-p
Output Rise/Fall Time
20% to 80%
108 ps
Single-ended absolute voltage level, VH
VCC + 0.3
V
TERMINATION CHARACTERISTICS
POWER SUPPLY
V
, V
VEE = 0 V
2.5
VCC + 0.3
V
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VCC = 2.5 V, V
equalizer (EQ) = 1 (3 dB), data rate = 4.25 Gbps (PRBS7 data pattern), ac-coupled inputs and outputs, differential input swing = 800 mV p-p,
= 25°C, unless otherwise noted.
T
A
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Data Rate (DR) per Channel (NRZ) dc 4.25 Gbps
Random Jitter RMS, no channel 0.8 ps rms
Residual Deterministic Jitter with
Receive Equalization
Data rate = 4.25 Gbps, 40 in. FR4, EQ boost = 12 dB 25 ps p-p
= 2.5 V, V
TTIx
= 2.5 V, D VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, output level (OLEV) = 4 (16 mA), preemphasis (PE) = 0 (0 dB),
TTOx
Data rate ≤ 4.25 Gbps, no channel
Data rate = 4.25 Gbps, 20 in. FR4, EQ boost = 12 dB 14 ps p-p
Data rate = 4.25 Gbps, 30 in. FR4, EQ boost = 12 dB 15 ps p-p
Transmit Preemphasis
Data rate = 4.25 Gbps, 30 in. FR4, PE boost = 6.8 dB 28 ps p-p
Data rate = 4.25 Gbps, 40 in. FR4, PE boost = 9.5 dB 32 ps p-p
Propagation Delay Input to output 920 ps
Channel-to-Channel Skew Earliest input/output lane to latest input/output lane 200 ps
Switching Time Update logic switching to 50% output data 20 ns
INPUT CHARACTERISTICS
V
Minimum Differential Input
Voltage Swing
Maximum Differential Input
Voltage Swing
1
1
= VCC − 0.6 V 50 mV p-p diff
ICM
= VCC − 0.6 V 2000 mV p-p diff
V
ICM
Input Voltage Range Single-ended absolute voltage level, VL VEE + 1.0 V
Single-ended absolute voltage level, VH VCC + 0.3 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Differential, PE boost = 0 dB, default output level, at dc 670 800 875 mV p-p diff
Output Voltage Range Single-ended absolute voltage level, VL VCC – 1.4 V
Per-Port Output Current PE boost = 0 dB, default output level 16 mA
PE boost = 6 dB, default output level 32 mA
Resistance Differential, VCC = V
MIN
to V
MAX
, TA = T
MIN
to T
88 100 114 Ω
MAX
Temperature Coefficient 0.015 Ω/°C
Operating Range
VCC VEE = 0 V 2.25 2.5 3.6 V
DVCC VEE = 0 V 3.0 3.3 3.6 V
V
, V
TTIA
TTOA
VEE = 0 V 2.5 VCC + 0.3 V
TTIB
TTOB
Supply Current Inputs/outputs disabled (reset condition)
ICC 55 64 mA
I
0.3 1.1 mA
DVCC
I
+ I
TTIA
I
TTOA
Inputs floating 0 1.5 mA
TTIB
+ I
Outputs floating 0 1.5 mA
TTOB
Rev. A | Page 3 of 56
ADN4605 Data Sheet
I
+ I
11
15
mA
Parameter Conditions Min Typ Max Unit
Supply Current
ICC 1320 1410 mA
I
0.3 1.1 mA
DVCC
I
+ I
11 15 mA
TTIB
+ I
335 360 mA
TTOB
I
TTIA
TTOA
All outputs enabled, ac-coupled I/O,
200 mV I/O swings (400 mV p-p differential),
PE boost = 0 dB, 50 Ω far-end terminations
Supply Current All outputs enabled, ac-coupled I/O,
ICC 1370 1460 mA
I
0.3 1.1 mA
DVCC
I
+ I
11 15 mA
TTIA
TTIB
I
+ I
TTOA
665 715 mA
TTOB
400 mV I/O swings (800 mV p-p differential),
PE boost = 0 dB, 50 Ω far-end terminations
Supply Current All outputs enabled, ac-coupled I/O,
ICC 1850 1960 mA
I
0.3 1.1 mA
DVCC
TTIA
TTIB
I
+ I
TTOA
1340 1380
TTOB
400 mV I/O swings (800 mV p-p differential),
PE boost = 6 dB, 50 Ω far-end terminations
THERMAL CHARACTERISTICS
Operating Temperature2 −40 +85 °C
θJA Still air; JEDEC multilayer test board 11.6 °C/W
θJB 1 m/s air velocity 5.4 °C/W
θJC 1 m/s air velocity 0.72 °C/W
LOGIC CHARACTERISTICS
Input High Voltage Threshold (VIH) DVCC = 3.3 V 0.7 ×
Input Low Voltage Threshold (VIL) DVCC = 3.3 V 0.25 ×
Output High Voltage (VOH) IOH = −3 mA (I2C/SPI mode only) 0.75 ×
Output Low Voltage (VOL) IOL = +3 mA VEE 0.4 V
1
V
is the input common-mode voltage.
ICM
2
Junction temperature cannot exceed 125°C (see the Absolute Maximum Ratings section).
V
DV
CC
DV
CC
DV
DV
CC
V
CC
V
Rev. A | Page 4 of 56
Data Sheet ADN4605
SDA
SCL
t
f
t
LOW
t
HD;STA
t
r
t
HD;DAT
t
HIGH
t
SU;DAT
t
f
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
SPSrS
09796-002
Low Period of the SCL Clock
t
1.4
µs
t
1
t
2
t
3
t
5
t
6
t
4
t
7
t
8
D7
CS
SCLK
DIN
DOUT
D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0
09796-003
Parameter
Symbol
Min
Max
Unit
Data Setup Time Prior to SCLK Rising Edge
t5
10 ns
I2C TIMING SPECIFICATIONS
2
Figure 2. I
C Timing Diagram
Table 2. I2C Timing Specifications
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Hold Time for a Start Condition t
Setup Time for a Repeated Start Condition t
High Period of the SCL Clock t
Data Hold Time t
Data Setup Time t
Rise Time for Both SDA and SCL t
Fall Time for Both SDA and SCL t
Setup Time for Stop Condition t
Bus Free Time Between a Stop Condition and a Start Condition t
0 500+ kHz
SCL
HD; STA
SU; STA
LOW
HIGH
HD; DAT
SU; DAT
r
f
SU; STO
BUF
0.5 µs
0.5 µs
0.6 µs
0.02 µs
0.02 µs
1 300 ns
1 300 ns
0.5 µs
1 ns
Bus Idle Time After a Reset 20 ns
Reset Pulse Width 20 ns
SPI TIMING SPECIFICATIONS
Table 3. SPI Timing Specifications
SCK Clock Frequency f
CS to SCLK Setup Time
SCLK High Pulse Width t2 30 ns
SCLK Low Pulse Width t3 30 ns
Data Access Time After SCLK Falling Edge t4 45 ns
Data Hold Time After SCLK Rising Edge t6 30 ns
CS to SCLK Hold Time
CS to SDO High Impedance
Reset Pulse Width 20 ns
Figure 3. SPI Timing Diagram
10 MHz
SCK
0 ns
t
1
t7 0
45
t
8
ns
ns
Rev. A | Page 5 of 56
ADN4605 Data Sheet
UPDATE
1
0
WE
D7:D0
A7:A0
1
0
CS
1
0
0
1
t
6
t
8
t
3
t
5
t
1
t
2
t
4
t
7
09796-004
UPDAT E Pulse Width
t7
30
ns
1
0
RE
CS
1
0
D7:D0 DATA (ADDR 1)
ADDR 1
1
0
ADDR 2
A7:A0
1
0
DATA (ADDR 2)
t
1
t
2
t
6
t
5
t
3
t
4
09796-005
PARALLEL MODE SPECIFICATIONS
Figure 4. Parallel Mode Write Cycle
Table 4. Parallel Mode Write Cycle Timing Specifications
Limit
Parameter Symbol Min Typ Max Unit
Chip Select Setup Time t
1
Parallel Data Setup Time t2 0 ns
t
WE Pulse Width
30 50 ns
3
Parallel Data Hold Time t4 25 ns
WE Pulse Separation
WE to UPDAT E Delay
t
5
t6 40 ns
0 ns
25 ns
Chip Select Hold Time t8 0 ns
Reset Pulse Width 20 ns
Table 5. Parallel Mode Read Cycle Timing Specifications
Limit
Parameter Symbol Min Typ Max Unit
Chip Select Setup Time t
Parallel RE Setup to Valid Time
Data Access Time t3 25 50 ns
Address to RE Hold Time
Data to RE Hold Time
Chip Select Hold Time t
Figure 5. Parallel Mode Read Cycle
1
10 ns
t
2
25 ns
t
4
25 ns
t
5
6
Rev. A | Page 6 of 56
0 ns
5 ns
Data Sheet ADN4605
Storage Temperature Range
−65°C to +125°C
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
VCC to VEE 3.7 V
DVCC to VEE 3.7 V
V
, V
VCC + 0.6 V
TTIA
TTIB
V
, V
TTOA
VCC + 0.6 V
TTOB
Internal Power Dissipation1 8.4 W
Differential Input Voltage 2.0 V
Logic Input Voltage VEE – 0.3 V < VIN < VCC + 0.6 V
Junction Temperature 125°C
1
Internal power dissipation is for the device in free air.
TA = 27° C; θJA = 11.6°C/W in still air.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 7 of 56
ADN4605 Data Sheet
1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
V
EE
VEEV
EE
VEEV
EE
V
EE
ON39 OP39 ON37 OP37 ON35 OP35 ON33 OP33 ON31 OP31 ON29 OP29 ON27 OP27 ON25 OP25 ON23 OP23 ON21 OP21
ON38 OP38 ON36 OP36 ON34 OP34 ON32 OP32 ON30 OP30 ON28 OP28 ON26 OP26 ON24 OP24 ON22 OP22
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
V
TTOB
ON20 OP20
V
EE
V
EE
VEEV
EE
V
EE
DV
CC
DV
CC
V
CC
V
CC
V
CC
V
TTIB
V
TTIB
V
TTIB
V
TTIB
V
CC
CS
RE
WE
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
IP0
IN0IP1
IP2IN1
IN2IP3
IP4IN3
IN4IP5
IP6IN5
IN6IP7
IP8IN7
IN8IP9
IP10IN9
IP12IN11
IN12IP13
IN10IP11
IN14IP15
IP14IN13
IN16IP17
IN18IP19
IP16IN15
IP18IN17
IN19
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
VCCV
CC
VCCV
CC
V
CC
V
CC
VCCV
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
EE
V
EE
V
EE
VEEVEEVEEV
EE
V
CCVCC
V
EEVEEVEE
V
EE
V
EEVEE
V
EE
DV
CC
V
EE
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
TTIA
V
CC
V
CC
V
CC
DV
CC
V
EE
IN38 IP39
IP38
IN36
IP36
IN37
IP37
IN34
IP34
IN35
IP35
IN32
IP32
IN33
IP33
IN30
IP30
IN31
IP31
V
EE
V
EE
V
EE
IN39
IN28 IP29
IP28
IN26
IP26
IN27
IP27
IN24
IP24
IN25
IP25
IN22
IP22
IN23
IP23
IN20
IP20
IN21
IP21
IN29
V
EE
V
EE
V
CC
DV
CC
V
CC
V
CC
V
EE
VEEV
EE
V
EE
ON19
V
EE
V
EE
V
EE
V
EE
V
EE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
V
TTIB
V
TTIB
V
TTIB
V
TTIB
V
TTIB
V
TTIB
V
TTIB
V
EE
V
EE
V
CC
V
CC
V
CC
V
CC
V
CC
V
EE
V
EE
V
EEVEE
V
EE
VEEV
EE
OP0 ON0
OP1 ON1
OP2 ON2
OP3 ON3
OP4 ON4
OP5 ON5
OP6 ON6
OP7 ON7
OP8 ON8
OP9 ON9
OP10 ON10
OP11 ON11
OP12 ON12
OP13 ON13
OP14 ON14
OP15 ON15
OP16 ON16
OP17 ON17
OP18 ON18
OP19
VEEVEEV
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EEVEE
V
EE
V
EE
VEEV
EEVEE
V
EE
ADDR7
V
TTOA
V
TTOA
V
TTOAVTTOA
V
TTOA
V
TTOA
V
TTOA
V
TTOA
V
TTOA
V
TTOAVTTOA
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RESET
SER/
PAR
I
2
C/
SPI
ADN4605
TopView
09796-006
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Rev. A | Page 8 of 56
Data Sheet ADN4605
A1
V
Power
Negative Supply.
A2
VEE
Power
Negative Supply.
A20
ON23
Output
High Speed Output Complement.
A21
OP23
Output
High Speed Output.
A22
ON21
Output
High Speed Output Complement.
B16
OP28
Output
High Speed Output.
B17
ON26
Output
High Speed Output Complement.
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type Description
EE
A3 VEE Power Negative Supply.
A4 ON39 Output High Speed Output Complement.
A5 OP39 Output High Speed Output.
A6 ON37 Output High Speed Output Complement.
A7 OP37 Output High Speed Output.
A8 ON35 Output High Speed Output Complement.
A9 OP35 Output High Speed Output.
A10 ON33 Output High Speed Output Complement.
A11 OP33 Output High Speed Output.
A12 ON31 Output High Speed Output Complement.
A13 OP31 Output High Speed Output.
A14 ON29 Output High Speed Output Complement.
A15 OP29 Output High Speed Output.
A16 ON27 Output High Speed Output Complement.
A17 OP27 Output High Speed Output.
A18 ON25 Output High Speed Output Complement.
A19 OP25 Output High Speed Output.
A23 OP21 Output High Speed Output.
A24 VEE Power Negative Supply.
A25 VEE Power Negative Supply.
A26 VEE Power Negative Supply.
B1 VEE Power Negative Supply.
B2 VEE Power Negative Supply.
B3 VEE Power Negative Supply.
B4 VEE Power Negative Supply.
B5 ON38 Output High Speed Output Complement.
B6 OP38 Output High Speed Output.
B7 ON36 Output High Speed Output Complement.
B8 OP36 Output High Speed Output.
B9 ON34 Output High Speed Output Complement.
B10 OP34 Output High Speed Output.
B11 ON32 Output High Speed Output Complement.
B12 OP32 Output High Speed Output.
B13 ON30 Output High Speed Output Complement.
B14 OP30 Output High Speed Output.
B15 ON28 Output High Speed Output Complement.
B18 OP26 Output High Speed Output.
B19 ON24 Output High Speed Output Complement.
B20 OP24 Output High Speed Output.
B21 ON22 Output High Speed Output Complement.
B22 OP22 Output High Speed Output.
Rev. A | Page 9 of 56
ADN4605 Data Sheet
B24
OP20
Output
High Speed Output.
B25
VEE
Power
Negative Supply.
C13
V
Power
Output Termination Supply (B). The V
pins are normally tied to the
C16
VCC
Power
Positive Supply.
C17
VCC
Power
Positive Supply.
D5
VCC
Power
Positive Supply.
D6
VCC
Power
Positive Supply.
Pin No. Mnemonic Type Description
B23 ON20 Output High Speed Output Complement.
B26 VEE Power Negative Supply.
C1 VEE Power Negative Supply.
C2 IP0 Input High Speed Input.
C3 VEE Power Negative Supply.
C4 VCC Power Positive Supply.
C5 VCC Power Positive Supply.
C6 VCC Power Positive Supply.
C7 V
C8 V
C9 V
C10 V
TTOB
Power
TTOB
Power
TTOB
Power
TTOB
C11 VCC Power Positive Supply.
C12 VCC Power Positive Supply.
TTOB
C14 V
C15 V
Power
TTOB
Power
TTOB
Power
Output Termination Supply (B). The V
pins.
V
TTOA
Output Termination Supply (B). The V
pins.
V
TTOA
Output Termination Supply (B). T The V
V
pins.
TTOA
Output Termination Supply (B). The V
pins.
V
TTOA
V
pins.
TTOA
Output Termination Supply (B). The V
V
pins.
TTOA
Output Termination Supply (B). The V
pins.
V
TTOA
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
TTOB
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
C18 V
C19 V
C20 V
C21 V
Power
TTOB
Power
TTOB
Power
TTOB
Power
TTOB
Output Termination Supply (B). The V
pins.
V
TTOA
Output Termination Supply (B). The V
V
pins.
TTOA
Output Termination Supply (B). The V
pins.
V
TTOA
Output Termination Supply (B). The V
V
pins.
TTOA
C22 VCC Power Positive Supply.
C23 VCC Power Positive Supply.
C24 DVCC Power Digital Positive Supply.
C25 VEE Power Negative Supply.
C26 VEE Power Negative Supply.
D1 IP1 Input High Speed Input.
D2 IN0 Input High Speed Input Complement.
D3 VCC Power Positive Supply.
D4 DVCC Power Digital Positive Supply.
D7 VEE Power Negative Supply.
D8 VEE Power Negative Supply.
D9 VEE Power Negative Supply.
D10 VEE Power Negative Supply.
D11 VCC Power Positive Supply.
D12 VCC Power Positive Supply.
Rev. A | Page 10 of 56
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
pins are normally tied to the
TTOB
Data Sheet ADN4605
D14
VEE
Power
Negative Supply.
D15
VEE
Power
Negative Supply.
E26
IP39
Input
High Speed Input
F1
IP3
Input
High Speed Input
F26
IN37
Input
High Speed Input Complement.
G1
IN3
Input
High Speed Input Complement.
G25
IN36
Input
High Speed Input Complement.
G26
IP37
Input
High Speed Input.
H1
IP5
Input
High Speed Input.
Pin No. Mnemonic Type Description
D13 VEE Power Negative Supply.
D16 VCC Power Positive Supply.
D17 VCC Power Positive Supply.
D18 VEE Power Negative Supply.
D19 VEE Power Negative Supply.
D20 VEE Power Negative Supply.
D21 VEE Power Negative Supply.
D22 VCC Power Positive Supply.
D23 DVCC Power Digital Positive Supply.
D24 VCC Power Positive Supply.
D25 VEE Power Negative Supply.
D26 IN39 Input High Speed Input Complement.
E1 IN1 Input High Speed Input Complement.
E2 IP2 Input High Speed Input.
E3 VCC Power Positive Supply.
E4 VEE Power Negative Supply.
E23 VEE Power Negative Supply.
E24 VCC Power Positive Supply.
E25 IN38 Input High Speed Input Complement.
F2 IN2 Input High Speed Input Complement.
F3 V
TTIA
Power
Input Termination Supply (A). The V
pins.
V
TTIB
F4 VEE Power Negative Supply.
F23 VEE Power Negative Supply.
F24 V
TTIB
Power
Input Termination Supply (B). The V
pins.
V
TTIA
F25 IP38 Input High Speed Input.
G2 IP4 Input High Speed Input.
G3 V
Power
TTIA
Input Termination Supply (A). The V
V
pins.
TTIB
G4 VEE Power Negative Supply.
G23 VEE Power Negative Supply.
G24 V
Power
TTIB
Input Termination Supply (B). The V
pins.
V
TTIA
H2 IN4 Input High Speed Input Complement.
H3 V
Power
TTIA
Input Termination Supply (A). The V
pins.
V
TTIB
H4 VEE Power Negative Supply.
H23
WE/SCL/SCK
Control
Parallel control interface: First-Rank Write Strobe (WE) Active Low.
I2C Control Interface: I2C Clock (SCL).
SPI Control Interface: SPI Clock (SCK).
H24 V
Power
TTIB
Input Termination Supply (B). The V
pins.
V
TTIA
Rev. A | Page 11 of 56
pins are normally tied to the
TTIA
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
pins are normally tied to the
TTIB
ADN4605 Data Sheet
H26
IN35
Input
High Speed Input Complement.
J1
IN5
Input
High Speed Input Complement.
J23
RE/SDI
Control
Parallel Control Interface: Read Strobe (RE) Active Low.
K4
Control
Serial Control Interface Selection (SER).
M24
V
Power
Input Termination Supply (B). The V
pins are normally tied to the
Pin No. Mnemonic Type Description
H25 IP36 Input High Speed Input.
J2 IP6 Input High Speed Input.
J3 V
J4
J24 V
J25 IN34 Input High Speed Input.
J26 IP35 Input High Speed Input Complement.
K1 IP7 Input High Speed Input.
K2 IN6 Input High Speed Input Complement.
K3 VCC Power Power Supply.
K23
K24 VCC Power Positive Supply.
K25 IP34 Input High Speed Input.
K26 IN33 Input High Speed Input Complement.
L1 IN7 Input High Speed Input Complement.
L2 IP8 Input High Speed Input.
L3 VCC Power Positive Supply.
L4
L23 DATA0/SDA/SDO Control
L24 VCC Power Positive Supply.
L25 IN32 Input High Speed Input Complement.
L26 IP33 Input High Speed Input.
M1 IP9 Input High Speed Input.
M2 IN8 Input High Speed Input Complement.
M3 V
M4 ADDR0 Control Parallel Control Interface: Register Address Bit 0.
M23
M25 IP32 Input High Speed Input
M26 IN31 Input High Speed Input Complement.
N1 IN9 Input High Speed Input Complement.
N2 IP10 Input High Speed Input.
N3 V
N4 ADDR1 Control
Power
TTIA
2
C/SPI/ UPDAT E
I
Power
TTIB
PAR
SER/
CS
RESET
Power
TTIA
UPDAT E
DATA1/
TTIB
Power
TTIA
Input Termination Supply (A). The V
pins.
V
TTIB
Control
2
C Control Interface Selection (I2C).
I
SPI Control Interface Selection (
Parallel Control Interface (
SPI Control Interface: Data Input (SDI) SPI Control.
Input Termination Supply (B). The V
pins.
V
TTIA
Parallel Control Interface Selection (PA R ) Active Low.
Control Chip Select Active Low.
Control
Configuration Registers: Reset (Active Low). This pin is normally pulled
up to DV
Parallel Control Interface: Register Data Bit 0 (DATA0).
2
C Control Interface: Data In (SDA).
I
.
CC
SPI Control Interface: Data Out (SDO).
Input Termination Supply (A). The V
V
pins.
TTIB
2
C Control Interface: Slave Address Bit 0.
I
Control
Parallel Control Interface: Register (DATA1). Data Bit 1.
2
C or SPI Serial Control Interface (U P DAT E). Active Low.
I
V
pins.
TTIA
Input Termination Supply (A). The V
pins.
V
TTIB
Parallel Control Interface: Register Address Bit 1.
2
C Control Interface: Slave Address Bit 1.
I
pins are normally tied to the
TTIA
SPI) Active Low.
UPDAT E) Active Low.
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
TTIB
pins are normally tied to the
TTIA
Rev. A | Page 12 of 56
Data Sheet ADN4605
N24
V
Power
Input Termination Supply (B). The V
pins are normally tied to the
T24
VCC
Power
Positive Supply.
T25
IP28
Input
High Speed Input.
U23
DATA6
Control
Parallel Control Interface: Register Data Bit 6.
U24
V
Power
Pin No. Mnemonic Type Description
N23 DATA 2 Control Parallel Control Interface: Register Data Bit 2.
TTIB
V
pins.
TTIA
N25 IN30 Input High Speed Input Complement.
N26 IP31 Input High Speed Input.
P1 IP11 Input High Speed Input.
P2 IN10 Input High Speed Input Complement.
P3 V
P4 ADDR2 Control
Power
TTIA
Input Termination Supply (A). The V
V
pins.
TTIB
Parallel Control Interface: Register Address Bit 2.
2
C Control Interface: Slave Address Bit 2.
I
P23 DATA3 Control Parallel Control Interface: Register Data Bit 3.
P24 V
Power
TTIB
Input Termination Supply (B). The V
pins.
V
TTIA
P25 IP30 Input High Speed Input.
P26 IN29 Input High Speed Input Complement.
R1 IN11 Input High Speed Input Complement.
R2 IP12 Input High Speed Input.
R3 VCC Power Positive Supply.
R4 ADDR3 Control
Parallel Control Interface: Register Address Bit 3.
2
C Control Interface: Slave Address Bit 3.
I
R23 DATA4 Control Parallel Control Interface: Register Data Bit 4.
R24 VCC Power Positive Supply.
R25 IN28 Input High Speed Input Complement.
R26 IP29 Input High Speed Input.
T1 IP13 Input High Speed Input.
T2 IN12 Input High Speed Input Complement.
T3 VCC Power Positive Supply.
T4 ADDR4 Control
Parallel Control Interface: Register Address Bit 4.
I2C Control Interface: Slave Address Bit 4.
T23 DATA 5 Control Parallel Control Interface: Register Data Bit 5.
TTIB
pins are normally tied to the
TTIA
pins are normally tied to the
TTIB
T26 IN27 Input High Speed Input Complement.
U1 IN13 Input High Speed Input Complement.
U2 IP14 Input High Speed Input.
U3 V
Power
TTIA
U4 ADDR5 Control
TTIB
U25 IN26 Input High Speed Input Complement.
U26 IP27 Input High Speed Input.
V1 IP15 Input High Speed Input.
V2 IN14 Input High Speed Input Complement.
V3 V
Power
TTIA
V4 ADDR6 Control
V23 DATA 7 Control Parallel Control Interface: Register Data Bit 7.
Input Termination Supply (A). The V
pins.
V
TTIB
Parallel Control Interface: Register Address Bit 5.
2
C Control Interface: Slave Address Bit 5.
I
Input Termination Supply (B). The V
pins.
V
TTIA
Input Termination Supply (A). The V
V
pins.
TTIB
Parallel Control Interface: Register Address Bit 6.
2
C Control Interface: Slave Address Bit 6.
I
Rev. A | Page 13 of 56
pins are normally tied to the
TTIA
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
ADN4605 Data Sheet
AA25
IN22
Input
High Speed Input Complement.
AA26
IP23
Input
High Speed Input.
Pin No. Mnemonic Type Description
V24 V
V25 IP26 Input High Speed Input.
V26 IN25 Input High Speed Input Complement.
W1 IN15 Input High Speed Input Complement.
W2 IP16 Input High Speed Input.
W3 V
W4 ADDR7 Control
W23 VEE Power Negative Supply.
W24 V
W25 IN24 Input High Speed Input Complement.
W26 IP25 Input High Speed Input.
Y1 IP17 Input High Speed Input.
Y2 IN16 Input High Speed Input Complement.
Y3 V
Y4 VEE Power Negative Supply.
Y23 VEE Power Negative Supply.
Y24 V
Y25 IP24 Input High Speed Input.
Y26 IN23 Input High Speed Input Complement.
AA1 IN17 Input High Speed Input Complement.
AA2 IP18 Input High Speed Input.
AA3 VCC Power Positive Supply.
AA4 VEE Power Negative Supply.
AA23 VEE Power Negative Supply.
AA24 VCC Power Positive Supply.
Power
TTIB
Power
TTIA
Power
TTIB
Power
TTIA
Power
TTIB
Input Termination Supply (B). The V
pins.
V
TTIA
Input Termination Supply (A). The V
pins.
V
TTIB
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
Parallel Control Interface: Register Address Bit 7.
I2C Control Interface: Slave Address Bit 7.
Input Termination Supply (B). The V
pins.
V
TTIA
Input Termination Supply (A). The V
pins.
V
TTIB
Input Termination Supply (B). The V
pins.
V
TTIA
pins are normally tied to the
TTIB
pins are normally tied to the
TTIA
pins are normally tied to the
TTOB
AB1 IP19 Input High Speed Input.
AB2 IN18 Input High Speed Input Complement.
AB3 VCC Power Positive Supply.
AB4 VEE Power Negative Supply.
AB23 VEE Power Negative Supply.
AB24 VCC Power Positive Supply.
AB25 IP22 Input High Speed Input.
AB26 IN21 Input High Speed Input Complement.
AC1 IN19 Input High Speed Input Complement.
AC2 VEE Power Negative Supply.
AC3 VCC Power Positive Supply.
AC4 DVCC Power Digital Positive Supply.
AC5 VCC Power Positive Supply.
AC6 VCC Power Positive Supply.
AC7 VEE Power Negative Supply.
AC8 VEE Power Negative Supply.
AC9 VEE Power Negative Supply.
AC10 VEE Power Negative Supply.
Rev. A | Page 14 of 56
Data Sheet ADN4605
AC12
VCC
Power
Positive Supply.
AC13
VEE
Power
Negative Supply.
AD6
VCC
Power
Positive Supply.
AD7
V
Power
Output Termination Supply (A). The V
pins are normally tied to the
AD19
V
Power
Pin No. Mnemonic Type Description
AC11 VCC Power Positive Supply.
AC14 VEE Power Negative Supply.
AC15 VEE Power Negative Supply.
AC16 VCC Power Positive Supply.
AC17 VCC Power Positive Supply.
AC18 VEE Power Negative Supply.
AC19 VEE Power Negative Supply.
AC20 VEE Power Negative Supply.
AC21 VEE Power Negative Supply.
AC22 VCC Power Positive Supply.
AC23 DVCC Power Digital Positive Supply.
AC24 VCC Power Positive Supply.
AC25 IN20 Input High Speed Input Complement.
AC26 IP21 Input High Speed Input.
AD1 VEE Power Negative Supply.
AD2 VEE Power Negative Supply.
AD3 VEE Power Negative Supply.
AD4 VCC Power Positive Supply.
AD5 VCC Power Positive Supply.
AD8 V
AD9 V
AD10 V
TTOA
Power
TTOA
Power
TTOA
Power
TTOA
V
pins.
TTOB
Output Termination Supply (A). The V
pins.
V
TTOB
Output Termination Supply (A). The V
V
pins.
TTOB
Output Termination Supply (A). The V
pins.
V
TTOB
AD11 VCC Power Positive Supply.
AD12 VCC Power Positive Supply.
AD13 V
AD14 V
AD15 V
Power
TTOA
Power
TTOA
Power
TTOA
Output Termination Supply (A). The V
pins.
V
TTOB
Output Termination Supply (A). The V
V
pins.
TTOB
Output Termination Supply (A). The V
pins.
V
TTOB
AD16 VCC Power Positive Supply.
AD17 VCC Power Positive Supply.
AD18 V
AD20 V
AD21 V
Power
TTOA
TTOA
Power
TTOA
Power
TTOA
Output Termination Supply (A). The V
pins.
V
TTOB
Output Termination Supply (A). The V
V
pins.
TTOB
Output Termination Supply (A). The V
pins.
V
TTOB
Output Termination Supply (A). The V
V
pins.
TTOB
AD22 VCC Power Positive Supply.
AD23 VCC Power Positive Supply.
AD24 VEE Power Negative Supply.
AD25 IP20 Input High Speed Input.
AD26 VEE Power Negative Supply.
Rev. A | Page 15 of 56
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
pins are normally tied to the
TTOA
ADN4605 Data Sheet
AE2
VEE
Power
Negative Supply.
AE3
OP0
Output
High Speed Output.
AE22
ON18
Output
High Speed Output Complement.
AE23
VEE
Power
Negative Supply.
AF16
OP13
Output
High Speed Output.
AF17
ON13
Output
High Speed Output Complement.
Pin No. Mnemonic Type Description
AE1 VEE Power Negative Supply.
AE4 ON0 Output High Speed Output Complement.
AE5 OP2 Output High Speed Output.
AE6 ON2 Output High Speed Output Complement.
AE7 OP4 Output High Speed Output.
AE8 ON4 Output High Speed Output Complement.
AE9 OP6 Output High Speed Output.
AE10 ON6 Output High Speed Output Complement.
AE11 OP8 Output High Speed Output.
AE12 ON8 Output High Speed Output Complement.
AE13 OP10 Output High Speed Output.
AE14 ON10 Output High Speed Output Complement.
AE15 OP12 Output High Speed Output.
AE16 ON12 Output High Speed Output Complement.
AE17 OP14 Output High Speed Output.
AE18 ON14 Output High Speed Output Complement.
AE19 OP16 Output High Speed Output.
AE20 ON16 Output High Speed Output Complement.
AE21 OP18 Output High Speed Output.
AE24 VEE Power Negative Supply.
AE25 VEE Power Negative Supply.
AE26 VEE Power Negative Supply.
AF1 VEE Power Negative Supply.
AF2 VEE Power Negative Supply.
AF3 VEE Power Negative Supply.
AF4 OP1 Output High Speed Output.
AF5 ON1 Output High Speed Output Complement.
AF6 OP3 Output High Speed Output.
AF7 ON3 Output High Speed Output Complement.
AF8 OP5 Output High Speed Output.
AF9 ON5 Output High Speed Output Complement.
AF10 OP7 Output High Speed Output.
AF11 ON7 Output High Speed Output Complement.
AF12 OP9 Output High Speed Output.
AF13 ON9 Output High Speed Output Complement.
AF14 OP11 Output High Speed Output.
AF15 ON11 Output High Speed Output Complement.
AF18 OP15 Output High Speed Output.
AF19 ON15 Output High Speed Output Complement.
AF20 OP17 Output High Speed Output.
AF21 ON17 Output High Speed Output Complement.
AF22 OP19 Output High Speed Output.
Rev. A | Page 16 of 56
Data Sheet ADN4605
AF24
VEE
Power
Negative Supply.
AF25
VEE
Power
Negative Supply.
Pin No. Mnemonic Type Description
AF23 ON19 Output High Speed Output Complement.
AF26 VEE Power Negative Supply.
Rev. A | Page 17 of 56
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