ANALOG DEVICES ADN4604 Service Manual

4.25 Gbps,

p

V

FEATURES

DC to 4.25 Gbps per port NRZ data rate
Programmable receive equalization

12 dB boost at 2 GHz
Compensates 40 inches of FR4 at 4.25 Gbps

Programmable transmit preemphasis/deemphasis

Up to 12 dB boost at 4.25 Gbps

Compensates 40 inches of FR4 at 4.25 Gbps
Low power: 130 mW per channel at 3.3 V (outputs enabled)
16 × 16, fully differential, nonblocking array

Double rank connection programming with dual

connection maps
Low jitter, typically 20 ps
Flexible I/O supply range
DC- or ac-coupled differential CML inputs
Programmable CML output levels
Per-lane input P/N pair inversion for routing ease

50 Ω on-chip I/O termination

Supports 8b/10b, scrambled or uncoded NRZ data

2

Serial (I
100-lead TQFP, Pb-free package

C slave or SPI) control interface

16 × 16, Digital Cross

FUNCTIONAL BLOCK DIAGRAM

IP[15:0]

V

TTIE

V

TTIW

IN[15:0]

RESET

UPDATE

I2C/SPI

ADDR1/SDI

ADDR0/CS

SDA/SDO

SCL/SCK

,

DV

RX TX

EQ

CONNECTION

MAP 0

CONNECTION

MAP 1

SERIAL

INTERFACE

CONTROL

LOGIC

CC

16 × 16
SWITCH
MATRIX

Figure 1.

CC

V

EE

oint Switch

ADN4604

PRE-

EMPHASIS

OUTPUT

LEVEL

HOOKUP

TABLE

PER-PORT

SETTINGS

ADN4604

OUTPUT

LEVEL

OP[15:0]
V

TTON

V

TTOS

ON[15:0]

,

07934-001

APPLICATIONS

Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI: 10GBASE-KX4
Gigabit Ethernet over backplane: 1000BASE-KX
1×, 2×, and 4× Fibre Channel
InfiniBand®
Digital video (HDMI, DVI, DisplayPort, 3G-/HD-/SD-SDI)
Data storage networks

GENERAL DESCRIPTION

The ADN4604 is a 16 × 16 asynchronous, protocol agnostic,
digital crosspoint switch, with 16 differential PECL-/CML­compatible inputs and 16 differential CML outputs.

The ADN4604 is optimized for nonreturn-to-zero (NRZ) sig­naling with data rates of up to 4.25 Gbps per port. Each port
offers a fixed level of input equalization and programmable
output swing and output preemphasis.

The ADN4604 nonblocking switch core implements a 16 × 16
crossbar and supports independent channel switching through
the serial control interface. The ADN4604 has low latency and
very low channel-to-channel skew.

2

An I

C® or SPI interface is used to control the device and pro­vide access to advanced features, such as additional levels of
preemphasis and output disable.

The ADN4604 is packaged in a 100-lead TQFP package and
operates from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADN4604

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Specifications ............................................................... 3

I2C Timing Specifications ............................................................ 4

SPI Timing Specifications ........................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 16

Introduction ................................................................................ 16

Receivers ...................................................................................... 16

Switch Core ................................................................................. 17

Transmitters ................................................................................ 19

Termination ................................................................................. 23

I2C Serial Control Interface ........................................................... 24

Reset ............................................................................................. 24

I2C Data Write ............................................................................. 24

I2C Data Read .............................................................................. 25

SPI Serial Control Interface .......................................................... 26

Register Map ................................................................................... 28

Applications Information .............................................................. 32

Supply Sequencing ..................................................................... 34

Power Dissipation....................................................................... 34

Output Compliance ................................................................... 34

Printed Circuit Board (PCB) Layout Guidelines ................... 36

Outline Dimensions ....................................................................... 38

Ordering Guide .......................................................................... 38

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

ADN4604

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VCC = 3.3 V, V
input swing = 800 mV p-p, T

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Data Rate (DR) per Channel (NRZ) DC 4.25 Gbps
Deterministic Jitter Data rate = 4.25 Gbps, no channel 20 ps p-p
Random Jitter RMS, no channel 1 ps rms
Residual Deterministic Jitter with

Receive Equalization

Data rate = 4.25 Gbps, 40 in. FR4, EQ boost = 12 dB 70 ps p-p
Residual Deterministic Jitter with

Transmit Preemphasis

Data rate = 4.25 Gbps, 40 in. FR4, PE boost = 6 dB 35 ps p-p
Propagation Delay Input to output, EQ boost = 12 dB 800 ps
Channel-to-Channel Skew ±50 ps
Switching Time Update logic switching to 50% output data 100 ns
Output Rise/Fall Time 20% to 80% 75 ps

INPUT CHARACTERISTICS

Differential Input Voltage Swing V
Input Voltage Range Single-ended absolute voltage level, VL V

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential, PE boost = 0 dB, default output level, at dc 600 800 900 mV p-p diff
Output Voltage Range Single-ended absolute voltage level, VL V

Per-Port Output Current PE boost = 0 dB, default output level 16 mA
PE boost = 6 dB, default output level 32 mA

TERMINATION CHARACTERISTICS

Resistance Single-ended, V

Temperature Coefficient 0.025 Ω/°C

POWER SUPPLY

Operating Range

VCC V
DVCC V
V

TTIE

V

TTON

Supply Current Outputs disabled

ICC 95 110 mA
I

DVCC

I

+ I

TTIE

Supply Current All outputs enabled, ac-coupled I/O, 400 mV I/O swings

ICC 342 370 mA
I

DVCC

I

+ I

TTIE

Supply Current All outputs enabled, ac-coupled I/O, 400 mV I/O swings

ICC 486 540 mA
I

DVCC

I

+ I

TTIE

= 3.3 V, V

TTIx

= 3.3 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, data rate = 4.25 Gbps, ac-coupled inputs and outputs, differential

TTOx

= 27°C, unless otherwise noted.

A

Data rate = 4.25 Gbps, 20 in. FR4, EQ boost = 12 dB 27 ps p-p
Data rate = 4.25 Gbps, 30 in. FR4, EQ boost = 12 dB 43 ps p-p

Data rate = 4.25 Gbps, 20 in. FR4, PE boost = 4.2 dB 23 ps p-p
Data rate = 4.25 Gbps, 30 in. FR4, PE boost = 6 dB 25 ps p-p

1

= VCC − 0.6 V; VCC = V

ICM

Single-ended absolute voltage level, VH V

Single-ended absolute voltage level, VH V

= 2.2 V to 3.6 V, TA = T

V

TTO

= 0 V 2.7 3.3 3.6 V

EE

= 0 V 2.7 3.3 3.6 V

EE

, V

V

TTIW

, V

V

TTOS

= 0 V 1.3 3.3 VCC + 0.3 V

EE

= 0 V 2.22 3.3 VCC + 0.3 V

EE

= 2.7 V to 3.6 V, V

CC

MIN

MIN

to V

to T

, TA = T

MAX

MAX

MIN

= 2.2 V to 3.6 V,

TTI

;

to T

200 2000 mV p-p diff

MAX

+ 1.1 V

EE

+ 0.3 V

CC

– 1.3 V

CC

+ 0.2 V

CC

44 50 56 Ω

20 35 mA

+ I

+ I

TTIW

TTON

0 10 mA

TTOS

(800 mV p-p differential), PE boost = 0 dB,

20 35 mA

+ I

+ I

TTIW

TTON

256 280 mA

TTOS

50 Ω far-end terminations

(800 mV p-p differential), PE boost = 6 dB,

20 35 mA

+ I

+ I

TTIW

TTON

512 540 mA

TTOS

50 Ω far-end terminations

Rev. 0 | Page 3 of 40

ADN4604

Parameter Conditions Min Typ Max Unit

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C
θJA Still air; JEDEC 4-layer test board 24.9 °C/W
θJB Still air 11.6 °C/W
θJC At the exposed pad 0.95 °C/W

LOGIC CHARACTERISTICS

Input High Voltage Threshold (VIH) DVCC = 3.3 V 0.7 × VCC VCC V
Input Low Voltage Threshold (VIL) DVCC = 3.3 V VEE 0.3 × VCC V
Output High Voltage (VOH) 2 kΩ pull-up resistor to DVCC DVCC V
Output Low Voltage (VOL) IOL = 3 mA VEE 0.4 V

1

V

is the input common-mode voltage.

ICM

2

Minimum V

I2C TIMING SPECIFICATIONS

is only applicable for a limited range of output current settings. Refer to the Power Dissipation section.

TTO

SDA

t

SU:DAT

t

f

t

f

SCL

t

f

t

LOW

t

HD:STA

t

f

t

BUF

t

HD:STA

t

HD:DAT

t

HIGH

t

SU:STA

Figure 2. I

2

C Timing Diagram

t

SU:STO

SPSrS

07934-002

Table 2. I

2

C Timing Specifications

Parameter Symbol Min Max Unit

SCL Clock Frequency f
Hold Time for a Start Condition t
Setup Time for a Repeated Start Condition t
Low Period of the SCL Clock t
High Period of the SCL Clock t
Data Hold Time t
Data Setup Time t
Rise Time for Both SDA and SCL t
Fall Time for Both SDA and SCL t
Setup Time for Stop Condition t
Bus-Free Time Between a Stop Condition and a Start Condition t

0 400+ kHz

SCL

HD;STA

SU;STA

LOW

HIGH

HD;DAT

SU;DAT

r

f

SU;STO

BUF

0.6 μs

0.6 μs

1.3 μs

0.6 μs
0 μs
10 ns
1 300 ns
1 300 ns

0.6 μs

1 ns
Bus Idle Time After a Reset 10 ns
Reset Pulse Width 10 ns

Rev. 0 | Page 4 of 40

ADN4604

SPI TIMING SPECIFICATIONS

CS

SCK

SDI

t

1

A7

t

2

t

3

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

t

5

6

t

7

SDO

t

4

XXXXXXXXXXXXXXX X

t

8

07934-003

Figure 3. SPI Write Timing Diagram

t

9

CS

SCK

SDI

SDO

t

1

A7

X

t

2

t

3

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X D7D6D5D4D3D2D1 D0

t

t

5

6

t

4

t

7

t

8

07934-004

Figure 4. SPI Read Timing Diagram

Table 3. SPI Timing Specifications

Parameter Symbol Min Max Unit

SCK Clock Frequency f
CS to SCK Setup Time

0 10 MHz

SCK

10 ns

t

1

SCK High Pulse Width t2 40 ns
SCK Low Pulse Width t3 40 ns
Data Access Time After SCK Falling Edge t4 35 ns
Data Setup Time Prior to SCK Rising Edge t5 20 ns
Data Hold Time After SCK Rising Edge t6 10 ns
CS to SCK Hold Time
CS to SDO High Impedance

CS High Pulse Width

t

10

7

40

t

8

10

t

9

ns
ns
ns

Rev. 0 | Page 5 of 40

ADN4604

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VCC to VEE 3.7 V
DVCC to VEE 3.7 V
V

, V

V

TTIE

TTIW

V

, V

TTON

V

TTOS

Internal Power Dissipation1 4.9 W
Differential Input Voltage 2.0 V
Logic Input Voltage VEE – 0.3 V < VIN < VCC + 0.6 V
Storage Temperature Range −65°C to +125°C
Lead Temperature Range 300°C
Junction Temperature 150°C

1

Internal power dissipation is for the device in free air.

T

= 27°C; θJA = 24.9°C/W in still air.

A

+ 0.6 V

CC

+ 0.6 V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 40

ADN4604

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

IP0
IN0

V

IP1
IN1

V

TTIW

IP2
IN2

V

IP3
IN3

V

IP4
IN4

V

IP5
IN5

V

TTIW

IP6
IN6

V

IP7
IN7

UPDATE

CC

OP1599ON15

DV

98

100

1

PIN 1

2
3
4

CC

5
6
7
8
9

10

EE

11
12
13

CC

14
15
16

EE

17
18
19
20
21
22

CC

23
24
25

26

27

28

29

EE

V

OP0

ON0

I2C/SPI

TTON

EE

OP1496ON1497V

95

32

30

31

OP1

ON1

TTOS

V

CC

OP1290ON1291V

OP1393ON1394V

89

92

ADN4604

TOP VIEW

(Not to Scale)

36

33

34

35

37 38

CC

V

OP2

ON2

EE

V

OP3

ON3

CC

EE

OP1187ON1188V

86

40

41

39

CC

V

OP4

ON4

TTON

OP1084ON1085V

83

42

43

44

OP5

ON5

TTOS

V

EE

OP981ON982V

80

45

46

47

EE

V

OP6

ON6

SCL/SCK77OP878ON879V

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57

56

55
54

53

52
51

48

49

50

OP7

ON7

ADDR1/SDI

NOTES

1. THE ADN4604 TQFP HAS AN EXPO SED PADDLE (EP AD) ON THE UNDERSIDE OF THE PACKAG E THAT AIDS
IN HEAT DISS IPATION. THE EPAD MUST BE E LECTRICALLY CONNECTED T O THE V
TO MEET THERMAL SPE CIFICATIONS.

2. SDA/SCL/ADDR1/0 FOR I
SCK/SDO/S DI/CS FOR S PI OPERATI ON.

2

C OPERATIO N.

SUPPLY PLANE

EE

Figure 5. Pin Configuration

SDA/SDO
IN15
IP15
V

CC

IN14
IP14
V

TTIE

IN13
IP13
V

EE

IN12
IP12
V

CC

IN11
IP11
V

EE

IN10
IP10
V

TTIE

IN9
IP9
V

CC

IN8
IP8
ADDR0/CS

07934-005

Rev. 0 | Page 7 of 40

ADN4604

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type Description

1

RESET

2 IP0 Input High Speed Input.
3 IN0 Input High Speed Input Complement.

Power Positive Supply.

4, 13, 22, 35, 41, 54, 63,

V

CC

72, 85, 91
5 IP1 Input High Speed Input.
6 IN1 Input High Speed Input Complement.
7, 19 V

Power

TTIW

8 IP2 Input High Speed Input.
9 IN2 Input High Speed Input Complement.

Power Negative Supply.

10, 16, 29, 38, 47, 60, 66,

V

EE

79, 88, 97, EPAD
11 IP3 Input High Speed Input.
12 IN3 Input High Speed Input Complement.
14 IP4 Input High Speed Input.
15 IN4 Input High Speed Input Complement.
17 IP5 Input High Speed Input.
18 IN5 Input High Speed Input Complement.
20 IP6 Input High Speed Input.
21 IN6 Input High Speed Input Complement.
23 IP7 Input High Speed Input.
24 IN7 Input High Speed Input Complement.
25

26

UPDATE

I2C

/SPI
27 OP0 Output High Speed Output.
28 ON0 Output High Speed Output Complement.
30 OP1 Output High Speed Output.
31 ON1 Output High Speed Output Complement.
32, 44 V

Power Output Termination Supply (South). These pins are normally tied to the V

TTOS

33 OP2 Output High Speed Output.
34 ON2 Output High Speed Output Complement.
36 OP3 Output High Speed Output.
37 ON3 Output High Speed Output Complement.
39 OP4 Output High Speed Output.
40 ON4 Output High Speed Output Complement.
42 OP5 Output High Speed Output.
43 ON5 Output High Speed Output Complement.
45 OP6 Output High Speed Output.
46 ON6 Output High Speed Output Complement.
48 OP7 Output High Speed Output.
49 ON7 Output High Speed Output Complement.
50 ADDR1/SDI Control I2C Slave Address Bit 1 (MSB) or SPI Data Input.
51

ADDR0/CS
52 IP8 Input High Speed Input.
53 IN8 Input High Speed Input Complement.
55 IP9 Input High Speed Input.
56 IN9 Input High Speed Input Complement.

Control

Control

Control I

Control I

Configuration Registers Reset, Active Low. This pin is normally pulled up

.

to DV

CC

Input Termination Supply (West). These pins are normally tied to the
V

pins.

TTIE

Second Rank Write Enable, Active Low. This pin is normally pulled up
to DV

.

CC

2

C/SPI Control Interface Selection, I2C Active Low.

2

C Slave Address Bit 0 (LSB) or SPI Chip Select (Active Low).

Rev. 0 | Page 8 of 40

TTON

pins.

ADN4604

Pin No. Mnemonic Type Description

57, 69 V
58 IP10 Input High Speed Input.
59 IN10 Input High Speed Input Complement.
61 IP11 Input High Speed Input.
62 IN11 Input High Speed Input Complement.
64 IP12 Input High Speed Input.
65 IN12 Input High Speed Input Complement.
67 IP13 Input High Speed Input.
68 IN13 Input High Speed Input Complement.
70 IP14 Input High Speed Input.
71 IN14 Input High Speed Input Complement.
73 IP15 Input High Speed Input.
74 IN15 Input High Speed Input Complement.
75 SDA/SDO Control I2C Data or SPI Data Output.
76 SCL/SCK Control I2C Clock or SPI Clock.
77 OP8 Output High Speed Output.
78 ON8 Output High Speed Output Complement.
80 OP9 Output High Speed Output.
81 ON9 Output High Speed Output Complement.
82, 94 V

83 OP10 Output High Speed Output.
84 ON10 Output High Speed Output Complement.
86 OP11 Output High Speed Output.
87 ON11 Output High Speed Output Complement.
89 OP12 Output High Speed Output.
90 ON12 Output High Speed Output Complement.
92 OP13 Output High Speed Output.
93 ON13 Output High Speed Output Complement.
95 OP14 Output High Speed Output.
96 ON14 Output High Speed Output Complement.
98 OP15 Output High Speed Output.
99 ON15 Output High Speed Output Complement.
100 DVCC Power Digital Positive Supply.

Power Input Termination Supply (East). These pins are normally tied to the V

TTIE

Power

TTON

Output Termination Supply (North). These pins are normally tied to

TTOS

pins.

the V

TTIW

pins.

Rev. 0 | Page 9 of 40

ADN4604

V

V

V

V

V

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 3.3 V, V
input swing = 800 mV p-p, T

= 3.3 V, V

TTIx

= 3.3 V, DVCC = 3.3 V, V

TTOx

= 27°C, unless otherwise noted.

A

= 0 V, RL = 50 Ω, data rate = 4.25 Gbps, ac-coupled inputs and outputs, differential

EE

200mV/DI

0.167IU/DIV

REFERENCE EYE DIAGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

INPUT
PIN

ADN4604

AC-COUPLED
EVALUATION

OUTPUT

BOARD

50Ω CABLES

2 2

PIN

50Ω

TP2TP1

OSCILLOSCOPE

HIGH SPEED

SAMPLING

07934-006

Figure 6. Standard Test Circuit

200mV/DI

0.167IU/DIV

Figure 7. 3.25 Gbps Input Eye (TP1 from Figure 6)

07934-007

200mV/DI

0.167IU/DIV

Figure 9. 3.25 Gbps Output Eye (TP2 from Figure 6)

07934-009

200mV/DI

0.167IU/DIV

Figure 8. 4.25 Gbps Input Eye (TP1 from Figure 6)

07934-008

200mV/DI

0.167IU/DIV

Figure 10. 4.25 Gbps Output Eye (TP2 from Figure 6)

4-010
0793

Rev. 0 | Page 10 of 40

ADN4604

V

V

V

V

V

200mV/DI

RE

0.167IU/DIV

FERENCE EYE DIAGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

Figure 11. Equalization Test Circuit

FR4 TEST BACKP LANE

DIFFERENTIAL
STRIPLI NE TRACES

TP1

8mils WI DE, 8mils S P ACE ,
8mils DIEL ECTRIC HEI GHT

LENGTHS = 10 INCHES, 20 INCHES ,
30 INCHES, 40 I NCHES

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

PIN

ADN4604

AC-COUPLED

EVALUATION

BOARD

2 2

PIN

50Ω CABLES

TP3

50Ω

HIGH

SPEED

SAMPLING

OSCILLOSCOPE

07934-011

200mV/DI

0.167IU/DIV

Figure 12. 4.25 Gbps Input Eye, 20 Inch FR4 Input Channel

(TP2 from Figure 11)

200mV/DI

0.167IU/DIV

Figu re 13. 4.25 Gb ps Input Eye, 40-Inch FR4 Input Channel

(TP2 from Figure 11)

200mV/DI

07934-012

0.167IU/DIV

07934-014

Figure 14. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, EQ = 12 dB

(TP3 from Figure 11)

200mV/DI

07934-013

0.167IU/DIV

07934-015

Figure 15. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, EQ = 12 dB

(TP3 from Figure 11)

Rev. 0 | Page 11 of 40

ADN4604

V

V

V

V

V

200mV/DI

0.167IU/DIV

REFERENCE EYE DIAGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

Figure 16. Preemphasis Test Circuit

TP1

INPUT

OUTPUT

PIN

ADN4604

AC-COUPLED

EVALUATION

BOARD

50Ω CABLES

2 2

PIN

FR4 TEST BACKPLANE

DIFFERENTIAL
STRIPLI NE T RACES

TP2

8mils WI DE , 8mils SP ACE,
8mils DIEL ECTRIC HEI GHT

LENGTHS = 10 INCHES, 20 INCHES,
30 INCHES, 40 INCHE S

50Ω CABLES

2 2

TP3

50Ω

HIGH

SPEED

SAMPLING

OSCILLOSCOPE

07934-016

200mV/DI

0.167IU/DIV

07934-017

Figu re 17. 4.25 G bps Ou tput Eye, 20-Inch FR4 Out put Channel, PE = 0 dB

(TP3 from Figure 16)

200mV/DI

0.167IU/DIV

07934-018

Figure 18. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 0 dB

(TP3 from Figure 16)

200mV/DI

0.167IU/DIV

07934-019

Figure 19. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, PE = 4.2 dB

(TP3 from Figure 16)

200mV/DI

0.167IU/DIV

07934-020

Figure 20. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 6 dB

(TP3 from Figure 16)

Rev. 0 | Page 12 of 40