ANALOG DEVICES ADN4600 Service Manual

4.25 Gbps, 8 × 8,

p

A

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FEATURES

Full 8 × 8 crossbar connectivity
Fully buffered signal path supports multicast and broadcast

operation
Optimized for dc to 4.25 Gbps data
Programmable receive equalization
Compensates for up to 30 in. of FR4 @ 4.25 Gbps
Programmable transmit pre-emphasis/de-emphasis
Compensates for up to 30 in. of FR4 @ 4.25 Gbps
Flexible 1.8 V to 3.3 V core supply
Per lane positive/negative (P/N) pair inversion for routing ease
Low power: 125 mW/channel at 4.25 Gbps
DC- or ac-coupled differential CML inputs
Programmable CML output levels
50 Ω on-chip termination

−40°C to +85°C temperature range operation
Supports 8b10b, scrambled or uncoded nonreturn-to-zero

(NRZ) data

2

I

C control interface

Package: 64-lead LFCSP

APPLICATIONS

1×, 2×, 4× FibreChannel
XAUI
Gigabit Ethernet over backplane
10GBase-CX4
InfiniBand®
50 Ω cables

GENERAL DESCRIPTION

The ADN4600 is an asynchronous, nonblocking crosspoint
switch with eight differential PECL-/CML-compatible inputs
with programmable equalization and eight differential CML
outputs with programmable output levels and pre-emphasis or
de-emphasis. The operation of this device is optimized for NRZ
data at rates up to 4.25 Gbps.

The receive inputs provide programmable equalization with
nine settings to compensate for up to 30 in. of FR4 and
programmable pre-emphasis with seven settings to compensate
for up to 30 in. of FR4 at 4.25 Gbps.

Asynchronous Cross

oint Switch

ADN4600

FUNCTIONAL BLOCK DIAGRAM

ADN4600

RECEIVE

IP[7:0]

IN[7:0]

DDR[1:0]

RESETB

EQUALIZATION

EQ PE

SCL
SDA

The ADN4600 nonblocking switch core implements an 8 × 8
crossbar and supports independent channel switching through the

2

I

C control interface. Every channel implements an asynchronous
path supporting NRZ data rates from dc to 4.25 Gbps. Each
channel is fully independent of other channels. The ADN4600
has low latency and very low channel-to-channel skew.

The main application for the ADN4600 is to support switching
on the backplane, line card, or cable interface sides of serial links.

The ADN4600 is packaged in a 9 mm × 9 mm, 64-lead LFCSP
package and operates from −40°C to +85°C.

CROSSPOINT

ARRAY

CONTROL LOG IC

Figure 1.

TRANSMIT

PRE-EMPHASIS

OP[7:0]

ON[7:0]

07061-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADN4600

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Specifications ............................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

REVISION HISTORY

6/08—Revision 0: Initial Version

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 13

Introduction ................................................................................ 13

Receivers ...................................................................................... 13

Switch Core ................................................................................. 15

Transmitters ................................................................................ 16

I2C Control Interface .................................................................. 22

PCB Design Guidelines ............................................................. 24

Control Register Map ..................................................................... 25

Package Outline Dimensions ........................................................ 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 2

ADN4600

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SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VCC = 1.8 V, VEE = 0 V, V
T

= 25°C, unless otherwise noted.

A

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Data Rate per Channel In NRZ format 4.25 Gbps
Deterministic Jitter Data rate < 4.25 Gbps; BER = 1e − 12 30 ps p-p
Random Jitter VCC = 1.8 V 1.5 ps rms
Residual Deterministic Jitter with

Receive Equalization

Residual Deterministic Jitter with

Transmit Pre-Emphasis

Output Rise/Fall Time 20% to 80% 75 ps
Channel-to-Channel Skew 50 ps
Propagation Delay 1 ns

OUTPUT PRE-EMPHASIS

Equalization Method One-tap programmable pre-emphasis
Maximum Boost 800 mV p-p output swing 6 dB

Pre-Emphasis Tap Range Minimum 2 mA
Maximum 12 mA

INPUT EQUALIZATION

Minimum Boost EQBY = 1 1.5 dB
Maximum Boost Maximum boost occurs @ 2.125 GHz 22 dB
Number of Equalization Steps 8 Steps
Gain Step Size 2.5 dB

INPUT CHARACTERISTICS

Input Voltage Swing Differential, V
Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.4 V p-p
Single-ended absolute voltage level, VH maximum VCC + 0.5 V p-p
Input Resistance Single-ended 45 50 55 Ω
Input Return Loss Measured at 2.5 GHz 5 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing @ dc, differential, PE = 0, default, VCC = 1.8 V 635 740 870 mV p-p
@ dc, differential, PE = 0, default, VCC = 3.3 V 800 mV p-p
@ dc, differential, PE = 0, min output level2, VCC = 1.8 V 100 mV p-p
@ dc, differential, PE = 0, min output level2, VCC = 3.3 V 100 mV p-p
@ dc, differential, PE = 0, max output level2, VCC = 1.8 V 1300 mV p-p
@ dc, differential, PE = 0, max output level2, VCC = 3.3 V 1800 mV p-p
Output Voltage Range

Output Current Minimum output current per channel 2 mA
Maximum output current per channel, VCC = 1.8 V 21
Output Resistance Single ended 45 50 55 Ω
Output Return Loss Measured at 2.5 GHz 5 dB

TTI

= V

= VCC, RL = 50 , differential output swing = 800 mV p-p differential, 4.25 Gbps, PRBS 27 − 1,

TTO

Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 0.16 UI
Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 0.20 UI
Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 0.13 UI
Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 0.18 UI

200 mV p-p output swing 12 dB

1

= VCC − 0.6 V; VCC = 3.3 V 300 2000 mV p-p

ICM

Single-ended absolute voltage level,
TxHeadroom = 0; V

Single-ended absolute voltage level,
TxHeadroom = 0; V

Single-ended absolute voltage level,
TxHeadroom = 1; V

Single-ended absolute voltage level,
TxHeadroom = 1; V

min

L

max

H

min

L

max

H

Rev. 0 | Page 3 of 3

V

V

V

V

− 1.1 V

CC

+ 0.6 V

CC

− 1.2 V

CC

+ 0.6 V

CC

ADN4600

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Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range

VCC V
DVCC V
V

(VEE + 0.4 V + 0.5 × VID) < V

TTI

V

(VCC − 1.1 V + 0.5 × VOD) < V

TTO

Supply Current

I

All outputs enabled 63 69 mA

TTO

3

ICC All outputs enabled 460 565 mA
I

EE

I

TTO

ICC Single channel enabled 173 214 mA
IEE Single channel enabled 205 mA

LOGIC CHARACTERISTICS

Input High (VIH) DVCC = 3.3 V 2.5 V
Input Low (VIL) 1.0 V
Output High (VOH) 2.5 V
Output Low (VOL) 1.0 V

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C
θJA 22 °C/W

1

V

is the input common-mode voltage.

ICM

2

Programmable via I2C.

3

Assumes dc-coupled outputs. For ac-coupled outputs, I

= 0 V 1.7 1.8 3.6 V

EE

= 0 V, DVCC ≤ (VCC + 1.3 V) 3.0 3.3 3.6 V

EE

< (VCC + 0.5 V)

TTI

V

EE

1.8 3.6 V

+

0.4

< (VCC + 0.5 V)

TTO

V

CC

1.8 3.6 V

−

1.1

All outputs enabled 586 mA
Single channel enabled 16 18 mA

currents will double.

TTO

Rev. 0 | Page 4 of 4

ADN4600

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TIMING SPECIFICATIONS

Table 2. I2C Timing Parameters

Parameter Min Max Unit Description

f

0 400 kHz SCL clock frequency

SCL

t

0.6 N/A

HD;STA

t

0.6 N/A

SU;STA

t

1.3 N/A

LOW

t

0.6 N/A

HIGH

t

0 N/A

HD;DAT

t

10 N/A ns Data setup time

SU;DAT

μs
μs
μs
μs
μs

tr 1 300 ns Rise time for both SDA and SCL
tf 1 300 ns Fall time for both SDA and SCL
t

0.6 N/A

SU;STO

t

1 N/A ns Bus-free time between a stop and a start condition

BUF

μs

CIO 5 7 Pf Capacitance for each I/O pin

I2C Timing Specifications

SDA

Hold time for a start condition
Setup time for a repeated start condition
Low period of the SCL clock
High period of the SCL clock
Data hold time

Setup time for a stop condition

t

t

HD:DAT

SU:DAT

t

f

t

HIGH

t

f

Figure 2. I

t

SU:STA

2

C Timing Diagram

t

HD:STA

t

SU:STO

t

f

t

BUF

SPSrS

07061-010

SCL

t

f

t

LOW

t

HD:STA

Rev. 0 | Page 5 of 5

ADN4600

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VCC to VEE 3.7 V
V

V

TTI

V

V

TTO

Internal Power Dissipation
Differential Input Voltage 2.0 V
Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V
Storage Temperature Range −65°C to +125°C
Lead Temperature 300°C

+ 0.6 V

CC

+ 0.6 V

CC

4.26 W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 6

ADN4600

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VEE

VCC

VEE

OP0

ON0

VCC

OP1

ON1

VTTO

OP2

ON2

VEE

OP3

ON3

ADDR1

646362616059585756555453525150

ADDR0

49

RESETB

VEE

IN0
IP0

VCC

IN1
IP1

VTTI

IN2
IP2

10

VEE

11

IN3

12

IP3

13

DVCC

14

VCC

15

VEE

16

NOTES

1. PAD ON BOT TOM OF PACKAGE MUST BE CONNECTED TO VEE.

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

171819202122232425262728293031

VEE

VCC

OP7

ON7

ADN4600

TOP VIEW

(Not to Scale)

OP6

ON6

VCC

VTTO

OP5

VEE

OP4

ON5

VEE

ON4

48

SCL

47

SDA

46

VEE

45

IP7

44

IN7

43

VCC

42

IP6

41

IN6

40

VTTI

39

IP5

38

IN5

37

VEE

36

IP4

35

IN4

34

VCC

33

VEE

32

VEE

VCC

07061-002

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 RESETB Control Reset Input (Active Low)
2, 11, 16, 17, 27,

VEE Power Negative Supply
30, 32, 33, 37,
46, 53, 62, 64

3, 6, 9, 12, 35,

IN0 to IN7 I/O High Speed Inputs
38, 41, 44

4, 7, 10, 13, 36,

IP0 to IP7 I/O High Speed Input Complements
39, 42, 45

5, 15, 18, 21, 31,

VCC Power Positive Supply
34, 43, 59, 63

8, 40 VTTI Power Input Termination Supply
14 DVCC Power Digital Positive Supply (3.3 V)
19, 22, 25, 28,

ON7 to ON0 I/O High Speed Outputs
51, 54, 57, 60

20, 23, 26, 29,

OP7 to ON0 I/O High Speed Output Complements
52, 55, 58, 61

24, 56 VTTO Power Output Termination Supply
47 SDA Control I2C Control Interface Data Input/Output
48 SCL Control I2C Control Interface Clock Input
49 ADDR0 Control I2C Control Interface Address LSB
50 ADDR1 Control I2C Control Interface Address MSB
EPAD Power Connect to VEE

Rev. 0 | Page 7 of 7

ADN4600

V

V

V

V

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 to Figure 8 were obtained using the standard test circuit shown in Figure 4.

DATA OUT

PATTERN

GENERATOR

2 2

INPUT
PIN

ADN4600

AC-COUPL ED
EVALUATION

OUTPUT

BOARD

50Ω CABLES

Figure 4. Standard Test Circuit (No Channel)

50Ω CABLES

2 2

PIN

50Ω

TP2TP1

OSCILLOSCOPE

HIGH SPEED

SAMPLING

07061-011

200mV/DI

50ps/DIV

07061-012

Figure 5. 3.25 Gbps Input Eye

(TP1 from Figure 4)

200mV/DI

50ps/DIV

07061-013

Figure 6. 4.25 Gbps Input Eye

(TP1 from Figure 4)

200mV/DI

50ps/DIV

Figure 7. 3.25 Gbps Output Eye, No Channel

(TP2 from Figure 4)

200mV/DI

50ps/DIV

Figure 8. 4.25 Gbps Output Eye, No Channel

(TP2 from Figure 4)

07061-014

07061-015

Rev. 0 | Page 8 of 8

ADN4600

V

V

V

V

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Figure 10 to Figure 13 were obtained using the standard test circuit shown in Figure 9.

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

FR4 TEST BACKPLANE

DIFFERENTIAL
STRIPLINE TRACES

TP1

8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 30''

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

PIN

ADN4600

AC-COUPLED
EVALUATION

BOARD

Figure 9. Input Equalization Test Circuit, FR4 (See Figure 5 and Figure 6 for the Reference Eye Diagrams at TP1)

2 2

PIN

50Ω CABLES

50Ω

HIGH SPEED

TP3

SAMPLING

OSCILLOSCOPE

07061-016

200mV/DI

50ps/DIV

Figure 10. 3.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

200mV/DI

50ps/DIV

Figure 11. 4.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

200mV/DI

07061-017

50ps/DIV

07061-019

Figure 12. 3.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

200mV/DI

07061-018

50ps/DIV

07061-020

Figure 13. 4.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

Rev. 0 | Page 9 of 9