Analog Devices ADN2928 prb Datasheet
XFP Single Chip Transceiver IC
Preliminary Technical Data
FEATURES
Fully integrated limiting amplifier and signal conditioner
transceiver IC
Meets XFP Telecoms and Datacoms module requirements
Supports OC-192, OC-192-FEC, 10GE, 10GFC, 10GE G.709
Line and system loop-back modes
Integrated Rx limiting amplifier with 10 mV sensitivity
Tx path equalizer for up to 12 inches of FR4
Rx loss of signal (LOS) detector
CML serial data interface
Supply power: 760 mW
3.3 V and 1.8 V power supplies
XFI signalling
Flip-chip, 49-pin BGA, 6 mm × 6 mm package
Temperature range 0°C to 85°C
Power down mode
APPLICATIONS
XFP MSA module receive/transmit signal conditioner
SONET OC-192, (+FEC) transponders
10 gigabit Ethernet optical transceivers
10 gigabit small form factor modules
Test equipment
Serial backplane applications
XFP MODULE
TXDATA
12” FR4
OTX
ADN2928
PRODUCT OVERVIEW
The ADN2928 provides the transmit and receive functions of
quantization, loss of signal detect, and clock and data recovery
at rates from 9.953 Gbps to 11.1 Gbps. The part is designed with
the flexibility to allow it to be used in either Telecoms or
Datacoms XFP module applications. The key advantages of this
circuit’s delay and phase-locked loop architecture are that it
provides a low jitter transfer bandwidth of 1 MHz, while also
exceeding the jitter tolerance requirements of XFP, SONET,
Gigabit Ethernet and Fibre Channel. The architecture also
provides fundamentally 0 dB of Jitter peaking.
XFP MODULE
ORX
12” FR4
RXDATA
SERDES/
ASIC
RXDATA
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
12” FR4
ADN2928
ORX
Figure 1. Typical XFP Application
12” FR4
SERDES/
ASIC
TXDATA
05264-001
ADN2928
OTX
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADN2928 Preliminary Technical Data
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Receive Path Specifications ............................................................. 4
Transmit Path Specifications........................................................... 5
Common Specifications................................................................... 6
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
General Description ......................................................................... 9
2
I
C Interface .................................................................................. 9
Receive Path .................................................................................. 9
Transmit Path................................................................................ 9
System Functions.......................................................................... 9
Applications Information .............................................................. 10
PCB Design Guidelines ............................................................. 10
Outline Dimensions....................................................................... 11
Ordering Guide........................................................................... 11
REVISION HISTORY
3/05—Revision PrB: Preliminary Version
Rev. PrB | Page 2 of 12
Preliminary Technical Data ADN2928
FUNCTIONAL BLOCK DIAGRAM
CFT
TxOUTP
TxOUTN
RxLOS
RxTHR
RxINP
RxINN
COSR
VDDT_1.8
VDDR_1.8
VDD_3.3
GN D
LimitingAmp
1.0V
regulator
CVDD_1.0
FL L
TxCDR
RxC DR
FL L
CFR
RxLOL
TxLOL
TxLOL
I2C
REGISTERS
Equalizer
4
4
TxINP
TxINN
COST
REFCKP
REFCKN
RxOUTP
RxOUT N
CDR_NR
SCK
SDA
PDN
Figure 2. ADN2928 Functional Block Diagram
Rev. PrB | Page 3 of 12
ADN2928 Preliminary Technical Data
RECEIVE PATH SPECIFICATIONS
Table 1.
PARAMETER Conditions Min Typ Max Unit
QUANTIZER DC CHARACTERISTICS ac coupled, PIN-NIN
Peak-to-Peak Differential Input
Input Sensitivity, VSENSE 10 mV
Input Offset Voltage 1 mV
Input Current µA
Input RMS Noise 365 µV
QUANTIZER AC CHARACTERISTICS Differential
−3 dB Bandwidth
Input Data Rate 9.953 11.1 Gbps
Small Signal Gain 45 dB
S11
Random Jitter 0.3 ps rms
Input Resistance 100 Ω
Input Capacitance TBD pF
Power Supply Rejection 100 mV p-p @ 100 MHz on VDD 60 dB
LEVEL DETECT
LOS Signal Level 5 mV
Hysteresis 3 dB
PHASE-LOCKED LOOP CHARACTERISTICS
For All Input Data Rates
Jitter Transfer BW - Telecoms 1.2 3 MHz
Jitter Transfer BW - Datacoms 1.2 3 MHz
Jitter Tolerance - Telecoms
Sinusoidal Jitter Tolerance Meets SONET mask.
Jitter Tolerance - Datacoms
Sinusoidal Jitter Tolerance Meets 802.3ae mask
Jitter Generation rms 0.7 ps rms
Jitter Peaking Measured 50 kHz – 80 MHz
< 120 kHz 0 dB
> 120 kHz 0 dB
CML OUTPUTS - RxOUTP/N
Single-Ended Output Swing Vse 200 425 mV
Differential Output Swing Vdiff 400 850 mV
Output High Voltage Voh TBD
Output Low Voltage Vol TBD
Rise Time 20% – 80% 24 ps
Fall Time 80% – 20% 24 ps
PIN-NIN, BER < 10
@ 10 GHz 10 GHz
−12
1.8 V
−12
dB
Rev. PrB | Page 4 of 12
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