ANALOG DEVICES ADN2892 Service Manual

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3.3 V, 4.25 Gbps,

FEATURES

Input sensitivity: 3.5 mV p-p 70 ps rise/fall times CML outputs: 750 mV p-p differential Bandwidth selectable for multirate 1×/2×/4× FC modules Optional LOS output inversion Programmable LOS detector: 3.5 mV to 35 mV Rx signal strength indicator (RSSI)

SFF-8472-compliant average power measurement Single-supply operation: 3.3 V Low power dissipation: 160 mW Available in space-saving, 3 mm × 3 mm, 16-lead LFCSP Extended temperature range: −40°C to +95°C SFP reference design available

APPLICATIONS

1×, 2×, and 4× FC transceivers SFP/SFF/GBIC optical transceivers GbE transceivers Backplane receivers

Limiting Amplifier

ADN2892

GENERAL DESCRIPTION

The ADN2892 is a 4.25 Gbps limiting amplifier with integrated loss of signal (LOS) detection circuitry and a received signal strength indicator (RSSI). This part is optimized for Fibre Channel (FC) and Gigabit Ethernet (GbE) optoelectronic conversion applications. The ADN2892 has a differential input sensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-p differential input overload voltage. The ADN2892 has current mode logic (CML) outputs with controlled rise and fall times.

The ADN2892 has a selectable low-pass filter with a −3 dB cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the filter can limit the relaxation oscillation of a low cost CD laser used in a legacy 1 Gbps FC transmitter. The limited BW also reduces the rms noise and in turn improves the receiver optical sensitivity for a lower data rate application, such as 1× FC and GbE.

By monitoring the bias current through a photodiode, the onchip RSSI detector measures the average power received with 2% typical linearity over the entire valid input range of the photodiode. The on-chip RSSI detector facilitates SFF-8472compliant optical transceivers by eliminating the need for external RSSI detector circuitry.

FUNCTIONAL BLOCK DIAGRAM

AVCC

AVEE

ADN2892

ADN2882

Rev. 0.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

NIN

PD_VCC

PD_CATHODE

LPF

50Ω

3.5kΩ V

REF

Figure 1. RSSI Function Capable—Applications Setup Block Diagram

Additional features include a programmable loss-of-signal (LOS) detector and output squelch. The ADN2892 is available in a 3 mm × 3 mm, 16-lead LFCSP.

BW_SEL SQUELCH

RSSI/LOS

DETECTOR

THRADJ

DRVEE

DRVCC

50Ω 50Ω

LOS_INV

www.analog.com

OUTP

OUTN

LOS

RSSI_OUT

V+

10kΩ

ADuC7020

04986-001

ADN2892

TABLE OF CONTENTS

Specifications..................................................................................... 3

Squelch Mode ............................................................................. 10

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Limiting Amplifier ..................................................................... 10

Loss-of-Signal (LOS) Detector ................................................. 10

Received Signal Strength Indicator (RSSI).............................. 10

REVISION HISTORY

4/05—Revision 0: Initial Version

BW_SEL (Bandwidth Selection) Mode................................... 10

LOS_INV (Lose of Signal_Invert) Mode................................ 10

Applications..................................................................................... 11

PCB Design Guidelines ............................................................. 11

Pad Coating and Pb-Free Soldering ........................................ 12

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

ADN2892

SPECIFICATIONS

Test Conditions: VCC = 2.9 V to 3.6 V, VEE = 0 V, TA = −40°C to +95°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

QUANTIZER DC CHARACTERISTICS

Input Voltage Range VCC − 1.2 VCC − 0.2 V At PIN or NIN, dc-coupled Input Common Mode 2.1 2.7 V DC-coupled Peak-to-Peak Differential Input Range 2.0 V p-p PIN − NIN, ac-coupled Input Sensitivity 6.6 3.5 mV p-p PIN − NIN, BER ≤ 1 × 10 Input Offset Voltage 100 µV Input RMS Noise 235 µV rms Input Resistance 50 Ω Single-ended Input Capacitance 0.65 pF

QUANTIZER AC CHARACTERISTICS

Input Data Rate 1.0 4.25 Gbps Small Signal Gain 51 dB Differential S11 −10 dB Differential, f < 4.25 GHz S22 −10 dB Differential, f < 4.25 GHz Random Jitter 3.0 3.9 ps rms Input ≥ 10 mV p-p, 4× FC, K28.7 pattern Deterministic Jitter 10 21.0 ps p-p Input ≥ 10 mV p-p, 4× FC, K28.5 pattern Low Frequency Cutoff 30 kHz Power Supply Rejection 45 dB 100 kHz < f < 10 MHz

LOSS OF SIGNAL DETECTOR (LOS)

LOS Assert Level 2.9 3.5 4.8 mV p-p R

22.4 35 55.0 mV p-p R

THRADJ

= 100 kΩ = 1 kΩ

Electrical Hysteresis 2.5 5.0 dB 1.0 Gbps, PRBS 223 − 1

2.8 5.0 dB 4× FC, PRBS 223 − 1 LOS Assert Time 950 ns DC-coupled LOS Deassert Time 62 ns DC-coupled

RSSI

Input Current Range 5 1000 µA RSSI Output Linearity 2 % 5 µA ≤ IIN ≤ 1000 µA Gain 1.0 mA/mA I

RSSI/IPD_CATHODE

Offset 145 nA Compliance Voltage (At PD_CATHODE) VCC − 0.4 V I V

− 0.9 V I

PD_CATHODE

= 5 µA = 1000 µA

BW_SEL (BANDWIDTH SELECTION)

Channel Bandwidth 1.5 GHz

−3 dB cutoff frequency of the on-chip, two-pole, low-pass filter, when BW_SEL = 0

POWER SUPPLIES

OPERATING TEMPERATURE RANGE −40 +25 +95 °C T

2.9 3.3 3.6 V 48 54 mA

to T

MIN

MAX

CML OUTPUT CHARACTERISTICS

Output Impedance 50 Ω Single-ended Output Voltage Swing 600 750 940 V p-p Differential Output Rise and Fall Time 70 103 ps 20% to 80%

−10

Rev. 0 | Page 3 of 16

ADN2892

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SQUELCH, LOS_INV, AND BW_SEL)

VIH, Input High Voltage 2.0 V

VIL, Input Low Voltage 0.8 V

Input Current (SQUELCH, LOS_INV) 39 µA

Input Current (BW_SEL) −38 µA

LOGIC OUTPUTS (LOS)

VOH, Output High Voltage 2.4 V

VOL, Output Low Voltage 0.4 V

, VIN = 2.4 V, 100 kΩ pull-down,

INH

on-chip resistor

, VIN = 0.0 V, 100 kΩ pull-up,

INL

on-chip resistor

Open drain output, 4.7 kΩ − 10 kΩ pull-up resistor to VCC

Rev. 0 | Page 4 of 16

ADN2892

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Power Supply Voltage 4.2 V Minimum Voltage

(All Inputs and Outputs)

Maximum Voltage

(All Inputs and Outputs) Storage Temperature −65°C to +150°C Operating Temperature Range −40°C to +95°C Production Soldering Temperature J-STD-20 Junction Temperature 125°C

VEE − 0.4 V

VCC + 0.4 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for 4-layer PCB with exposed paddle soldered to GND.

Table 3.

Package Type θ

3 mm × 3 mm, 16-lead LFCSP 28 °C/W

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 5 of 16

ADN2892

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PD_CATHODE

PD_VCC15RSSI_OUT

BW_SEL

SQUELCH

LOS

LOS_INV

DRVCC OUTP OUTN DRVEE

04986-002

NIN

1 2

ADN2892

TOP VIEW

(Not to Scale)

THRADJ

AVCC

AVEE

Figure 2. Pin Configuration

Note that there is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias.

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Type1Description

1 AVCC P Analog Power Supply. 2 PIN AI Differential Data Input, Positive Port, 50 Ω On-Chip Termination. 3 NIN AI Differential Data Input, Negative Port, 50 Ω On-Chip Termination. 4 AVEE P Analog Ground. 5 THRADJ AO LOS Threshold Adjust Resistor. 6 BW_SEL DI With one 100 kΩ on-chip, pull-up resistor, BW_SEL = 0 for 1×/2× FC, BW_SEL = 1 for 4× FC. 7 LOS_INV DI

With one 100 kΩ on-chip, pull-down resistor, LOS_INV = 1 inverts the LOS output

to be active low for SFF. 8 LOS DO LOS Detector Output, Open Collector. 9 DRVEE P Output Buffer Ground. 10 OUTN DO Differential Data Output, CML, Negative Port, 50 Ω, On-Chip Termination. 11 OUTP DO Differential Data Output, CML, Positive Port, 50 Ω, On-Chip Termination. 12 DRVCC P Output Buffer Power Supply. 13 SQUELCH DI Disable Outputs, 100 kΩ On-Chip, Pull-Down Resistor. 14 RSSI_OUT AO Average Current Output. 15 PD_VCC P Power Input for RSSI Measurement. 16 PD_CATHODE AO Photodiode Bias Voltage. Exposed Pad Pad P Connect to Ground.

P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.

Rev. 0 | Page 6 of 16

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ANALOG DEVICES ADN2892 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual