ANALOG DEVICES ADN2871 Service Manual

3.3 V, 50 Mbps to 4.25 Gbps,

V

FEATURES

SFP/SFF and SFF-8472 MSA-compliant
SFP reference design available
50 Mbps to 4.25 Gbps operation
Automatic average power control
Typical rise/fall time 60 ps
Supports VCSEL, DFB, and FP lasers
Bias current range 2 mA to 100 mA
Modulation current range 5 mA to 90 mA
Laser fail alarm and automatic laser shutdown (ALS)
Bias and modulation current monitoring

3.3 V operation
4 mm × 4 mm LFCSP
Voltage setpoint control
Resistor setpoint control
Pin-compatible with

APPLICATIONS

1×/2×/4× Fibre Channel SFP/SFF modules
Multirate OC3 to OC48-FEC SFP/SFF modules
LX-4 modules
DWDM/CWDM SFP modules
1GE SFP/SFF transceiver modules
VCSEL, DFB, and FP transmitters

Tx_DISABLE

Tx_FAULT

ADN2870

MICROCONTRO LLER

DAC

DAC

Figure 1. Application Diagram of Voltage Setpoint Control with a Single-Ended Laser Interface

ADI

ADC

1kΩ

1kΩ

V

GND

GND

CC

MPD

PAVSET

PAVREF

RPAV

ERREF

ERSET

Single-Loop, Laser Diode Driver

ADN2871

GENERAL DESCRIPTION

The ADN2871 laser diode driver is designed for advanced SFP
and SFF modules, using SFF-8472 digital diagnostics. The
ADN2871 supports operation from 50 Mbps to 4.25 Gbps.

Average power and extinction ratio can be set with a voltage
provided by a microcontroller DAC or by a trimmable resistor
or digital potentiometer. The average power control loop is
implemented using feedback from a monitor photodiode. The
part provides bias and modulation current monitoring as well
as fail alarms and automatic laser shutdown (ALS). The device
interfaces easily with the Analog Devices, Inc. ADuC70xx
family of MicroConverters® and with the ADN289x family of
limiting amplifiers to make a complete SFP/SFF transceiver
solution. An SFP reference design is available. The product is
pin-compatible with the ADN2870 dual-loop LDD, allowing
one PC board layout to work with either device. For dual-loop
applications, refer to the

The product is available in a space-saving 4 mm × 4 mm LFCSP
specified over the −40°C to +85°C temperature range.

Figure 1 shows an application diagram of the voltage setpoint
control with single-ended laser interface.
differential laser interface.

CC

V

CC

ALSFAIL

CONTROL

×100

IBMON IMMON

V

GND

CC

470Ω1kΩ

GND GND

IMODN

IMOD

ADN2871

PAVCAP

GND

ADN2870 data sheet.

V

CC

L

R

IMODP

100Ω

NC

IBIAS

CCBIAS

V

CC

R

Figure 36 shows a

V

CC

LASER

DATAP

DATAN

Z

05228-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

ADN2871

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

SFP Timing Specifications............................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Optical Waveforms........................................................................... 8

Multirate Performance Using Low Cost Fabry Perot TOSA

NEC NX7315UA .......................................................................... 8

Performance Over Temperature Using DFB Tosa

SUMITOMO SLT2486................................................................. 8

Typical Performance Characteristics ............................................. 9

Single-Ended Output ................................................................... 9

Differential Output..................................................................... 10

Performance Characteristics..................................................... 11

Theory of Operation ...................................................................... 13

Laser Control .............................................................................. 13

Control Methods........................................................................ 13

Volt a ge S etp o int C al i brat i on ..................................................... 13

Resistor Setpoint Calibration.................................................... 15

I

Monitoring .......................................................................... 15

MPD

Loop Bandwidth Selection ........................................................ 16

Power Consumption .................................................................. 16

Automatic Laser Shutdown (Tx_Disable)............................... 16

Bias and Modulation Monitor Currents.................................. 16

Data Inputs .................................................................................. 17

Laser Diode Interfacing............................................................. 17

Alarms.......................................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

2/07—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changes to Figure 29 and Figure 30............................................. 14

Changes to Resistor Setpoint Calibration Section, Figure 32,

and Figure 33................................................................................... 15

Inserted Power-On Sequence in Resistor Setpoint

Mode Section................................................................................... 15

Changes to Loop Bandwidth Selection Section.......................... 16

Changes to Laser Diode Interfacing Section, Figure 35, and

Figure 36 ..........................................................................................17

Changes to Table 6.......................................................................... 18

6/05—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADN2871

SPECIFICATIONS

VCC = 3.0 V to 3.6 V. All specifications T

MIN

to T

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

LASER BIAS CURRENT (IBIAS)

Output Current (IBIAS) 2 100 mA
Compliance Voltage 1.2 V
IBIAS when ALS is High 0.1 mA

MODULATION CURRENT (IMODP, IMODN)

2

Output Current (IMOD) 5 90 mA
Compliance Voltage 1.5 V
IMOD when ALS is High 0.1 mA 5 mA < IMOD < 90 mA
Rise Time, Single-Ended Output
Fall Time, Single-Ended Output
Random Jitter, Single-Ended Output
Deterministic Jitter, Single-Ended Output

2, 3

2, 3

2, 3

3, 4

Pulse-Width Distortion, Single-Ended Output
Rise Time, Differential Output
Fall Time, Differential Output
Random Jitter, Differential Output
Deterministic Jitter, Differential Output

3, 5

3, 5

3, 5

3, 6

Pulse-Width Distortion, Differential Output
Rise Time, Differential Output
Fall Time, Differential Output
Random Jitter, Differential Output
Deterministic Jitter, Differential Output

3, 5

3, 5

3, 5

3, 7

Pulse-Width Distortion, Differential Output

AVERAGE POWER SET (PAVSET)

Pin Capacitance 80 pF
Voltage 1.1 1.2 1.3 V
Photodiode Monitor Current (Average Current) 50 1200 μA Resistor setpoint mode

EXTINCTION RATIO SET INPUT (ERSET)

Resistance Range 1.5 25 kΩ Resistor setpoint mode
Resistance Range 0.99 1 1.01 kΩ Voltage setpoint mode

AVERAGE POWER REFERENCE VOLTAGE INPUT (PAVREF)

Voltage Range 0.07 1 V

Photodiode Monitor Current (Average Current) 70 1000 μA

EXTINCTION RATIO REFERENCE VOLTAGE INPUT (ERREF)

Voltage Range 0.05 0.9 V

ERREF Voltage to IMOD Gain 100 mA/V

DATA INPUTS (DATAP, DATAN)

8

V p-p (Differential) 0.4 2.4 V AC-coupled
Input Impedance (Single-Ended) 50 Ω

LOGIC INPUTS (ALS)

V

IH

V

IL

1

, unless otherwise noted. Typical values as specified at 25°C.

MAX

CC

V

CC

V

60 104 ps 5 mA < IMOD < 90 mA
60 96 ps 5 mA < IMOD < 90 mA

0.8 1.1 ps (rms) 5 mA < IMOD < 90 mA
19 35 ps 20 mA < IMOD < 90 mA

2, 3

21 30 ps 20 mA < IMOD < 90 mA

47.1 ps 5 mA < IMOD < 30 mA
46 ps 5 mA < IMOD < 30 mA

0.64 ps (rms) 5 mA < IMOD < 30 mA
12 ps 5 mA < IMOD < 30 mA

3, 5

2.1 ps 5 mA < IMOD < 30 mA
56 ps 5 mA < IMOD < 90 mA
55 ps 5 mA < IMOD < 90 mA

0.61 ps (rms) 5 mA < IMOD < 90 mA
17 ps 5 mA < IMOD < 90 mA

3, 5

1.6 ps 5 mA < IMOD < 90 mA

2 V

0.8 V

Voltage setpoint mode
(RPAV fixed at 1 kΩ)

Voltage setpoint mode
(RPAV fixed at 1 kΩ)

Voltage setpoint mode
(RERSET fixed at 1 kΩ)

Rev. A | Page 3 of 20

ADN2871

Parameter Min Typ Max Unit Conditions/Comments

ALARM OUTPUT (FAIL)

V

OFF

V

ON

IBMON/IMMON DIVISION RATIO

IBIAS/IBMON

IBIAS/IBMON

IBIAS/IBMON

IBIAS/IBMON Stability

IMOD/IMMON 42 A/A

IBMON Compliance Voltage 0 1.3 V
SUPPLY

11

I

CC

VCC (with respect to GND)

1

Temperature range: –40°C to +85°C.

2

Measured into a single-ended 15 Ω load (22 Ω resistor in parallel with digital scope 50 Ω input) using a 1111111100000000 pattern at 2.5 Gbps, shown in Figure 2.

3

Guaranteed by design and characterization. Not production tested.

4

Measured into a single-ended 15 Ω load using a K28.5 pattern at 2.5 Gbps, shown in Figure 2.

5

Measured into a differential 30 Ω (43 Ω differential resistor in parallel with a digital scope of 50 Ω input) load using a 1111111100000000 pattern at 4.25 Gbps, as

shown in Figure 3.

6

Measured into a differential 30 Ω load using a K28.5 pattern at 4.25 Gbps, as shown in Figure 3.

7

Measured into a differential 30 Ω load using a K28.5 pattern at 2.7Gbps, as shown in Figure 3.

8

When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.

9

Guaranteed by design. Not production tested.

10

IBIAS/IBMON ratio stability is defined in SFF-8472 Revision 9 over temperature and supply variation.

11

See the ICC minimum for power calculation in the Power Consumption section.

12

All VCC pins should be shorted together.

9

>1.8 V

Voltage required at FAIL for
IBIAS and IMOD to turn off
when FAIL asserted

<1.3 V

Voltage required at FAIL for
IBIAS and IMOD to stay on
when FAIL asserted

3

3

3

3, 10

76 94 112 A/A 2 mA < IBIAS < 11 mA
85 100 115 A/A 11 mA < IBIAS < 50 mA
92 100 108 A/A 50 mA < IBIAS < 100 mA
±5 % 10 mA < IBIAS < 100 mA

32 mA When IBIAS = IMOD = 0

12

ADN2871

22Ω

IMODP

Figure 2. High Speed Electrical Test Single-Ended Output Circuit

3.0 3.3 3.6 V

V

CCVCC

R

L

C

BIAS TEE

80kHz → 27GHz

BIAS TEE

80kHz → 27GHz

TO HIGH SPEED
DIGITAL
OSCILLOSCOPE
50Ω INPUT

05228-002

V

CC

L

C

C

L

V

CC

BIAS TEE

80kHz → 27GHz

TO HIGH SPEED
DIGITAL
OSCILLOSCOPE
50Ω DIFFERENTIAL INPUT

ADN2871

IMODN

IMODP

43Ω

R

Figure 3. High Speed Electrical Test Differential Output Circuit

Rev. A | Page 4 of 20

05228-040

ADN2871

SFP TIMING SPECIFICATIONS

Table 2.

Parameter Symbol Min Typ Max Unit Conditions/Comments

ALS Assert Time t_off 1 5 μs

ALS Negate Time

1

t_on 0.15 0.4 ms

Time to Initialize, Including Reset of FAIL1t_init 25 275 ms From power-on or negation of FAIL using ALS
FAIL Assert Time t_fault 100 μs Time to fault to FAIL on
ALS to Reset Time t_reset 5 μs Time Tx_DISABLE must be held high to reset Tx_FAULT.

1

Guaranteed by design and characterization. Not production tested.

V

SE

DATAP

DATAN

Time for the rising edge of ALS (Tx_DISABLE) to when
the bias current falls below 10% of nominal

Time for the falling edge of ALS to when the modulation
current rises above 90% of nominal

DATAP–DATAN

0V

V p-p

DIFF

= 2× V

SE

05228-003

Figure 4. Signal Level Definition

SFP MODULE

VCC_Tx

Figure 5. Recommended SFP Supply

1μH

0.1μF 0.1μF 10μF

SFP HOST BOARD

3.3V

05228-004

Rev. A | Page 5 of 20

ADN2871

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VCC to GND 4.2 V
IMODN, IMODP −0.3 V to +4.8 V
All Other Pins −0.3 V to +3.9 V
Junction Temperature 150°C
Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range –65°C to +150°C

Junction Temperature (TJ max) 125°C
LFCSP

Power Dissipation

θJA Thermal Impedance

1

2

(TJ max − TA)/θJA W

30°C/W
θJC Thermal Impedance 29.5°C/W
Lead Temperature (Soldering 10 sec) 300°C

1

Power consumption equations are provided in the Power Consumption

section.

2

θ

is defined when part is soldered on a 4-layer board.

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 20