Analog Devices ADN2860 a Datasheet

3-Channel Digital Potentiometer with

FEATURES

3 channels:

Dual 512-position

Single 128-position
25 kΩ or 250 kΩ full-scale resistance
Low temperature coefficient:

Potentiometer divider 15 ppm/°C

Rheostat mode 35 ppm/°C
Nonvolatile memory retains wiper settings
Permanent memory write protection
Linear increment/decrement
±6 dB increment/decrement

2

C-compatible serial interface

I

2.7 V to 5.5 V single-supply operation
±2.25 V to ±2.75 V dual-supply operation
Power-on reset time
256 bytes general-purpose user EEPROM
11 bytes RDAC user EEPROM
GBIC and SFP compliant EEPROM
100-year typical data retention at T

APPLICATIONS

Laser diode drivers
Optical amplifiers
TIA gain setting
TEC controller temperature setpoint

GENERAL DESCRIPTION

The ADN2860 provides dual 512-position and single
128-position, digitally controlled variable resistors
single 4 mm × 4 mm LFCSP package. This device performs the
same electronic adjustment function as a potentiometer,
trimmer, or variable resistor. Each VR offers a completely
programmable value of resistance between the A terminal and
the wiper, or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 25 kΩ or 250 kΩ has a 1% channel-to­channel matching tolerance and a nominal temperature
coefficient of 35 ppm/°C.

Wiper position programming, EEPROM
writing are conducted via the standard 2-wire I
vious default wiper position settings can be stored in memory,
and refreshed upon system power-up.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

= 55°C

A

1

(VR) in a

2

reading, and EEPROM

2

C interface. Pre-

Nonvolatile Memory

ADN2860

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

SS

DGND

SCL
SDA
AD0

AD1
A0_EE
A1_EE

RESET

WP

2

I

C

SERIAL

INTERFACE

POWER-ON

RESET

Additional features of the ADN2860 include preprogrammed
linear and logarithmic increment/decrement wiper changing.
The actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.

The ADN2860 EEPROM, channel resolution, and package size
conform to GBIC and SFP specifications. The ADN2860 is
available in a 4 mm × 4 mm, 24-lead LFCSP package. All parts
are guaranteed to operate over the extended industrial tempera­ture range −40°C to +85°C.

1

The terms programmable resistor, variable resistor, RDAC, and digital

potentiometer are used interchangeably.

2

The terms nonvolatile memory, EEMEM, and EEPROM are used

interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

256 BYTES

USER

EEPROM

32 BYTES

RDAC

EEPROM

DATA
CONTROL

COMMAND

DECODE

LOGIC

ADDRESS

DECODE

LOGIC

DECODE

LOGIC

Figure 1.

RDAC0

REGISTER

RDAC1

REGISTER

RDAC2

REGISTER

RDAC0

9 BITS

RDAC1

9 BITS

RDAC2

7 BITS

A0

A0

A0
W0

W0

W0
B0

B0

B0

A1

A1

A1
W1

W1

W1
B1

B1

B1

A2

A2

A2
W2

W2

W2
B2

B2

B2

03615-001

ADN2860

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Digital Input/Output Configuration........................................ 16

Electrical Characteristics ................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Interface Descriptions.................................................................... 10

2

I

C Interface ................................................................................ 10

EEPROM Interface..................................................................... 11

RDAC I

Theory of Operation ...................................................................... 15

Linear Increment and Decrement Commands ...................... 15

Logarithmic Taper Mode Adjustment (±6 dB/step).............. 15

Using Additional Internal Nonvolatile EEPROM.................. 16

2

C Interface.................................................................... 12

REVISION HISTORY

Multiple Devices on One Bus ................................................... 16

Level Shift for Bidirectional Communication........................ 16

Terminal Voltage Operation Range ......................................... 16

Power-Up Sequence................................................................... 17

Layout and Power Supply Biasing............................................ 17

RDAC Structure.......................................................................... 17

Calculating the Programmable Resistance ............................. 17

Programming the Potentiometer Divider............................... 18

Applications..................................................................................... 19

Laser Diode Driver (LDD) Calibration................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

11/04—Rev. 0 to Rev. A

Changes to Ordering Guide.......................................................... 20

7/04—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADN2860

ELECTRICAL CHARACTERISTICS

Single supply: VDD = 2.7 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted.
Dual supply: V

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS,
RHEOSTAT MODE

Resistor Differential Nonlinearity2

Resistor Integral Nonlinearity2

Resistance Temperature Coefficent
Wiper Resistance RW V

Channel Resistance Matching ∆R
Nominal Resistor Tolerance ∆RAB/RAB Dx = 0x3FF −15

DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE

Differential Nonlinearity3

Integral Nonlinearity3

Voltage Divider Temperature
Coefficent

Full-Scale Error V

Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range4 V
Capacitance5 Ax, Bx C

Capacitance5 Wx CW

Common-Mode Leakage Current

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V

Input Logic Low VIL V

Output Logic High (SDA) VOH

Output Logic Low VOL

WP Leakage Current
A0 Leakage Current IA0 A0 = GND

= +2.25 V or +2.75 V, VSS = −2.25 V or −2.75 V, and −40°C < TA < +85°C, unless otherwise noted.

DD

R-DNL RWB, 7-bit channel −0.75

RWB, 9-bit channels −2.5

R-INL RWB, 7-bit channel −0.5
R-INL RWB, 9-bit channels, VDD = 5.5 V −2.0
R-INL RWB, 9-bit channels, VDD = 2.7 V −4.0

(∆RWB/RWB)/∆T × 106

/∆R

AB1

Ch 1 and Ch 2 RWB, Dx = 0x1FF

AB2

= 5 V, IW = 1 V/RWB

DD

VDD = 3 V, IW = 1 V/RWB

35
100 150 Ω
250 400 Ω

0.1

DNL 7-bit channel −0.5 +0.5 LSB
DNL 9-bit channels −2.0

INL 7-bit channel −0.5 +0.5 LSB
INL 9-bit channels −2.0 +2.0 LSB

)/∆T × 106 Code = half scale

(∆V

W/VW

WFSE

7-bit channel/9-bit channels,

15

−1/−2.75 0/0 LSB

code = full scale

WZSE

7-bit channel/9-bit channels,

0/0

code = zero scale

A, B, W

A,B

f = 1 kHz, measured to GND,

VSS

85

code = half scale
f = 1 kHz, measured to GND,

95

code = half scale

5, 6

ICM V

= VDD/2

W

= 5 V, VSS = 0 V 2.4

DD

VDD/VSS = +2.7 V/0 V or
V

= ±2.5 V

DD/VSS

= 5 V, VSS = 0 V

DD

VDD/VSS = +2.7 V/0 V or

= ±2.5 V

V

DD/VSS

= 2.2 kΩ to VDD = 5 V,

R

PULL-UP

= 0 V

V

SS

= 2.2 kΩ to VDD = 5 V,

R

PULL-UP

V

= 0 V

SS

I

WP

WP

= VDD

2.1

4.9

0.01 1 µA

+0.75 LSB
+2.5 LSB

+0.5 LSB
+2.0 LSB
+4.0 LSB

ppm/°C

%

+15 %

+2.0 LSB

ppm/°C

1/2.0 LSB

VDD V

pF

pF

V
V

0.8 V

0.6 V

V

0.4 V

9 µA
3 µA

Rev. A | Page 3 of 20

ADN2860

A

Parameter Symbol Conditions Min Typ1 Max Unit

Input Leakage Current (Excluding WP

II V

= 0 V or VDD

IN

and A0)

Input Capacitance5 C

I

POWER SUPPLIES

Single-Supply Power Range VDD V

Dual-Supply Power Range VDD/VSS

Positive Supply Current IDD V

Negative Supply Current ISS

EEMEM Data Storing Mode Current I

EEMEM Data Restoring Mode Current I

Power Dissipation7 P

Power Supply Sensitivity5 P

V

DD_STORE

DD_RESTORE

V

V

DISS

∆VDD = 5 V ± 10%

SS

= 0 V 2.7

SS

= VDD or VIL = GND, VSS = 0 V

IH

= VDD or VIL = GND, VDD =

V

IH

2.5 V, V

= −2.5 V

SS

= VDD or VIL = GND

IH

= VDD or VIL = GND

IH

= VDD = 5 V or VIL = GND

IH

1

Typical represents average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

5

±2.25

5 15 µA

−5 −15 µA

35

2.5
25 75 µW

0.01 0.025 %/%

±1 µA

pF

5.5 V
±2.75 V

mA
mA

t

8

SD

SCL

t

1

t

8

t

2

t

PS SP

3

Figure 2. I

t

9

t

4

2

C Timing Diagram

t

5

t

6

t

7

t

10

03615-015

Rev. A | Page 4 of 20

ADN2860

ELECTRICAL CHARACTERISTICS

Single Supply: VDD = 3 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted.
Dual Supply: V

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ.
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Spectral Density e
Digital Crosstalk CT

Analog Crosstalk CAT

INTERFACE TIMING CHARACTERISTICS (Apply
to All Parts)

SCL Clock Frequency f
t

Bus Free Time between Stop and Start t1

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3

LOW

t

High Period of SCL Clock t4

HIGH

t

Setup Time for Start Condition t5

SU;STA

t

Data Hold Time t6

HD;DAT

t

Data Setup Time t7

SU;DAT

tR Rise Time of Both SDA and SCL Signals t8
tF Fall Time of Both SDA and SCL Signals t9
t

Setup Time for Stop Condition t10

SU;STO

EEMEM Data Storing Time t
EEMEM Data Restoring Time at Power-On t
EEMEM Data Restoring Time on Restore t
Command or Reset Operation
EEMEM Data Rewritable Time t

FLASH/EE MEMORY RELIABILITY

Endurance6
Data Retention7 55°C.

1

Typical represents average readings at 25°C, VDD = 5 V.

2

All dynamic characteristics use VDD = 5 V.

3

Guaranteed by design and not subject to production test.

4

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

5

See Figure 2 for the location of measured values.

6

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles.

7

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature.

= +2.25 V or +2.75 V, VSS = −2.25 V or −2.75 V, and −40°C < TA < +85°C, unless otherwise noted.

DD

2, 3

= 1 V rms, VB = 0 V, f = 1 kHz.

A

= VDD, VB = 0 V,

V

A

V

= 0.50% error band,

W

code = 0x000 to 0x100, RAB = 25 kΩ/250 kΩ.

R

N_WB

= 25 kΩ/250 kΩ, TA = 25°C.

AB

= VDD, VB = 0 V, measure VW with

V

A

adjacent RDAC making full-scale
change.

Signal input at A0 and measure output
at W1, f = 1 kHz.

4, 5

SCL

After this period, the first clock pulse is
generated.

EEMEM_STORE

EEMEM_RESTORE1

EEMEM_RESTORE2

EEMEM_REWRITE

125/12 kHz

0.05 %
4/36 µs

14/45 nV√Hz

−80 dB

−72 dB

400 kHz

1.3 µs
600 ns

1.3 µs

0.6 50 µs
600 ns
900 ns
100 ns
300 ns
300 ns
600 ns
26 ms
360 µs
360 µs

540 µs

100

kcycles

100 years

Rev. A | Page 5 of 20

ADN2860

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
IA, IB, IW

Intermittent1 ±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C
Thermal Resistance Junction-to-Ambient

,

θ

JA

LFCSP-24 32°C/W

1

Includes programming of nonvolatile memory.

2

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20