ANALOG DEVICES ADN2855 Service Manual

Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps

Burst Mode Clock and Data Recovery IC with Deserializer

FEATURES

Serial data input

155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps
12-bit acquisition time
4-bit parallel LVDS output interface
Patented dual-loop clock recovery architecture
Integrated PRBS generator
Byte rate reference clock
Loss-of-lock indicator
Supports double data rate (DDR)-compatible FPGA

2

I

C interface to access optional features
Single-supply operation: 3.3 V
Power

670 mW typical in serial output mode
825 mW typical in deserializer mode

5 mm × 5 mm, 32-lead LFCSP

APPLICATIONS

Passive optical networks
GPON/BPON/GEPON OLT receivers

ADN2855

GENERAL DESCRIPTION

The ADN2855 is a burst mode clock and data recovery IC
designed for GPON/BPON/GEPON optical line terminal (OLT)
receiver applications. The part can operate at 155.52 Mbps,

622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable
via the I

The ADN2855 frequency locks to the OLT reference clock and
aligns to the input data within 12 bits of the start of the preamble.
The device provides a full rate or an optional half rate output
clock for a double data rate (DDR) interface to an FPGA or
digital ASIC.

All specifications are quoted for −40°C to +85°C ambient tempera­ture, unless otherwise noted. The ADN2855 is available in a
compact 5 mm × 5 mm, 32-lead chip scale package.

2

C interface.

RESET

PIN

NIN

ADN2855

CML INPUT

BUFFER

FUNCTIONAL BLOCK DIAGRAM

REFCLKP,
REFCLKN

DESERIALIZER

PHASE

SHIFTER

DATA

RE-TIMING

2

4 × 2

DATxP,
DATxN

DATAV

FREQUENCY/

LOCK

DETECT

PHASE

DETECT

CLKOUTP,
CLKOUTN

Figure 1.

CF1 CF2

LOOP

FILTER

LOOP

FILTER

DIVIDER

2

VCC VEE

VCO

I2C

SDA
SCK

SQUELCH

06660-001

Rev. 0

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