Datasheet ADN2850 Datasheet (Analog Devices)

Nonvolatile Memory, Dual

ADDR

DECODE

ADN2850

RDAC1

SERIAL

INTERFACE

CS

CLK

SDI

SDO

PR

WP

RDY

V

DD

V

SS

GND

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

26 BYTES

USER EEMEM

PWR ON
PRESET

EEMEM

CONTROL

W1

B1

RDAC2

W2

B2

CURRENT

MONITOR

I

1

I

2

V

1

V

2

CODE – Decimal

100

75

0

0 1023256

R

WB

(D) – % of Full-Scale R

WB

512 768

50

25

a

1024-Position Programmable Resistors

FEATURES
Dual, 1024-Position Resolution
25 k, 250 k Full-Scale Resistance
Low Temperature Coefficient: 35 ppm/C
Nonvolatile Memory

1

Preset Maintains Wiper Settings
Permanent Memory Write-Protection
Wiper Settings Read Back
Actual Tolerance Stored in EEMEM

1

Linear Increment/Decrement
Log Taper Increment/Decrement
SPI Compatible Serial Interface
3 V to 5 V Single Supply or 2.5 V Dual Supply
26 Bytes User Nonvolatile Memory for Constant Storage
Current Monitoring Configurable Function
100-Year Typical Data Retention T

= 55C

A

APPLICATIONS
SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser

Diode Driver Optical Supervisory Systems

GENERAL DESCRIPTION

The ADN2850 provides dual-channel, digitally controlled program­mable resistors

2

with resolution of 1024 positions. These devices
perform the same electronic adjustment function as a mechanical
rheostat with enhanced resolution, solid-state reliability, and
superior low temperature coefficient performance. The ADN2850’s
versatile programming via a standard serial interface allows
16 modes of operation and adjustment, including scratch pad pro­gramming, memory storing and retrieving, increment/decrement,
log taper adjustment, wiper setting readback, and extra user
defined EEMEM

1

.

Another key feature of the ADN2850 is that the actual tolerance
is stored in the EEMEM. The actual full-scale resistance can
therefore be known, which is valuable for tolerance matching
and calibration.

In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC

2

register, which sets the resis­tance between terminals W and B. The RDAC register can also
be loaded with a value previously stored in the EEMEM register.
The value in the EEMEM can be changed or protected. When
changes are made to the RDAC register, the value of the new
setting can be saved into the EEMEM. Thereafter, such value will
be transferred automatically to the RDAC register during system
power ON, which is enabled by the internal preset strobe.
EEMEM can also be retrieved through direct programming and
external preset pin control.

*Patent pending

NOTES

1

The term nonvolatile memory and EEMEM are used interchangeably.

2

The term programmable resistor and RDAC are used interchangeably.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

ADN2850

*

FUNCTIONAL BLOCK DIAGRAM

Figure 1. RWB(D) vs. Decimal Code

The linear step increment and decrement commands enable the
setting in the RDAC register to be moved UP or DOWN, one step
at a time. For logarithmic changes in wiper setting, a left/right
bit shift command adjusts the level in ±6 dB steps.

The ADN2850 is available in the 5 mm  5 mm 16-lead frame chip
scale LFCSP and thin 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADN2850–SPECIFICATIONS

(VDD = 3 V to 5.5 V and –40C < TA < +85C,

ELECTRICAL CHARACTERISTICS 25 k, 250 k VERSIONS

unless otherwise noted.)

1

Parameter Symbol Conditions Min Typ2Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs)

Resistor Differential Nonlinearity3R-DNL R
Resistor Integral Nonlinearity
Resistance Temperature Coefficient R
Wiper Resistance R

3

R-INL R

WB/T

W

WB

WB

VDD = 5 V, IW = 100 µA,

–2 +2 LSB
–4 +4 LSB

35 ppm/°C

Code = Half-scale 50 100 Ω

= 3 V, IW = 100 µA,

V

DD

Code = Half-scale 200 Ω

Channel Resistance Matching R
Nominal Resistor Tolerance R

RESISTOR TERMINALS

Terminal Voltage Range

4

Capacitance5 Bx C

5

Capacitance

Wx C

V

W, B

B

W

WB/RWB

WB

Ch 1 and 2 RWB, Dx = 3FF

H

–30 +30 %

V
f = 1 MHz, measured to GND,
Code = Half-scale 11 pF
f = 1 MHz, measured to GND,

0.1 %

SS

V

DD

V

Code = Half-scale 80 pF

Common-Mode Leakage Current6I

CM

VW = VB = VDD/2 0.01 ±2 µA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Logic High V

Input Logic Low V

Output Logic High (SDO, RDY) V
Output Logic Low V
Input Current I
Input Capacitance

5

IH

IL

IH

IL

IH

IL

OH

OL

IL

C

IL

With respect to GND, VDD = 5 V 2.4 V
With respect to GND, VDD = 5 V 0.8 V
With respect to GND, VDD = 3 V 2.1 V
With respect to GND, VDD = 3 V 0.6 V
With respect to GND,
V

= +2.5 V, V

DD

= –2.5 V 2.0 V

SS

With respect to GND,

= +2.5 V, V

V

DD

R

= 2.2 kΩ to 5 V 4.9 V

PULL-UP

IOL = 1.6 mA, V
VIN = 0 V or V

= –2.5 V 0.5 V

SS

= 5 V 0.4 V

LOGIC

DD

±2.25 µA

5pF

POWER SUPPLIES

Single-Supply Power Range V
Dual-Supply Power Range V
Positive Supply Current I

Positive Supply Current I
Programming Mode Current I
Read Mode Current

7

Negative Supply Current I

Power Dissipation

8

Power Supply Sensitivity P

CURRENT MONITOR TERMINALS

Current Sink at V
Current Sink at V

DYNAMIC CHARACTERISTICS

9

1

2

5, 10

Resistor Noise Spectral Density e
Analog Crosstalk (C

)CTVB1 = VB2 = 0 V, Measured VW1 with

W1/CW2

DD

DD/VSS

DD

DD

DD(PG)

I

DD(XFR)

SS

P

DISS

SS

I

1

I

2

N_WB

VSS = 0 V 3.0 5.5 V

±2.25 ± 2.75 V
VIH = VDD or VIL = GND,

= 25oC24.5 µA

T

A

VIH = VDD or VIL = GND 3.5 6.0 µA
VIH = VDD or VIL = GND 35 mA
VIH = VDD or VIL = GND 0.3 3 9 mA
VIH = VDD or VIL = GND,

= +2.5 V, V

V

DD

= –2.5 V 3.5 6.0 µA

SS

VIH = VDD or VIL = GND 18 50 µW
∆VDD = 5 V ± 10% 0.002 0.01 %/%

0.0001 10 mA
10 mA

R

= 25 kΩ/250 kΩ, f = 1 kHz 20/64 nV/√Hz

WB_FS

= 100 mV p-p @ f = 100 kHz,

V

W2

Code 1 = Code 2 = 200

H

–65 dB

REV. B–2–

ADN2850

Parameter Symbol Conditions Min Typ2Max Unit

INTERFACE TIMING CHARACTERISTICS (apply to all parts)

Clock Cycle Time (t
CS Setup Time t
CLK Shutdown Time to CS Rise t
Input Clock Pulsewidth t4 , t
Data Setup Time t
Data Hold Time t

CS to SDO – SPI Line Acquire t
CS to SDO – SPI Line Release t

CLK to SDO Propagation Delay

CS High Pulsewidth
CS High to CS High
RDY Rise to CS Fall t
CS Rise to RDY Fall Time t

Read/Store to Nonvolatile EEMEM
CS Rise to Clock Edge Setup t
Preset Pulsewidth (Asynchronous) t
Preset Response Time to Wiper Setting t

)t

CYC

12

13

13

1

2

3

5

6

7

8

9

t

10

t

12

t

13

14

15

14

t

16

17

PRW

PRESP

Clock Level High or Low 10 ns
From Positive CLK Transition 5 ns
From Positive CLK Transition 5 ns

RP = 2.2 kΩ, CL < 20 pF 50 ns

Applies to Command 2H, 3H, 9

Not Shown in Timing Diagram 50 ns
PR Pulsed Low to Refresh 140 µs
Wiper Positions

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

NOTES

1

Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.

2

Typicals represent average readings at 258C and VDD = 5 V.

3

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for V

4

Resistor terminals W and B have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V

7

Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.

8

P

DISS

9Applies to photodiode of optical receiver.

10

All dynamic characteristics use VDD = +2.5 V and V

11

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using both VDD = 3 V and 5 V.

12

Propagation delay depends on value of VDD, R

13

Valid for commands that do not activate the RDY pin.

14

RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA= –40°C
and VDD < 3 V extends the save time to 35 ms.

15

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

16

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will
derate with junction temperature.

Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil  103 mil, 10,197 sq mil.

15

16

is calculated from (IDD  VDD) + (ISS  VSS).

PULL_UP

= –2.5 V.

SS

, and CL. See Applications section.

5, 11

20 ns
10 ns
1t

10 ns
4t
0ns

0.15 0.3 ms

H

35 ms

10 ns

100 K Cycles

100 Years

= 2.7 V and IW ~ 400 µA for V

DD

/2.

DD

40 ns
50 ns

= 5 V.

DD

CYC

CYC

REV. B

–3–

ADN2850

TIMING DIAGRAMS

CS

CLK

CPOL = 1

SDO

SDI

RDY

CPHA = 1

t

t

LSB

3

t

9

t

15

t

t

2

t

8

*

t

14

*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

5

t

4

t

10

MSB LSB OUT

t

7

t

6

MSB

t

11

Figure 2a. CPHA = 1 Timing Diagram

12

t

13

t

17

t

16

CS

CLK

CPOL = 0

SDO

SDI

RDY

CPHA = 0

t

12

t

1

t

2

t

8

MSB OUT LSB

MSB IN

t

14

*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

t

5

t

4

t

10

t

7

t

6

LSB

t

3

t

17

t

11

t

9

*

t

15

Figure 2b. CPHA = 0 Timing Diagram

t

13

t

16

REV. B–4–

ADN2850

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V

V

SS

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

, VW to GND . . . . . . . . . . . . . . . . V

V

B

, I

I

B

W

Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 mA

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA

Digital Inputs and Output Voltage

to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

Operating Temperature Range3 . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering

4

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C

1

– 0.3 V, V

SS

) . . . . . . . . . 150°C

J MAX

+ 0.3 V

DD

+ 0.3 V

DD

Thermal Resistance Junction-to-Ambient θ

JA,

LFCSP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

Thermal Resistance Junction-to-Case θ

JC,

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W

Package Power Dissipation = (T

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the B and W terminals at a given resistance.

3

Includes programming of nonvolatile memory.

4

Applicable to TSSOP-16 only. For LFCSP-16, please consult factory for details.

J MAX

– TA)/θ

JA

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C

ORDERING GUIDE

R

WB_FS

RDNL RINL Temperature Package Package Ordering

Model (k) (LSB) (LSB) Range (°C) Description Option Quantity Top Mark*

ADN2850BCP25 25 ± 2 ±4 –40 to +85 LFCSP-16 CP-16 96 BCP25
ADN2850BCP25-RL7 25 ± 2 ±4 –40 to +85 LFCSP-16 CP-16 1,000 BCP25

7" Reel

ADN2850BCP250 250 ±2 ± 4 –40 to +85 LFCSP-16 CP-16 96 BCP250
ADN2850BCP250-RL7 250 ±2 ±4 –40 to +85 LFCSP-16 CP-16 1,000 BCP250

7" Reel

ADN2850BRU25 25 ± 2 ±4 –40 to +85 TSSOP-16 RU-16 96 2850B25
ADN2850BRU25-RL7 25 ± 2 ±4 –40 to +85 TSSOP-16 RU-16 1,000 2850B25

7" Reel

*Line 1 contains product number, ADN2850, line 2 Top Mark branding contains differentiating detail by part type, line 3 contains lot number, line 4 contains product

date code YYWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADN2850 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

WARNING!

ESD SENSITIVE DEVICE

ADN2850

TOP VIEW

(Not To Scale)

1

2

3

4

5

6

7

8

SDI

SDO

GND

V

1

V

SS

W1

ADN2850BRU

CLK

B1

16

15

14

13

12

11

10

9

CS

PR

WP

V

DD

V

2

W2

B2

RDY

SDO

GND

V

1

2

3

SS

4

V

1

CS

RDY

CLK

SDI

16

15 14 13

ADN2850BCP

CHIP SCALE

PACKAGE

8765

B2

B1

W1

W2

PIN CONFIGURATIONS

12

PR

11

WP

10

V

DD

9

V

2

ADN2850BCP PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1SDO Serial Data Output Pin. Open-Drain output

requires external pull-up resistor. CMD_9 and
CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of

multiple packages.
2GND Ground Pin, logic ground reference
3V

SS

Negative Supply. Connect to zero volts for

single-supply applications.
4V

1

Log Output Voltage 1 generated from internal

diode configured transistor
5W1Wiper terminal of RDAC1 ADDR

(RDAC1) = 0

.

H

6B1B terminal of RDAC1
7B2B terminal of RDAC2
8W2Wiper terminal of RDAC2. ADDR

9V

2

(RDAC2) = 1

Log Output Voltage 2 generated from internal

.

H

diode configured transistor
10 V

DD

Positive Power Supply Pin
11 WP Write Protect Pin. When active low, WP

prevents any changes to the present register

contents, except PR and CMD_1 and CMD_8

will refresh the RDAC register from EEMEM.

Execute a NOP instruction before returning

to WP high.
12 PR Hardware Override Preset Pin. Refreshes the

scratch pad register with current contents of

the EEMEM register. Factory default loads

midscale 51210 until EEMEM loaded with

a new value by the user (PR is activated at

the logic high transition).
13 CS Serial Register chip select active low.

Serial register operation takes place when

CS returns to logic high.
14 RDY Ready. Active high open-drain output. Identifies

completion of commands 2, 3, 8, 9, 10, and PR.
15 CLK Serial Input Register Clock Pin. Shifts in

16 SDI Serial Data Input Pin. Shifts in one bit at a time

one bit at a time on positive clock edges.

on positive clock CLK edges. MSB loaded first.

ADN2850BRU PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1 CLK Serial Input Register Clock Pin. Shifts in

one bit at a time on positive clock edges.

2 SDI Serial Data Input Pin. Shifts in one bit at

a time on positive clock CLK edges.
MSB loaded first.

3SDO Serial Data Output Pin. Open-drain out put

requires external pull-up resistor. CMD_9
and CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of

multiple packages.
4GND Ground Pin, logic ground reference
5V

SS

Negative Supply. Connect to zero volts for

single-supply applications.
6V

1

Log Output Voltage 1 generated from internal

diode configured transistor
7W1Wiper terminal of RDAC1. ADDR

(RDAC1) = 0

.

H

8B1B terminal of RDAC1
9B2B terminal of RDAC2
10 W2 Wiper terminal of RDAC2. ADDR

11 V

(RDAC2) = 1

2

Log Output Voltage 2 generated from internal

.

H

diode configured transistor
12 V

DD

Positive Power Supply Pin
13 WP Write Protect Pin. When active low, WP prevents

any changes to the present contents except PR

and CMD_1 and CMD_8 will refresh the

RDAC register from EEMEM. Execute a NOP

instruction before returning to WP high.
14 PR Hardware Override Preset Pin. Refreshes the

scratch pad register with current contents of

the EEMEM register. Factory default loads

midscale 512

until EEMEM loaded with a

10

new value by the user (PR is activated at the

logic high transition).
15 CS Serial Register chip select active low. Serial

register operation takes place when CS returns

to logic high.
16 RDY Ready. Active high open-drain output. Identifies

completion of commands 2, 3, 8, 9, 10, and PR.

REV. B–6–

ADN2850

Table I. 24-Bit Serial Data-Word

MSB Instruction Byte 0 Data Byte 1 Data Byte 0 LSB

RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Command bits are C0 to C3. Address bits are A3–A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM
Register. Command instruction codes are defined in Table II.

Table II. Instruction Operation Truth Table

1, 2, 3

Inst Instruction Byte 0 Data Byte 1 Data Byte 0 Operation
Number B23 • • • • • • • • • • • • • • • • B16 B15 • • • • • • B8 B7 • • • • • B0

C3 C2 C1 C0 A3 A2 A1 A0 X • • • • D9 D8 D7 • • • • • D0

00000XXX XX • • • • X XX • • • • • • X NOP: Do nothing. See Table XI for Programming

example.

10001000 A0 X • • • • X X X • • • • • • X Retrieve contents of EEMEM(A0) to RDAC(A0)

Register. This command leaves device in the Read
Program power state. To return part to the idle state,
perform NOP instruction 0. See Table XI.

20010000 A0 X • • • • X XX • • • • • • X SAVE WIPER SETTING: Write contents of RDAC(A0)

to EEMEM(A0). See Table X.

4

3

0011A3 A2 A1 A0 D15 • • • • D8 D7 • • • • • D0 Write contents of Serial Register Data Bytes 0 and

1 (total 16-bit) to EEMEM(ADDR). See Table XIII.

5

4

0100000 A0 X • • • • X XX • • • • • • X Decrement 6 dB: Right shift contents of RDAC(A0)

Register, stops at all “Zeros.”

5

5

0101XXX XX • • • • X XX • • • • • • X Decrement All 6 dB: Right shift contents of all RDAC

Registers, stops at all “Zeros.”

5

6

0110000 A0 X • • • • X X X • • • • • • X Decrement contents of RDAC(A0) by “One,” stops

at all “Zeros.”

5

7

0111XXX XX • • • • X X X • • • • • • X Decrement contents of all RDAC Registers by

“One,” stops at all “Zeros.”

81000XXX XX • • • • X X X • • • • • • X RESET: Load all RDACs with their corresponding

EEMEM previously saved values.

91001A3A2A1A0X • • • • X XX • • • • • • X Transfer contents of EEMEM (ADDR) to Serial

Register Data Bytes 0 and 1, and previously stored
data can be read out from the SDO pin. See Table XIV.

10 1 0 1 0 0 0 0 A0 X • • • • X X X • • • • • • X Transfer contents of RDAC (A0) to Serial Register

Data Bytes 0 and 1, and wiper setting can be read
from the SDO pin. See Table XV.

11 1 0 1 1 0 0 0 A0 X • • • • D9 D8 D7 • • • • • D0 Write contents of Serial Register Data Bytes 0 and

1 (total 11-bit) to RDAC(A0). See Table IX.

12

5

1100000 A0 X • • • • X X X • • • • • • X Increment 6 dB: Left shift contents of RDAC(A0),

stops at all “Ones.” See Table XII.

13

5

1101XXX XX • • • • X X X • • • • • • X Increment All 6 dB: Left shift contents of all RDAC

Registers, stops at all “Ones.”

14

5

1110000 A0 X • • • • X X X • • • • • • X Increment contents of RDAC(A0) by “One,” stops

at all “Ones.” See Table X.

15

5

1111XXX XX • • • • X X X • • • • • • X Increment contents of all RDAC Registers by “One,”

stops at all “Ones.”

NOTES

1

The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10,

the selected internal register data will be present in data byte 0 and 1. The instructions following 9 and 10 must also be a full 24-bit data-word to completely clock out
the contents of the serial register.

2

The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register.

3

Execution of the above operations takes place when the CS strobe returns to logic high.

4

Instruction 3 writes 2 data bytes (total 16-bit) to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting.

5

The increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1.

REV. B

–7–

ADN2850

OPERATIONAL OVERVIEW

The ADN2850 programmable resistor is designed to operate as
a true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratch pad register which allows unlimited changes of resistance
settings. The scratch pad register can be programmed with any
position setting using the standard SPI serial interface by loading
the 24-bit data-word. The format of the data-word is that the first
4 bits are instructions, the following 4 bits are addresses, and the
last 16 bits are data. Once a specific value is set, this value can be
saved into a corresponding EEMEM register. During subsequent
power-ups, the wiper setting will automatically be loaded at that
value. Saving data to the EEMEM takes about 25 ms and con­sumes approximately 20 mA. During this time the shift register
is locked, preventing any changes from taking place. The RDY pin
indicates the completion of this EEMEM saving process. There
are also 13 two-bytes addresses, of user defined data that can be
stored in EEMEM.

OPERATION DETAIL

There are 16 instructions that facilitate users’ programming
needs. Referring to Table II, the instructions are:

0. Do Nothing

1. Restore EEMEM setting to RDAC

2. Save RDAC setting to EEMEM

3. Save user data or RDAC setting to EEMEM

4. Decrement 6 dB

5. Decrement all 6 dB

6. Decrement one step

7. Decrement all one step

8. Reset all EEMEM settings to RDAC

9. Read EEMEM to SDO

10. Read Wiper Setting to SDO

11. Write data to RDAC

12. Increment 6 dB

13. Increment all 6 dB

14. Increment one step

15. Increment all one step

Tables VIII to XIV provide a few programming examples by using
some of these instructions.

Scratch Pad and EEMEM Programming

The basic mode of setting the programmable resistor wiper position
(programming the scratch pad register) is done by loading the
serial data input register with the instruction 11, the corresponding
address, and the data. Since the scratch pad register is a standard
logic register, there is no restriction on the number of changes
allowed. When the desired wiper position is determined, the user can
load the serial data input register with the instruction 2, which stores
the setting into the corresponding EEMEM register. The EEMEM
value can be changed at any time or permanently protected by
activating the WP command. Table III provides a programming
example listing the sequence of serial data input (SDI) words and
the corresponding serial data output (SDO) in hexadecimal format.

Table III. Set and Save RDAC with Independent Data
to EEMEM Registers

SDI SDO Action

B00100

XXXXXXHLoads data 100H into RDAC1 register,

H

Wiper W1 moves to 1/4 full-scale
position.

20xxxx

H

B00100

Saves copy of RDAC1 register content

H

into corresponding EEMEM1 register.

B10200

H

20xxxx

Loads 200H data into RDAC2 register,

H

Wiper W2 moves to 1/2 full-scale
position.

21xxxx

H

B10200

Saves copy of RDAC2 register contents

H

into corresponding EEMEM2 register.

At system power ON, the scratch pad register is automatically
refreshed with the value previously saved in the corresponding
EEMEM register. The factory preset EEMEM value is midscale.
During operations, the scratch pad register can also be refreshed
with the current contents of the EEMEM registers in three different
ways. First, executing instruction 1 retrieves the corresponding
EEMEM value. Second, executing instruction 8 resets the EEMEM
values of both channels. Finally, pulsing the PR pin also refreshes
both EEMEM settings. Operating the hardware control PR
function, however, requires a complete pulse signal. When PR
goes low, the internal logic sets the wiper at midscale. The
EEMEM value will not be loaded until PR returns to high.

EEMEM Protection

The write-protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed and can overwrite the
WP by using commands 1, 8, and PR pulse. To disable WP, it is
recommended to execute a NOP command before returning
WP to logic high.

Linear Increment and Decrement Commands

The increment and decrement commands (14, 15, 6, 7) are useful
for linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
just send an increment or decrement command to the device. The
adjustment can be individually or gang controlled. For incre­ment command, executing instruction 14 will automatically move the
wiper to the next resistance segment position. The master increment
instruction 15 will move all resistor wipers up by one position.

Logarithmic Taper Mode Adjustment (6 dB/step)

There are four programming instructions which provide the
logarithmic taper increment and decrement wiper position con­trol by either individual or gang control. 6 dB increment is
activated by instructions 12 and 13 and 6 dB decrement is acti­vated by instructions 4 and 5. For example, starting at zero
scale, executing 11 times the increment instruction 12 will move
the wiper in 6 dB per step from the 0% of the full-scale R
the full-scale R

. The 6 dB increment instruction doubles the

WB

WB

to

value of the RDAC register contents each time the command is
executed. When the wiper position is near the maximum setting,
the last 6 dB increment instruction will cause the wiper to go to
the full-scale 1023-code position. Further 6 dB per increment
instruction will no longer change the wiper position beyond its
full-scale, Table IV.

6 dB step increment and decrement are achieved by shifting the bit
internally to the left and right, respectively. The following infor­mation explains the nonideal ±6dB step adjustment at certain

REV. B–8–

ADN2850

conditions. Table IV illustrates the operation of the shifting
function on the individual RDAC register data bits. Each line
going down the table represents a successive shift operation. Note
that the left shift 12 and 13 commands were modified such that
if the data in the RDAC register is equal to zero, and the data is
left shifted, the RDAC register is then set to code 1. Similarly, if the
data in the RDAC register is greater than or equal to midscale,
and the data is left shifted, then the data in the RDAC register is
automatically set to full scale. This makes the left shift function
as ideal a logarithmic adjustment as possible.

The right shift 4 and 5 commands will be ideal only if the LSB is
zero (i.e., ideal logarithmic—no error). If the LSB is a one, then
the right shift function generates a linear half LSB error, which
translates to a number of bits-dependent logarithmic error as
shown in Figure 3. The plot shows the error of the odd numbers
of bits for ADN2850.

Table IV. Detail Left and Right Shift Functions for 6 dB
Step Increment and Decrement

Left Shift Right Shift

00 0000 0000 11 1111 1111
00 0000 0001 01 1111 1111
00 0000 0010 00 1111 1111
00 0000 0100 00 0111 1111
00 0000 1000 00 0011 1111

Left Shift
6 dB/step

00 0001 0000 00 0001 1111
00 0010 0000 00 0000 1111

Right Shift
–6 dB/step

00 0100 0000 00 0000 0111
00 1000 0000 00 0000 0011
01 0000 0000 00 0000 0001
10 0000 0000 00 0000 0000
11 1111 1111 00 0000 0000
11 1111 1111 00 0000 0000

Actual conformance to a logarithmic curve between the data con­tents in the RDAC register and the wiper position for each right
shift 4 and 5 command execution contains an error only for odd
numbers of bits. Even numbers of bits are ideal. The graph in
Figure 3 shows plots of Log_Error [i.e., 20  log
ADN2850. For example, code 3 Log_Error = 20  log

(error/code)]

10

(0.5/3)

10

= –15.56 dB, which is the worst case. The plot of Log_Error is
more significant at the lower codes.

0

–20

–40

dB

Using Additional Internal Nonvolatile EEMEM

The ADN2850 contains additional internal user storage registers
(EEMEM) for saving constants and other 16-bit data. Table V
provides an address map of the internal storage registers shown
in the functional block diagram as EEMEM1, EEMEM2, and
and 26 bytes (13 addresses  2 bytes each) of USER EEMEM.

Table V. EEMEM Address Map

EEMEM
Number Address EEMEM Content For

1 0000 RDAC1
2 0001 RDAC2
3 0010 USER1

1, 2

3

4 0011 USER2
:: :
15 1110 USER13
16 1111 % Tolerance

NOTES

1

RDAC data stored in EEMEM locations are transferred to their corresponding
RDAC REGISTER at power-on, or when instructions 1, 8, and PR are executed.

2

Execution of instruction 1 leaves the device in the read mode power consumption
state. After the last instruction 1 is executed, the user should perform a NOP,
instruction 0 to return the device to the low power idling state.

3

USER <data> are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using instructions 3 and 9 respectively.

4

Read only.

4

Calculating Actual Full-Scale Resistance

The actual tolerance of the rated full-scale resistance R

WB1

is
stored in EEMEM register 15 during factory testing. The actual
full-scale resistance can therefore be calculated, which will be
valuable for tolerance matching or calibration. Notice this value
is read only, and the full-scale resistance of R
R

of typically 0.1%.

WB1_FS,

WB2_FS

matches

The tolerance in % is stored in the last 16 bits of data in EEMEM
register 15. The format is sign magnitude binary format with the
MSB designates for sign (0 = positive and 1 = negative), the next
7 MSB designate for the integer number, and the 8 LSB designate
for the decimal number. See Table VI.

Table VI. Tolerance in % from Rated Full-Scale Resistance

D8

D7

D6

D5

D4

D3

D2

D1

sign
mag

sign

Sign

For example, if R

5

6

2

2

2

{

{

7 Bits for Integer Number

4

2

WB_FS_RATED

D13

D11

D12

D14

Bit

D15

1100 0000 1111, R

D9

D10

3

0

1

2

2

2

2

Decimal

Point

= 250 kΩ and the data is 0001

WB_FS_ACTUAL

•

-1

-2

-3

-4

2

2

{

-5

2

2

2

{

8 Bits for Decimal Number

can be calculated as follows:

D0

-6

-7

-8

2

2

2

MSB: 0 = Positive
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15  2

–8 =

0.06

% Tolerance = +28.06%

Thus, R

WB_FS_ACTUAL

= 320.15 kΩ

–60

–80

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

CODE – From 1 to 1023 by 2.0  10

3

Figure 3. Plot of Log_Error Conformance for Odd
Numbers of Bits Only (Even Numbers of Bits Are Ideal)

REV. B

–9–

ADN2850

Daisy-Chain Operation

The serial data output pin (SDO) serves two purposes. It can be
used to read out the contents of the wiper settings or EEMEM
values using instructions 10 and 9 respectively. If these instruc­tions are not used, SDO can be used for daisy-chaining multiple
devices in simultaneous operations (see Figure 4). The SDO pin
contains an open-drain N-Ch FET and requires a pull-up resis­tor if SDO function is used. Users need to tie the SDO pin of
one package to the SDI pin of the next package. Users may need
to increase the clock period because the pull-up resistor and the
capacitive loading at the SDO-SDI interface may induce time
delay to the subsequent devices (see Figure 4). If two ADN2850s
are daisy-chained, a total 48 bits of data is required. The first
24 bits (formatted 4-bit instruction, 4-bit address, and 16-bit
data) go to U2 and the second 24 bits with the same format go
to U1. The CS should be kept low until all 48 bits are clocked into
their respective serial registers. The CS is then pulled high to
complete the operation.

V

DD

SCLK

C

MOSI

SS

ADN2850

U1

SDI SDO

CLK

R

2.2k

P

SDI SDO

ADN2850

U2

CLKCS CS

PR WP

CLK

CS

SDI

VA LI D

COMMAND

COUNTER

COMMAND

PROCESSOR

AND ADDRESS

DECODE

SERIAL

REGISTER

ADN2850

5V

SDO

GND

R

PULLUP

Figure 5. Equivalent Digital Input-Output Logic

V

DD

INPUTS

LOGIC

PINS

300

GND

Figure 6a. Equivalent ESD Digital Input Protection

Figure 4. Daisy-Chain Configuration

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected. Digital inputs are high
impedance and can be driven directly from most digital sources.
Active at logic low, PR and WP should be biased to V

if they

DD

are not used. There are no internal pull-up resistors present on
any digital input pins. To avoid floating digital pins that may
cause false triggering in a noisy environment, pull-up resistors
should be added to these pins. However, this only applies to the
case where the device will be detached from the driving source
once it is programmed.

The SDO and RDY pins are open-drain digital outputs. Similarly,
pull-up resistors are needed if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.

The equivalent serial data input and output logic is shown in
Figure 5. The open-drain output SDO is disabled whenever
chip select CS is logic high. ESD protection of the digital inputs
is shown in Figures 6a and 6b.

V

DD

INPUT

WP

300

GND

Figure 6b. Equivalent WP Input Protection

SERIAL DATA INTERFACE

The ADN2850 contains a 4-wire, SPI compatible, digital inter­face (SDI, SDO, CS, and CLK). The 24-bit serial word must be
loaded with MSB first, and the format of the word is shown in
Table I. The Command Bits (C0 to C3) control the operation of
the programmable resistor according to the instruction shown
in Table II. A0 to A3 are assigned for address bits. A0 is used to
address RDAC1 or RDAC2. Addresses 2 to 14 are accessible by
users. Address 15 is reserved for the factory. Table V provides an
address map of the EEMEM locations. The data bits (D0 to D9) are
the values that are loaded into the RDAC registers at instruc­tion 11. The data bits (D0 to D15) are the values that are loaded
into the EEMEM registers at instruction 3.

The last instruction prior to a period of no programming activity
should be applied with the No Operation (NOP), instruction 0. It
is recommended to do so to ensure minimum power consumption
in the internal logic circuitry

The SPI interface can be used in two slave modes, CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in these microconverters
and microprocessors: ADuC812/ADuC824, M68HC11,
and MC68HC16R1/916R1.

REV. B–10–

ADN2850

SW(1)

SW(0)

SWB

B

R

S

R

S

SW(2

N

–

1)

W

SW(2

N

–

2)

RDAC

WIPER

REGISTER

AND

DECODER

R

S = RWB

/2

N

R

S

DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY

TERMINAL VOLTAGE OPERATING RANGE

The ADN2850 positive VDD and negative VSS power supply
defines the boundary conditions for proper two-terminal program­mable resistance operation. Supply signals present on terminals W
and B that exceed V

or VSS will be clamped by the internal

DD

forward biased diodes (see Figure 7).

V

DD

W

B

V

SS

Figure 7. Maximum Terminal Voltages Set by VDD and V

The ground pin of the ADN2850 device is primarily used as a digital
ground reference that needs to be tied to the PCB’s common
ground. The digital input control signals to the ADN2850 must
be referenced to the device ground pin (GND), and satisfy the
logic level defined in the Specifications table of this data sheet.
An internal level shift circuit ensures that the common-mode
voltage range of the two terminals extends from V

SS

to V
regardless of the digital input level. In addition, there is no
polarity constraint on voltage across terminals W and B. The
magnitude of |V

| is bounded by V

WB

DD

– VSS.

Power-Up Sequence

Since diodes limit the voltage compliance at terminals B and W
(see Figure 7) it is important to power V

first before apply-

DD/VSS

ing any voltage to terminals B and W. Otherwise, the diode will be
forward biased such that V
For example, applying 5 V across V

will be powered unintentionally.

DD/VSS

will cause the VDD terminal

DD

to exhibit 4.3 V. Although it is not destructive to the device, it may
affect the rest of the user’s system. As a result, the ideal power-up
sequence is in the following order: GND, V
and V

. The order of powering VB, VW, and Digital Inputs is not

B/W

important as long as they are powered after V

, VSS, Digital Inputs,

DD

.

DD/VSS

Regardless of the power-up sequence and the ramp rates of the
power supplies, once V

are powered, the power-on reset

DD/VSS

remains effective, which retrieves EEMEM saved values to the
RDAC registers (see TPC 7).

Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos­sible with a minimum of conductor length. Ground paths should
have low resistance and low inductance. To minimize the digital
ground bounce, the digital signal ground reference can be joined
remotely to the analog ground terminal of the ADN2850.

Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µFto0.1 µF disc or chip
ceramics capacitors. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to minimize
any transient disturbance (see Figure 8).

REV. B

DD

ADN2850

V

DD

V

SS

10F

10F

+

C3

C1

0.1F

+

C4

C2

0.1F

V

DD

V

SS

GND

Figure 8. Power Supply Bypassing

RDAC STRUCTURE

The patent-pending RDAC contains a string of equal resistor
segments, with an array of analog switches, that act as the wiper
connection. The number of positions is the resolution of the
device. The ADN2850 has 1024 connection points, allowing it to
provide better than 0.1% setability resolution. Figure 9 shows an
equivalent structure of the connections between the two terminals
that make up one channel of the RDAC. The S
ON, while one of the switches SW(0) to SW(2

SS

one at a time depending on the resistance position decoded from

will always be

WB

N

– 1) will be ON

the data bits. Since the switch is not ideal, there is a 50 Ω wiper
resistance, R

. Wiper resistance is a function of supply voltage

W

and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if accurate
prediction of the output resistance is needed.

Figure 9. Equivalent RDAC Structure

Table VII. Nominal Individual Segment Resistor Values

Device Resolution 25 kΩ 250 kΩ
1024-Step 24.4 244

CALCULATING THE PROGRAMMABLE RESISTANCE

The nominal full-scale resistance of the RDAC between terminals
W and B, R

, is available with 25 kΩ and 250 kΩ with 1024

WB_FS

positions (10-bit resolution). The final digits of the part number
determine the nominal resistance value, e.g., 25 kΩ = 25 and
250 kΩ = 250.

The 10-bit data-word in the RDAC latch is decoded to select one
of the 1024 possible settings. The following discussion describes
the calculation of resistance R

(D) at different codes of a 25 kΩ

WB

part. The wiper’s first connection starts at the B terminal for
data 000

. RWB(0) is 50 Ω because of the wiper resistance and it

H

is independent of the full-scale resistance. The second connection
is the first tap point where R

(1) becomes 24.4 Ω + 50 = 74.4 Ω

WB

–11–

ADN2850

for data 001H. The third connection is the next tap point represent­ing R

(2) = 48.8 + 50 = 98.8 Ω for data 002H and so on. Each

WB

LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at R

(1023) = 25026 Ω. See

WB

Figure 9 for a simplified diagram of the equivalent RDAC circuit.

25

20

15

(D) – k

WB

10

R

R

WB_FS

5

0

0 1023256

= 25k

512 768

CODE – Decimal

Figure 10. RWB(D) vs. Code

The general equation that determines the programmed output
resistance between Wx and Bx is:

RD

()

WB WB FS W

D

=× +

1024

RR

_

(1)

where D is the decimal equivalent of the data contained in the
RDAC register, R
W and B, and R

is the full-scale resistance between terminals

WB_FS

is the wiper resistance.

W

For example, the following output resistance values will be set for
the following RDAC latch codes with V

= 25 kΩ programmable resistors):

R

WB_FS

Table VIII. RWB at Selected Codes (R

DR

WB

(D)

= 5 V (applies to

DD

= 25 k)

WB_FS

(DEC) () Output State

1023 25026 Full-Scale
512 12550 Mid Scale
1 74.4 1 LSB
050Zero-Scale (Wiper contact resistance)

Note that in the zero-scale condition a finite wiper resistance of
50 Ω is present. In this state, care should be taken to limit the
current flow between W and B to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.

Channel-to-channel R
scale. The change in R

matching is well within 1% at full-

WB

with temperature has a 35 ppm/°C

WB

temperature coefficient.

REV. B–12–

Typical Performance Characteristics–ADN2850

CODE

36

16

0 1200200 400 600 800 1000

34

28

22

20

18

32

30

26

24

OHMS

TEMPERATURE – C

4

–40 –20 0 20 100

CURRENT – A

40

3

2

1

0

–1

60 80

ISS @ VDD/VSS = 2.7V/0V

I

DD

@ VDD/VSS = 2.7V/0V

I

SS

@ VDD/VSS = 5V/0V

I

DD

@ VDD/VSS = 5V/0V

0.25

FREQUENCY – Hz

0.0E+00

I

DD

– mA

0

0.20

0.15

0.10

0.05

2.0E+06 4.0E+06 6.0E+06 8.0E+06 1.0E+07 1.2E+07

MIDSCALE

FULL SCALE

ZERO SCALE

VDD/VSS = 5V/0V
R

AR

= 25k

1.0

0.8

0.6

0.4

0.2

0

R-INL ERROR – LSB

–0.2

–0.4

–0.6

0 200 400 600 800

DIGITAL CODE

TPC 1. R-INL vs. Code, TA = 40C, 25C,

85

C Overlay, RAB = 25 k

0.4

0.2

0

Ω

+25C
–40C
+85C

1000

TPC 4. Wiper On-Resistance vs. Code

–0.2

–0.4

R-DNL ERROR – LSB

–0.6

–0.8

0 200 400 600 1000

DIGITAL CODE

TPC 2. R-DNL vs. Code, TA = 40C, 25C,

85

C Overlay, RAB = 25 k

120

100

C

80

60

40

20

0

REV. B

–20

–40

RHEOSTAT MODE TEMPCO – ppm/ 

–60

–80

TPC 3.∆RWB/∆T Rheostat Mode Tempco

25k VERSION

250k VERSION

3842561280

CODE – Decimal

Ω

VDD/VSS = 5.0V/0V
T

640512

= 25C

A

768

800

896

1023

–13–

TPC 5. IDD vs. Temperature, RAB = 25 k

Ω

TPC 6. IDD vs. Clock Frequency, RAB = 25 k

Ω

ADN2850

W

B

NC

I

W

DUT

V

MS

NC = NO CONNECT

A

DUT

V

SS

ICM

W

B

V

DD

NC

NC

VCM

GND

A

NC = NO CONNECT

IW = IA

= 25C

T

A

0.5V/DIV

RWB(D)

EXPECTED

MIDSCALE

NORMALIZED RESISTANCE

VA LU E

50S/DIV

TPC 7. Memory Restore During Power-On Reset

5V/DIV

CS

5V/DIV

CLK

V

5V/DIV

SDI

I

DD

20mA/DIV

4ms/DIV

TPC 8. IDD vs. Time (Save) Program Mode

100

TA = 25C

10

– mA

WB_MAX

1

0.1

THEORETICAL – I

0.01

TPC 10. I

R

= 25k

WB_FS

R

WB_FS

CODE – Decimal

vs. Code

WB_MAX

= 250k

896768640512384128 2560

1024

TEST CIRCUITS

Test Circuits 1 to 3 show some of the test conditions used in the
Specifications table.

5V/DIV

CS

5V/DIV

CLK

SDI

5V/DIV

I

DD

2mA/DIV

SUPPLY CURRENT RETURNS TO MINIMUM POWER
CONSUMPTION IF INSTRUCTION 0 (NOP) IS
EXECUTED IMMEDIATELY AFTER INSTRUCTION 1
(READ EEMEM)

4ms/DIV

TPC 9. IDD vs. Time (Read) Program Mode

Test Circuit 1. Resistor Position Nonlinearity
Error (Rheostat Operation; R-INL, R-DNL)

0.1V

R

=

SW

DUT

B

W

ISW

CODE = 00

TO V

V

SS

I

SW

H

+

0.1V

_

DD

Test Circuit 2. Incremental ON Resistance

Test Circuit 3. Common-Mode Leakage Current

REV. B–14–

ADN2850

PROGRAMMING EXAMPLES

The following programming examples illustrate the typical sequence
of events for various features of the ADN2850. Users should refer
to Table II for the instructions and data-word format. The instruc­tion numbers, addresses, and data appearing at SDI and SDO pins
are displayed in hexadecimal format in the following examples.

Table IX. Scratch Pad Programming

SDI SDO Action

B00100

XXXXXXHLoads data 100H into RDAC1 register,

H

Wiper W1 moves to 1/4 full-scale
position.

B10200

H

B00100

Loads data 200H into RDAC2 register,

H

Wiper 2 moves to 1/2 full-scale position.

Table X. Incrementing RDAC Followed by Storing
the Wiper Setting to EEMEM

SDI SDO Action

B00100

XXXXXXHLoads data 100H into RDAC1 register,

H

Wiper W1 moves to 1/4 full-scale position.
E0XXXX
E0XXXX

B00100HIncrements RDAC1 register by one to 101H.

H

E0XXXXHIncrements RDAC1 register by one to 102H.

H

Repeat the increment command –
(E0XXXX

until desired wiper

H)

position is reached

20XXXX

XXXXXXHSaves RDAC1 data into EEMEM1

H

Optionally tie WP to GND to protect

EEMEM values

Table XII. Using Left Shift by One to Increment 6 dB Steps

SDI SDO Action

C0XXXX

XXXXXXHMoves wiper 1 to double the present

H

data contained in RDAC1 register.

C1XXXX

C0XXXXHMoves wiper 2 to double the present

H

data contained in RDAC2 register.

Table XIII. Storing Additional User Data in EEMEM

SDI SDO Action

32AAAA

XXXXXXHStores data AAAAH into spare EEMEM

H

location USER1. (Allowable to address
in 13 locations with maximum 16 bits
of data).

335555

32AAAAHStores data 5555H into spare EEMEM

H

location USER2. (Allowable to address
in 13 locations with maximum 16 bits
of data).

Table XIV. Reading Back Data From Various Memory Locations

SDI SDO Action

92XXXX

XXXXXXHPrepares data read from USER1

H

location.

00XXXX

92AAAAHNOP instruction 0 sends 24-bit word

H

out of SDO where the last 16 bits
contain the contents of USER1 location.
NOP command ensures device returns
to idle power dissipation state.

Table XI. Restoring EEMEM Values to RDAC Registers

EEMEM values for RDACs can be restored by: Power-On,
Strobing PR pin or Programming shown below.

SDI SDO Action

10XXXX

XXXXXXHRestores EEMEM1 value to RDAC1

H

register.

00XXXX

H

100100

NOP. Recommended step to minimize

H

power consumption.

8XXXXX

00XXXXHReset EEMEM1 and EEMEM2

H

values to RDAC1 and RDAC2 registers
respectively.

Table XV. Reading Back Wiper Setting

SDI SDO Action

B00200
C0XXXX

XXXXXXHSets RDAC1 to midscale.

H

B00200

H

Doubles RDAC1 from midscale to

H

full-scale.

A0XXXX

C0XXXXHPrepares reading wiper setting from

H

RDAC1 register.

XXXXXX

A003FFHReadback full-scale value from RDAC1

H

register.

Analog Devices offers a user-friendly ADN2850EVAL evaluation
kit that can be controlled by a personal computer through the printer
port. The driving program is self-contained, so no programming
languages or skills are needed.

REV. B

–15–

ADN2850

APPLICATIONS
Optical Transmitter Calibration with ADN2841

Together with the multirate 2.7 Gbps Laser Diode Driver ADN2841,
the ADN2850 forms an optical supervisory system where the dual
programmable resistors are used to set the laser average optical
power and extinction ratio (see Figure 11). The ADN2850 is
particularly ideal for the optical parameter settings because of its
high resolution, compact footprint, and superior temperature
coefficient characteristics.

The ADN2841 is a 2.7 Gbps laser diode driver that uses a unique
control algorithm to manage both the laser average power and
extinction ratio after the laser initial factory calibration. It stabilizes
the laser data transmission by continuously monitoring its optical
power, and correcting the variations caused by temperature and
the laser degradation over time. In the ADN2841, the I
the laser diode current. Through its dual-loop power and extinction
ratio control, calibrated by the ADN2850, the internal driver
controls the bias current I
It also regulates the modulation current I

and consequently the average power.

BIAS

by changing the

MODP

modulation current linearly with slope efficiency. Any changes in
the laser threshold current or slope efficiency are therefore com­pensated. As a result, this optical supervisory system minimizes the
laser characterization efforts and enables designers to apply com­parable lasers from multiple sources.

Incoming Optical Power Monitoring

The ADN2850 comes with a pair of matched diode connected
PNPs, Q

and Q2, that can be used to configure an incoming optical

1

power monitoring function. With a reference current source, an
instrumentation amplifier, and a logarithmic amplifier, this feature
can be used to monitor the optical power by knowing the dc
average photodiode current from the following relationships:

I

V=V =V

1 BE1 T

V=V =VI

2 BE2 T

In

CS1

I

1

I

CS2

n

I

2

monitors

MPD

(2)

(3)

V

CC

I

ADN2841

DIN

DINQ

MPD

I

MODP

IDTONE

I

BIAS

CLK

SDI

CS

ADN2850

CONTROL

EEMEM

EEMEM

RDAC1

RDAC2

W1

B1

W2

B2

DIN

DINQ

IDTONE

PSET

ERSET

Figure 11. Optical Supervisory System

Knowing IC1 = a1  I
therefore a and I

are matched. Combining Equations 2 and 3

S

PD, IC2

= a2  I

and Q1–Q2 are matched,

REF,

theoretically yields:





I

V–V=VIn

REF

T21





I





PD

Where IS1 and IS2 are saturation current

, V2 are VBE, base-emitted voltages of the diode connector

V

1

transistors

is the thermal voltage, which is equal to k × T/q.

V

T

= 26 mV at 25°C

V

T

k = Boltzmann’s constant = 1.38E–23 Joules/Kelvin
q = electron charge = 1.6E–19 coulomb
T = temperature in Kelvin

= photodiode current

I

PD

= reference current

I

REF

Figure 12 shows such a conceptual circuit.

V

CC

(4)

POST

V

DD

V

SS

ADN2850

W

1

B

1

AMP

0.75 BIT RATE

AD623

G

IN AMP

LOG AMP

LPF

(1 + 100k/RG)  (V2 – V1)

VT COMPENSATION

C
PRC
THERMISTOR

TIA

10nF

I

V

W

1

2

Q

1

B

2

GND

–5V

I

PD

REF

R

V

2

Q

2

CDR

DATA

CLOCK

LOG
AVERAGE
POWER

Figure 12. Conceptual Incoming Optical Power Monitoring Circuit

REV. B–16–

The output voltage represents the average incoming optical power.
The output voltage of the log stage does not have to be accurate
from device to device, as the responsivity of the photodiode will
change between devices. An op amp stage is shown after the log
amp stage, which compensates for V

variation over temperature.

T

Equation 4 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V

VV=0.026 In

2 —1

and V1. A curve fit approximation yields

2





0.001

×




+

003.



I



PD

(5)

Such offset is believed to be caused by the transistors self-heating
and the thermal gradient effect. As seen in Figure 13, the error
between an approximation and the actual performance ranges is
less than 0% to –4% from 0.1 mA to 0.1 A.

0.30

0.25

0.20

– V

1

0.15

– V

2

V

0.10

0.05

DEVICE 1

DEVICE 2

DEVICE 3

CURVE FIT

I
T

REF

A

= 1mA

= 25C

ERROR

12

9

6

3

0

APPROXIMATING ERROR – %

–3

ADN2850

B2

51200

W2

R

(6)

W1

B1

Figure 14. Reduce Resistance by Half with Linear
Adjustment Characteristics

Much lower resistance can also be achieved by paralleling a
discrete resistor as shown in Figure 15.

W1

B1

Figure 15. Resistor Scaling with Pseudo-Log Taper
Adjustment Characteristics

The equivalent resistance at a given setting is approximated as:

DR

×+

R=

eq

×++×

WB FS_

WB_FS

51200 1024DR R

In this approach, the adjustment is not linear but pseudo­logarithmic. Users should be aware of the need for tolerance matching
as well as temperature coefficient matching of the components.

BASIC RDAC SPICE MODEL

0

1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

IPD – A

Figure 13. Typical V2 – V1 vs. I

PD

at I

REF

–6

= 1 mA

and TA = 25°C

Resistance Scaling

The ADN2850 offers either 25 kΩ or 250 kΩ full-scale resistance.
Users who need lower resistance and still maintain the numbers
of step adjustment can parallel two or more devices. Figure 14
shows a simple scheme of paralleling both channels of the pro­grammable resistors. In order to adjust half of the resistance
linearly per step, users need to program both devices coherently
with the same settings. Note that since the devices will be pro­grammed one after another, an intermediate state will occur, and
this method may not be suitable for certain applications.

RDAC

25k

CW = 80pF

W

C

B

B

= 11pF

Figure 16. RDAC Circuit Simulation Model (RDAC = 25 kΩ)

The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RADCs. A general
parasitic simulation model is shown in Figure 16.

Listing I provides a macro model net list for the 25 kΩ RDAC:

Listing I. Macro Model Net List for RDAC

.PARAM D = 1024, RDAC = 25E3

*

.SUBCKT RDAC (W, B)

*

RWB W B {D/1024  RDAC  50}

CW W 0 80E-12

CB B 0 11E-12

*

.ENDS RDAC

REV. B

–17–

ADN2850

OUTLINE DIMENSIONS

16-Lead Frame Chip Scale Package [LFCSP]

5 x 5 mm Body

(CP-16 5x5)

Dimensions shown in millimeters

PIN 1

INDICATOR

0.90 MAX

0.85 NOM

12 MAX

SEATING
PLANE

5.0

BSC SQ

TOP

VIEW

0.70 MAX

0.65 NOM

COMPLIANT TO JEDEC STANDARDS MO-220VHHB

0.40

0.33

0.28

4.75

BSC SQ

0.20 REF

0.60 MAX

0.80 BSC

0.05 MAX

0.01 NOM

COPLANARITY

0.75

0.60

0.50

0.08

13

12

9

8

0.60 MAX

BOTTOM

VIEW

16

1

4

5

2.40 BSC

PIN 1
INDICATOR

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40
BSC

SEATING

PLANE

0.20

0.09

0.75



8



0

0.60

0.45

3.25

3.10

2.95

REV. B–18–

ADN2850

Revision History

Location Page

9/02—Data sheet changed from REV. A to REV. B.

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to Calculating Actual Full-Scale Resistance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to Table VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REV. B

–19–

C02660–0–9/02(B)

–20–

PRINTED IN U.S.A.