Analog Devices ADN2850 b Datasheet

Nonvolatile Memory, Dual

ADDR

DECODE

ADN2850

RDAC1

SERIAL

INTERFACE

CS

CLK

SDI

SDO

PR

WP

RDY

V

DD

V

SS

GND

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

26 BYTES

USER EEMEM

PWR ON
PRESET

EEMEM

CONTROL

W1

B1

RDAC2

W2

B2

CURRENT

MONITOR

I

1

I

2

V

1

V

2

CODE – Decimal

100

75

0

0 1023256

R

WB

(D) – % of Full-Scale R

WB

512 768

50

25

a

1024-Position Programmable Resistors

FEATURES
Dual, 1024-Position Resolution
25 k, 250 k Full-Scale Resistance
Low Temperature Coefficient: 35 ppm/C
Nonvolatile Memory

1

Preset Maintains Wiper Settings
Permanent Memory Write-Protection
Wiper Settings Read Back
Actual Tolerance Stored in EEMEM

1

Linear Increment/Decrement
Log Taper Increment/Decrement
SPI Compatible Serial Interface
3 V to 5 V Single Supply or 2.5 V Dual Supply
26 Bytes User Nonvolatile Memory for Constant Storage
Current Monitoring Configurable Function
100-Year Typical Data Retention T

= 55C

A

APPLICATIONS
SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser

Diode Driver Optical Supervisory Systems

GENERAL DESCRIPTION

The ADN2850 provides dual-channel, digitally controlled program­mable resistors

2

with resolution of 1024 positions. These devices
perform the same electronic adjustment function as a mechanical
rheostat with enhanced resolution, solid-state reliability, and
superior low temperature coefficient performance. The ADN2850’s
versatile programming via a standard serial interface allows
16 modes of operation and adjustment, including scratch pad pro­gramming, memory storing and retrieving, increment/decrement,
log taper adjustment, wiper setting readback, and extra user
defined EEMEM

1

.

Another key feature of the ADN2850 is that the actual tolerance
is stored in the EEMEM. The actual full-scale resistance can
therefore be known, which is valuable for tolerance matching
and calibration.

In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC

2

register, which sets the resis­tance between terminals W and B. The RDAC register can also
be loaded with a value previously stored in the EEMEM register.
The value in the EEMEM can be changed or protected. When
changes are made to the RDAC register, the value of the new
setting can be saved into the EEMEM. Thereafter, such value will
be transferred automatically to the RDAC register during system
power ON, which is enabled by the internal preset strobe.
EEMEM can also be retrieved through direct programming and
external preset pin control.

*Patent pending

NOTES

1

The term nonvolatile memory and EEMEM are used interchangeably.

2

The term programmable resistor and RDAC are used interchangeably.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

ADN2850

*

FUNCTIONAL BLOCK DIAGRAM

Figure 1. RWB(D) vs. Decimal Code

The linear step increment and decrement commands enable the
setting in the RDAC register to be moved UP or DOWN, one step
at a time. For logarithmic changes in wiper setting, a left/right
bit shift command adjusts the level in ±6 dB steps.

The ADN2850 is available in the 5 mm  5 mm 16-lead frame chip
scale LFCSP and thin 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADN2850–SPECIFICATIONS

(VDD = 3 V to 5.5 V and –40C < TA < +85C,

ELECTRICAL CHARACTERISTICS 25 k, 250 k VERSIONS

unless otherwise noted.)

1

Parameter Symbol Conditions Min Typ2Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs)

Resistor Differential Nonlinearity3R-DNL R
Resistor Integral Nonlinearity
Resistance Temperature Coefficient R
Wiper Resistance R

3

R-INL R

WB/T

W

WB

WB

VDD = 5 V, IW = 100 µA,

–2 +2 LSB
–4 +4 LSB

35 ppm/°C

Code = Half-scale 50 100 Ω

= 3 V, IW = 100 µA,

V

DD

Code = Half-scale 200 Ω

Channel Resistance Matching R
Nominal Resistor Tolerance R

RESISTOR TERMINALS

Terminal Voltage Range

4

Capacitance5 Bx C

5

Capacitance

Wx C

V

W, B

B

W

WB/RWB

WB

Ch 1 and 2 RWB, Dx = 3FF

H

–30 +30 %

V
f = 1 MHz, measured to GND,
Code = Half-scale 11 pF
f = 1 MHz, measured to GND,

0.1 %

SS

V

DD

V

Code = Half-scale 80 pF

Common-Mode Leakage Current6I

CM

VW = VB = VDD/2 0.01 ±2 µA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Logic High V

Input Logic Low V

Output Logic High (SDO, RDY) V
Output Logic Low V
Input Current I
Input Capacitance

5

IH

IL

IH

IL

IH

IL

OH

OL

IL

C

IL

With respect to GND, VDD = 5 V 2.4 V
With respect to GND, VDD = 5 V 0.8 V
With respect to GND, VDD = 3 V 2.1 V
With respect to GND, VDD = 3 V 0.6 V
With respect to GND,
V

= +2.5 V, V

DD

= –2.5 V 2.0 V

SS

With respect to GND,

= +2.5 V, V

V

DD

R

= 2.2 kΩ to 5 V 4.9 V

PULL-UP

IOL = 1.6 mA, V
VIN = 0 V or V

= –2.5 V 0.5 V

SS

= 5 V 0.4 V

LOGIC

DD

±2.25 µA

5pF

POWER SUPPLIES

Single-Supply Power Range V
Dual-Supply Power Range V
Positive Supply Current I

Positive Supply Current I
Programming Mode Current I
Read Mode Current

7

Negative Supply Current I

Power Dissipation

8

Power Supply Sensitivity P

CURRENT MONITOR TERMINALS

Current Sink at V
Current Sink at V

DYNAMIC CHARACTERISTICS

9

1

2

5, 10

Resistor Noise Spectral Density e
Analog Crosstalk (C

)CTVB1 = VB2 = 0 V, Measured VW1 with

W1/CW2

DD

DD/VSS

DD

DD

DD(PG)

I

DD(XFR)

SS

P

DISS

SS

I

1

I

2

N_WB

VSS = 0 V 3.0 5.5 V

±2.25 ± 2.75 V
VIH = VDD or VIL = GND,

= 25oC24.5 µA

T

A

VIH = VDD or VIL = GND 3.5 6.0 µA
VIH = VDD or VIL = GND 35 mA
VIH = VDD or VIL = GND 0.3 3 9 mA
VIH = VDD or VIL = GND,

= +2.5 V, V

V

DD

= –2.5 V 3.5 6.0 µA

SS

VIH = VDD or VIL = GND 18 50 µW
∆VDD = 5 V ± 10% 0.002 0.01 %/%

0.0001 10 mA
10 mA

R

= 25 kΩ/250 kΩ, f = 1 kHz 20/64 nV/√Hz

WB_FS

= 100 mV p-p @ f = 100 kHz,

V

W2

Code 1 = Code 2 = 200

H

–65 dB

REV. B–2–

ADN2850

Parameter Symbol Conditions Min Typ2Max Unit

INTERFACE TIMING CHARACTERISTICS (apply to all parts)

Clock Cycle Time (t
CS Setup Time t
CLK Shutdown Time to CS Rise t
Input Clock Pulsewidth t4 , t
Data Setup Time t
Data Hold Time t

CS to SDO – SPI Line Acquire t
CS to SDO – SPI Line Release t

CLK to SDO Propagation Delay

CS High Pulsewidth
CS High to CS High
RDY Rise to CS Fall t
CS Rise to RDY Fall Time t

Read/Store to Nonvolatile EEMEM
CS Rise to Clock Edge Setup t
Preset Pulsewidth (Asynchronous) t
Preset Response Time to Wiper Setting t

)t

CYC

12

13

13

1

2

3

5

6

7

8

9

t

10

t

12

t

13

14

15

14

t

16

17

PRW

PRESP

Clock Level High or Low 10 ns
From Positive CLK Transition 5 ns
From Positive CLK Transition 5 ns

RP = 2.2 kΩ, CL < 20 pF 50 ns

Applies to Command 2H, 3H, 9

Not Shown in Timing Diagram 50 ns
PR Pulsed Low to Refresh 140 µs
Wiper Positions

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

NOTES

1

Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.

2

Typicals represent average readings at 258C and VDD = 5 V.

3

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for V

4

Resistor terminals W and B have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V

7

Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.

8

P

DISS

9Applies to photodiode of optical receiver.

10

All dynamic characteristics use VDD = +2.5 V and V

11

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using both VDD = 3 V and 5 V.

12

Propagation delay depends on value of VDD, R

13

Valid for commands that do not activate the RDY pin.

14

RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA= –40°C
and VDD < 3 V extends the save time to 35 ms.

15

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

16

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will
derate with junction temperature.

Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil  103 mil, 10,197 sq mil.

15

16

is calculated from (IDD  VDD) + (ISS  VSS).

PULL_UP

= –2.5 V.

SS

, and CL. See Applications section.

5, 11

20 ns
10 ns
1t

10 ns
4t
0ns

0.15 0.3 ms

H

35 ms

10 ns

100 K Cycles

100 Years

= 2.7 V and IW ~ 400 µA for V

DD

/2.

DD

40 ns
50 ns

= 5 V.

DD

CYC

CYC

REV. B

–3–

ADN2850

TIMING DIAGRAMS

CS

CLK

CPOL = 1

SDO

SDI

RDY

CPHA = 1

t

t

LSB

3

t

9

t

15

t

t

2

t

8

*

t

14

*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

5

t

4

t

10

MSB LSB OUT

t

7

t

6

MSB

t

11

Figure 2a. CPHA = 1 Timing Diagram

12

t

13

t

17

t

16

CS

CLK

CPOL = 0

SDO

SDI

RDY

CPHA = 0

t

12

t

1

t

2

t

8

MSB OUT LSB

MSB IN

t

14

*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

t

5

t

4

t

10

t

7

t

6

LSB

t

3

t

17

t

11

t

9

*

t

15

Figure 2b. CPHA = 0 Timing Diagram

t

13

t

16

REV. B–4–

ADN2850

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V

V

SS

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

, VW to GND . . . . . . . . . . . . . . . . V

V

B

, I

I

B

W

Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 mA

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA

Digital Inputs and Output Voltage

to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

Operating Temperature Range3 . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering

4

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C

1

– 0.3 V, V

SS

) . . . . . . . . . 150°C

J MAX

+ 0.3 V

DD

+ 0.3 V

DD

Thermal Resistance Junction-to-Ambient θ

JA,

LFCSP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

Thermal Resistance Junction-to-Case θ

JC,

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W

Package Power Dissipation = (T

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the B and W terminals at a given resistance.

3

Includes programming of nonvolatile memory.

4

Applicable to TSSOP-16 only. For LFCSP-16, please consult factory for details.

J MAX

– TA)/θ

JA

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C

ORDERING GUIDE

R

WB_FS

RDNL RINL Temperature Package Package Ordering

Model (k) (LSB) (LSB) Range (°C) Description Option Quantity Top Mark*

ADN2850BCP25 25 ± 2 ±4 –40 to +85 LFCSP-16 CP-16 96 BCP25
ADN2850BCP25-RL7 25 ± 2 ±4 –40 to +85 LFCSP-16 CP-16 1,000 BCP25

7" Reel

ADN2850BCP250 250 ±2 ± 4 –40 to +85 LFCSP-16 CP-16 96 BCP250
ADN2850BCP250-RL7 250 ±2 ±4 –40 to +85 LFCSP-16 CP-16 1,000 BCP250

7" Reel

ADN2850BRU25 25 ± 2 ±4 –40 to +85 TSSOP-16 RU-16 96 2850B25
ADN2850BRU25-RL7 25 ± 2 ±4 –40 to +85 TSSOP-16 RU-16 1,000 2850B25

7" Reel

*Line 1 contains product number, ADN2850, line 2 Top Mark branding contains differentiating detail by part type, line 3 contains lot number, line 4 contains product

date code YYWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADN2850 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

WARNING!

ESD SENSITIVE DEVICE

ADN2850

TOP VIEW

(Not To Scale)

1

2

3

4

5

6

7

8

SDI

SDO

GND

V

1

V

SS

W1

ADN2850BRU

CLK

B1

16

15

14

13

12

11

10

9

CS

PR

WP

V

DD

V

2

W2

B2

RDY

SDO

GND

V

1

2

3

SS

4

V

1

CS

RDY

CLK

SDI

16

15 14 13

ADN2850BCP

CHIP SCALE

PACKAGE

8765

B2

B1

W1

W2

PIN CONFIGURATIONS

12

PR

11

WP

10

V

DD

9

V

2

ADN2850BCP PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1SDO Serial Data Output Pin. Open-Drain output

requires external pull-up resistor. CMD_9 and
CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of

multiple packages.
2GND Ground Pin, logic ground reference
3V

SS

Negative Supply. Connect to zero volts for

single-supply applications.
4V

1

Log Output Voltage 1 generated from internal

diode configured transistor
5W1Wiper terminal of RDAC1 ADDR

(RDAC1) = 0

.

H

6B1B terminal of RDAC1
7B2B terminal of RDAC2
8W2Wiper terminal of RDAC2. ADDR

9V

2

(RDAC2) = 1

Log Output Voltage 2 generated from internal

.

H

diode configured transistor
10 V

DD

Positive Power Supply Pin
11 WP Write Protect Pin. When active low, WP

prevents any changes to the present register

contents, except PR and CMD_1 and CMD_8

will refresh the RDAC register from EEMEM.

Execute a NOP instruction before returning

to WP high.
12 PR Hardware Override Preset Pin. Refreshes the

scratch pad register with current contents of

the EEMEM register. Factory default loads

midscale 51210 until EEMEM loaded with

a new value by the user (PR is activated at

the logic high transition).
13 CS Serial Register chip select active low.

Serial register operation takes place when

CS returns to logic high.
14 RDY Ready. Active high open-drain output. Identifies

completion of commands 2, 3, 8, 9, 10, and PR.
15 CLK Serial Input Register Clock Pin. Shifts in

16 SDI Serial Data Input Pin. Shifts in one bit at a time

one bit at a time on positive clock edges.

on positive clock CLK edges. MSB loaded first.

ADN2850BRU PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1 CLK Serial Input Register Clock Pin. Shifts in

one bit at a time on positive clock edges.

2 SDI Serial Data Input Pin. Shifts in one bit at

a time on positive clock CLK edges.
MSB loaded first.

3SDO Serial Data Output Pin. Open-drain out put

requires external pull-up resistor. CMD_9
and CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of

multiple packages.
4GND Ground Pin, logic ground reference
5V

SS

Negative Supply. Connect to zero volts for

single-supply applications.
6V

1

Log Output Voltage 1 generated from internal

diode configured transistor
7W1Wiper terminal of RDAC1. ADDR

(RDAC1) = 0

.

H

8B1B terminal of RDAC1
9B2B terminal of RDAC2
10 W2 Wiper terminal of RDAC2. ADDR

11 V

(RDAC2) = 1

2

Log Output Voltage 2 generated from internal

.

H

diode configured transistor
12 V

DD

Positive Power Supply Pin
13 WP Write Protect Pin. When active low, WP prevents

any changes to the present contents except PR

and CMD_1 and CMD_8 will refresh the

RDAC register from EEMEM. Execute a NOP

instruction before returning to WP high.
14 PR Hardware Override Preset Pin. Refreshes the

scratch pad register with current contents of

the EEMEM register. Factory default loads

midscale 512

until EEMEM loaded with a

10

new value by the user (PR is activated at the

logic high transition).
15 CS Serial Register chip select active low. Serial

register operation takes place when CS returns

to logic high.
16 RDY Ready. Active high open-drain output. Identifies

completion of commands 2, 3, 8, 9, 10, and PR.

REV. B–6–