Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C
2.7 V to 5 V single supply or ±2.5 V dual supply
Current monitoring configurable function
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined
information
1M programming cycles
100-year typical data retention
driver, optical supervisory systems
Mechanical rheostat replacement
Instrumentation gain adjustment
Programmable filters, delays, time constants
Sensor calibration
GENERAL DESCRIPTION
The ADN2850 is a dual-channel, nonvolatile memory1, digitally
controlled resistors
guaranteed maximum low resistor tolerance error of ±8%. The
device performs the same electronic adjustment function as a
mechanical rheostat with enhanced resolution, solid state
reliability, and superior low temperature coefficient
performance. The versatile programming of the ADN2850 via
an SPI®-compatible serial interface allows 16 modes of
operation and adjustment including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up table, or system identification
information.
1
The terms nonvolatile memory and EEMEM are used interchangeably.
2
The terms digital resistor and RDAC are used interchangeably.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
2
with 1024-step resolution, offering
Nonvolatile Memory, Dual
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC
2
register, which sets the
resistance between Terminal W and Terminal B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.
The EEMEM content can be restored dynamically or through
external
EE
PR
AA strobing, and a AA
EE
WP
AA function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.
The ADN2850 patterned resistance tolerance is stored in the
EEMEM. The actual full scale resistance can, therefore, be
known by the host processor in readback mode. The host can
1
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.
The ADN2850 is available in the 5 mm × 5 mm 16-lead frame
chip scale LFCSP and thin, 16-lead TSSOP package. The part is
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADN2850 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted. These
specifications apply to versions with a date code 1209 or later.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (All RDACs)
Resolution N 10
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB
Nominal Resistor Tolerance ∆RWB/RWB Code = full scale −8 +8 %
Resistance Temperature Coefficient3 (∆RWB/RWB)/
Terminal Voltage Range3 VB, VW VSS VDD V
Capacitance Bx3 CB f = 1 MHz, measured to GND,
6
∆T × 10
Code = full scale ±0.1 %
WB1/RWB2
Code = full scale 35 ppm/°C
11 pF
code = half-scale
Common-Mode Leakage Current
3, 4
ICM VW = VDD/2 0.01 ±1 µA
Input Logic 3
High VIH VDD = 5 V 2.4 V
VDD = 2.7 V 2.1 V
VDD = +2.5 V, VSS = −2.5 V 2.0 V
Low VIL VDD = 5 V 0.8 V
VDD = 2.7 V 0.6 V
VDD = +2.5 V, VSS = −2.5 V 0.5 V
code = half-scale
Output Logic High (SDO, RDY) VOH R
Output Logic Low VOL IOL = 1.6 mA, V
= 2.2 kΩ to 5 V (see Figure 25) 4.9 V
PULL-UP
= 5 V (see Figure 25) 0.4 V
LOGIC
Input Current IIL VIN = 0 V or VDD ±1 µA
Input Capacitance3 CIL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA
Negative Supply Current ISS VDD = +2.5 V, VSS = −2.5 V VIH = VDD or VIL = GND −4 −2 µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,
= GND, ISS ≈ 0
V
SS
2 mA
ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current5 IDD (restore) VIH = VDD or VIL = GND,
V
= GND, ISS ≈ 0
SS
320 µA
ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA
DISS
Rev. E | Page 3 of 28
ADN2850 Data Sheet
Parameter Symbol Conditions Min Typ1 Max Unit
CURRENT MONITOR TERMINALS
Current Sink at V1 I1 0.0001 10 mA
Current Sink at V2 I2 0.0001 10 mA
DYNAMIC CHARACTERISTICS
Resistor Noise Density e
RWB = 25 kΩ/250 kΩ, TA = 25°C 20/64
Analog Crosstalk CT VBX = GND, Measured VW1 with VW2 =
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum current in each code is defined by I
(see Figure 20).
3
Guaranteed by design and not subject to production test.
4
Common-mode leakage current is a measure of the dc leakage from any Terminal B, or Terminal W to a common-mode bias level of VDD/2.
5
EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.
6
P
is calculated from (IDD × VDD) + (ISS × VSS).
DISS
7
All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
3, 7
Code= full scale
N_WB
−95/−80
1 V
, f = 1 kHz, Code 1 = midscale,
RMS
Code 2 = midscale,
= 25 kΩ/250 kΩ
R
WB
WB = (VDD − 1)/RWB.
nV/√Hz
dB
Rev. E | Page 4 of 28
Data Sheet ADN2850
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
CLK to SDO Propagation Delay
t10
RP = 2.2 kΩ, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 kΩ, CL < 20 pF
0
ns
Read EEMEM Time4
t16
Applies to instructions 0x8, 0x9, 0x10
7 30
µs
Data Retention
100 Years
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V
= 3 V and VDD = 5 V.
DD
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
Clock Cycle Time (t
EE
AA Setup Time
CS
CLK Shutdown Time to AA
) t1 20 ns
CYC
EE
AA Rise t
CS
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
EE
AA
AA to SDO-SPI Line Acquire t
CS
EE
AA
AA to SDO-SPI Line Release t
CS
= tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
R
t2 10 ns
1 t
3
40 ns
8
50 ns
2
10F
9
CYC
EE
AA
AA High Pulse Width11F
CS
AA
EE AAHigh to AA
CS
RDY Rise to AA
EE
AA
AA Rise to RDY Fall Time t
CS
CS
CS
Store EEMEM Time
EE
AA
AA Rise to Clock Rise/Fall Setup t
CS
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY
Endurance
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Propagation delay depends on the value of VDD, R
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms,
5
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
3
t12
EE
3
AA High
t13 4 t
EE
AA Fall t
4,
5
12F
13F
t16 Applies to instructions 0x2, 0x3 15 50 ms
6
14F
t
6
6
t
0 ns
14
0.15 0.3 ms
15
10 ns
17
50 ns
PRW
t
PRESP
EEMEM
AA
EE
pulsed low to refresh wiper positions
AA
PR
10 ns
30 µs
30 µs
7
15F
TA = 25°C 1
100
8
16F
, and CL.
PULL-UP
PR
hardware pulse ~ 30 µs.
derates with junction temperature in the Flash/EE memory.
CYC
MCycles
kCycles
Rev. E | Page 5 of 28
ADN2850 Data Sheet
CPOL = 1
t
12
t
13
t
3
t
17
t
9
t
11
t
5
t
4
t
2
t
1
CLK
t
8
B24*
B23 (MSB)B0 (LSB)
B23 (MSB)
HIGH
OR LOW
HIGH
OR LOW
B23B0
B0 (LSB)
RDY
CPHA = 1
t
10
t
7
t
6
t
14
t
15
t
16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLYTHE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATATO THE POSITIVE EDGE OF THE CLOCK.
SDO
SDI
CS
02660-002
t
12
t
13
t
3
t
17
t
9
t
11
t
5
t
4
t
2
t
1
CLK
CPOL = 0
t
8
B23 (MSB OUT)B0 (LSB)
SDO
B23 (MSB IN)
B23B0
HIGH
OR LOW
HIGH
OR LOW
B0 (LSB)
SDI
RDY
CPHA = 0
t
10
t
7
t
6
t
14
t
15
t
16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
*
CS
02660-003
Timing Diagrams
Figure 2. CPHA = 1 Timing Diagram
Figure 3. CPHA = 0 Timing Diagram
Rev. E | Page 6 of 28
Data Sheet ADN2850
Vapor Phase (60 sec)
215°C
Junction-to-Case θJC, TSSOP-16
28°C/W
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
to VSS 7 V
V
DD
VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
, IW
I
B
Pulsed0F0F1 ±20 mA
Continuous
±2 mA
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
2
1F1F
Operating Temperature Range
−40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Includes programming of nonvolatile memory.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. E | Page 7 of 28
ADN2850 Data Sheet
SDI
SDO
GND
V1
V
SS
W1
CLK
B1
CS
PR
WP
V
DD
V2
W2
B2
RDY
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADN2850
TOP VIEW
(Not to Scale)
02660-005
Pin No.
Mnemonic
Description
2
SDI
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
7
W1
Wiper Terminal of RDAC1. ADDR (RDAC1) = 0x0.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
4 GND Ground Pin, Logic Ground Reference.
5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
6 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
8 B1 Terminal B of RDAC1.
9
10
B2 Terminal B of RDAC2.
W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
12
13
14 AA
15 AA
16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
VDD Positive Power Supply.
EE
AA
Optional Write Protect. When active low, AA
WP
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie AA
EE
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
PR
register. Factory default loads midscale 512
at the logic high transition. Tie AA
EE
Serial Register Chip Select Active Low. Serial register operation takes place when AA
CS
Instruction 9, Instruction 10, and
PR
EE
AA to V
AA
PR
EE
AA.
EE
AA
prevents any changes to the present contents, except AA
WP
until EEMEM is loaded with a new value by the user. AA
10
, if not used.
DD
WP
EE
AA to V
, if not used.
DD
CS
EE
AA returns to logic high.
PR
PR
EE
AA
strobe.
EE
AA is activated
Rev. E | Page 8 of 28
Data Sheet ADN2850
A
DN2850
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
SS
1
SDI
16
1SDO
2GND
(EXPOSED
3V
4V
5
1
W
CLK
15
PAD)
6
B1
CS
RDY
14
13
12 PR
11 WP
10 V
DD
9V
2
8
7
2
B2
W
02660-105
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
SS
OR IS TIED TO V
.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
2 GND Ground Pin, Logic Ground Reference.
3 VSS
Negative Supply. Connect to 0 V for single-supply applications. If V
is used in dual supply, it must be able to sink
SS
2 mA for 15 ms when storing data to EEMEM.
4 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
5 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
6 B1 Terminal B of RDAC1.
7 B2 Terminal B of RDAC2.
8 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
9 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
10 VDD Positive Power Supply.
11
12
13
E
AWP
Optional Write Protect. When active low, AWP
E
APR
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
E
ACS
Serial Register Chip Select Active Low. Serial register operation takes place when ACS
14 RDY
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie
register. Factory default loads midscale until EEMEM is loaded with a new value by the user.
at the logic high transition. Tie
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and
E
A
APR
to VDD, if not used.
E
A
APR
.
E
A
prevents any changes to the present contents, except APR
E
A
AWP
to VDD, if not used.
E
A
returns to logic high.
15 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
16 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
EP Exposed Pad. The exposed pad is left floating or is tied to VSS.
E
A
APR
is activated
E
A
strobe.
Rev. E | Page 9 of 28
ADN2850 Data Sheet
DIGITAL CODE
02004006001000
INL ERROR (LSB)
800
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–40°C
+25°C
+85°C
02660-008
DIGITAL CODE
02004006001000
DNL ERROR (LSB)
800
0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
02660-009
–40°C
+25°C
+85°C
02660-011
CODE (Decimal)
RHEOSTAT MODE TEMPCO (ppm/°C)
200
180
160
140
120
100
80
60
40
20
0
01023768512256
25kΩ
250kΩ
CODE (Decimal)
02004008006001000
WIPER ON RESISTANCE (Ω)
60
50
40
30
20
10
0
2.7V
3.0V
3.3V
5.0V
5.5V
02660-012
TEMPERATURE (°C)
–40–20025406085
I
DD
/I
SS
(µA)
3
–3
–2
–1
0
1
2
I
DD
= 2.7V
I
DD
= 3.3V
I
DD
= 3.0V
I
DD
= 5.5V
IDD= 5.0V
ISS= 2.7V
I
SS
= 3.3V
I
SS
= 3.0V
I
SS
= 5.5V
I
SS
= 5.0V
02660-013
FREQUENCY (MHz)
11098765432
I
DD
(µA)
50
10
20
30
40
0
FULL SCALE
MIDSCALE
ZERO SCALE
02660-014
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
Figure 7. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
The ADN2850 digital programmable resistor is designed to
operate as a true variable resistor. The resistor wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing unlimited changes of
resistance settings. The scratchpad register can be programmed
with any position setting using the standard SPI serial interface by
loading the 24-bit data-word. In the format of the data-word, the
first four bits are commands, the following four bits are addresses,
and the last 16 bits are data. When a specified value is set, this
value can be stored in a corresponding EEMEM register. During
subsequent power-ups, the wiper setting is automatically loaded to
that value.
Storing data to the EEMEM register takes about 15ms and
consumes approximately 2 mA. During this time, the shift
register is locked, preventing any changes from taking place.
The RDY pin pulses low to indicate the completion of this
EEMEM storage. There are also 13 addresses with two bytes
each of user-defined data that can be stored in the EEMEM
register from Address 2 to Address 14.
The following instructions facilitate the programming needs of
the user (see Tab l e 8 for details):
0. Do nothing.
1. Restore EEMEM content to RDAC.
2. Store RDAC setting to EEMEM.
3. Store RDAC setting or user data to EEMEM.
4. Decrement by 6 dB.
5. Decrement all by 6 dB.
6. Decrement by one step.
7. Decrement all by one step.
8. Reset EEMEM content to RDAC.
9. Read EEMEM content from SDO.
10. Read RDAC wiper setting from SDO.
11. Write data to RDAC.
12. Increment by 6 dB.
13. Increment all by 6 dB.
14. Increment by one step.
15. Increment all by one step.
Table 14 to Tabl e 20 provide programming examples that use
some of these commands.
SCRATCHPAD AND EEMEM PROGRAMMING
The scratchpad RDAC register directly controls the position of
the digital resistor wiper. For example, when the scratchpad register
is loaded with all 0s, the wiper is connected to Te rm in a l B of the
variable resistor. The scratchpad register is a standard logic
register with no restriction on the number of changes allowed,
but the EEMEM registers have a program erase/write cycle
limitation.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the proper
wiper position is determined, the user can load the serial data
input register with Instruction 2 (0x2), which stores the wiper
position data in the EEMEM register. After 15 ms, the wiper
position is permanently stored in nonvolatile memory.
Table 6 provides a programming example listing the sequence of
the serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.
Table 6. Write and Store RDAC Settings to EEMEM Registers
SDI SDO Action
0xB00100 0xXXXXXX Writes data 0x100 to the RDAC1 register,
Wiper W1 moves to 1/4 full-scale position.
0x20XXXX 0xB00100 Stores RDAC1 register content into the
EEMEM1 register.
0xB10200 0x20XXXX Writes Data 0x200 to the RDAC2 register,
Wiper W2 moves to 1/2 full-scale position.
0x21XXXX 0xB10200 Stores RDAC2 register contents into the
EEMEM2 register.
At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets the EEMEM values
of both channels. Finally, pulsing the
EEMEM settings. Operating the hardware control
requires a complete pulse signal. When
logic sets the wiper at midscale. The EEMEM value is not
loaded until
EE
PR
AA
AA returns high.
EE
PR
AA pin refreshes both
PR
EE
PR
AA
AA goes low, the internal
AA
EE
AA function
Rev. E | Page 13 of 28
ADN2850 Data Sheet
VALID
COMMAND
COUNTER
COMMAND
PROCESSOR
AND ADDRESS
DECODE
(FOR DAISY
CHAIN ONLY)
SERIAL
REGISTER
CLK
SDI
5V
R
PULL-UP
SDO
GND
PRWP
ADN2850
CS
02660-037
LOGIC
PINS
V
DD
GND
INPUTS
300Ω
02660-038
V
DD
GND
INPUT
300Ω
WP
02660-039
EEMEM PROTECTION
EE
The write protect (AA
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the
PR
AA
hardware EEMEM protection feature.
DIGITAL INPUT AND OUTPUT CONFIGURATION
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
EE
PR
low,
AA
AA and AA
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.
The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.
The equivalent serial data input and output logic is shown in
Figure 25
chip-select (
inputs is shown in
. The open-drain output SDO is disabled whenever
Figure 25. Equivalent Digital Input and Output Logic
WP
AA) pin disables any changes to the
EE
AA pulse. Therefore, AA
EE
WP
AA must be tied to V
EE
CS
AA
AA) is in logic high. ESD protection of the digital
EE
WP
AA can be used to provide a
, if they are not used. No
DD
Figure 26 and Figure 27.
Figure 27. Equivalent AA
EE
WP
AA Input Protection
SERIAL DATA INTERFACE
The ADN2850 contains a 4-wire SPI-compatible digital
interface (SDI, SDO,
must be loaded with MSB first. The format of the word is shown in
Table 7. The command bits (C0 to C3) control the operation of the
digital resistor according to the command shown in Table 8. A0
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage. Tab l e 10 provides an
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.
The ADN2850 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, ADN2850
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when
is multiple of four. In addition, the ADN2850 has a subtle
CS
feature that, if
AA
repeats the previous command (except during power-up). As a
the CLK or
result, care must be taken to ensure that no excessive noise exists in
EE
CS
AA
AA line that might alter the effective number-of-bits
pattern.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.
EE
CS
AA
AA, and CLK). The 24-bit serial data-word
EE
CS
AA
AA
goes high but remains in the register if it
EE
AA is pulsed without CLK and SDI, the part
Figure 26. Equivalent ESD Digital Input Protection
Rev. E | Page 14 of 28
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 28). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 28, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
Data Sheet ADN2850
CLK
R
P
2.2kΩ
SDISDO
U2
CS
CLK
SDISDO
U1
ADN2850
CS
V
DD
SCLK SS
MOSI
MICRO-
CONTROLLER
02660-040
ADN2850
V
SS
V
DD
W
B
02660-041
ADN2850
V
DD
GND
V
SS
C3
10µF
C4
10µFC20.1µF
C1
0.1µF
+
+
V
DD
V
SS
02660-042
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two ADN2850s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep
clocked into their respective serial registers.
EE
CS
AA
AA low until all 48 bits are
EE
CS
AA
AA is then pulled
high to complete the operation.
Figure 28. Daisy-Chain Configuration Using SDO
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the ADN2850
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Termi na l B, and
Terminal W that exceed V
forward-biased diodes (see Figure 29).
or VSS are clamped by the internal
DD
extends from V
to VDD, regardless of the digital input level.
SS
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal B, and Terminal W (see Figure 29), it is important to
power V
and VSS first before applying any voltage to Terminal
DD
B, and Terminal W. Otherwise, the diode is forward-biased such
that V
applying 5 V across Terminal W and Terminal B prior to V
causes the V
and VSS are powered unintentionally. For example,
DD
terminal to exhibit 4.3 V. It is not destructive to
DD
DD
the device, but it might affect the rest of the user’s system. The
ideal power-up sequence is GND, V
and V
, and VW. The order of powering VB, VW, and the digital
B
inputs is not important as long as they are powered after V
and V
.
SS
and VSS, digital inputs,
DD
DD
Regardless of the power-up sequence and the ramp rates of the
power supplies, when V
and VSS are powered, the power-on
DD
preset activates, which restores the EEMEM values to the RDAC
registers.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 µF to 0.1 µF disk or chip ceramic capacitors.
Also, apply low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 30).
Figure 29. Maximum Terminal Voltages Set by V
DD
and V
SS
The GND pin of the ADN2850 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the ADN2850 ground terminal should be joined remotely to
the common ground (see Figure 30). The digital input control
signals to the ADN2850 must be referenced to the device
ground pin (GND) and must satisfy the logic level defined in
the Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
Figure 30. Power Supply Bypassing
Rev. E | Page 15 of 28
ADN2850 Data Sheet
MSB
Command Byte 0
Data Byte 1
Data Byte 0
LSB
Restore EEMEM (A0) contents to RDAC (A0)
Store wiper setting. Store RDAC (A0) setting to
Read RDAC wiper setting from SDO output in the
Write contents of Serial Register Data Byte 0 and
5
In Table 7, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.
Table 7. 24-Bit Serial Data-Word
RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM
Command instruction codes are defined in Table 8.
Table 8. Command Operation Truth Table
Command
Number
0
1
2
320F4 0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0
5
4
21F
5
5
5
6
5
7
8
9
10
11
12
13
14
15
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a
full 24-bit data-word to completely clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the CS strobe returns to logic high.
4
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1.
EEMEM (A0). See Table 15.
Store contents of Serial Register Data Byte 0 and
Serial Register Data Bytes 1 (total 16 bits) to
EEMEM (ADDR). See Table 18.
0 1 0 0 0 0 0 A0 X … X X X … X
Decrement by 6 dB. Right-shift contents of RDAC
(A0) register, stop at all 0s.
0 1 0 1 X X X X X … X X X … X
Decrement all by 6 dB. Right-shift contents of all
RDAC registers, stop at all 0s.
0 1 1 0 0 0 0 A0 X … X X X … X
Decrement contents of RDAC (A0) by 1, stop at
all 0s.
0 1 1 1 X X X X X … X X X … X
Decrement contents of all RDAC registers by 1,
stop at all 0s.
1 0 0 0 0 0 0 0 X … X X X … X
Reset. Refresh all RDACs with their corresponding
EEMEM previously stored values.
1 0 0 1 A3 A2 A1 A0 X … X X X … X
Read contents of EEMEM (ADDR) from SDO
output in the next frame. See
1 0 1 0 0 0 0 A0 X … X X X … X
next frame. See Table 20.
1 0 1 1 0 0 0 A0 X … D9 D8 D7 … D0
Serial Register Data Byte 1 (total 10 bits) to RDAC
1 1 0 0 0 0 0 A0 X … X X X … X
5
1 1 0 1 X X X X X … X X X … X
(A0). See
Increment by 6 dB: Left-shift contents of RDAC (A0),
stop at all 1s. See
Increment all by 6 dB. Left-shift contents of all
Table 14.
Table 17.
RDAC registers, stop at all 1s.
5
1 1 1 0 0 0 0 A0 X … X X X … X
Increment contents of RDAC (A0) by 1, stop at all
1s. See Table 15.
5
1 1 1 1 X X X X X … X X X … X
Increment contents of all RDAC registers by 1,
stop at all 1s.
Table 19.
Rev. E | Page 16 of 28
Data Sheet ADN2850
00 0010 0000
00 0000 1111
11 1111 1111
00 0000 0000
CODE (From 1 to 1023 by 2.0 × 103)
0
GAIN (dB)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
0
–40
–20
–60
–80
02660-043
ADVANCED CONTROL MODES
The ADN2850 digital resistor includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
Key programming features include the following:
• Scratchpad programming to any desirable values
• Nonvolatile memory storage of the scratchpad RDAC
register value in the EEMEM register
•Increment and decrement instructions for the RDAC wiper
register
•Left and right bit shift of the RDAC wiper register to
achieve ±6 dB level changes
•26 extra bytes of user-addressable nonvolatile memory
Linear Increment and Decrement Instructions
The increment and decrement instructions (Instruction 14,
Instruction 15, Instruction 6, and Instruction 7) are useful for
linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
send just an increment or decrement command to the device.
The adjustment can be individual or in a ganged resistor
arrangement where both wiper positions are changed at the
same time.
For an increment command, executing Instruction 14
automatically moves the wiper to the next resistance segment
position. The master increment command, Instruction 15,
moves all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment
Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
an individual resistor or by a ganged resistor arrangement
where both wiper positions are changed at the same time. The 6
dB increment is activated by Instruction 12 and Instruction 13,
and the 6 dB decrement is activated by Instruction 4 and
Instruction 5. For example, starting with the wiper connected to
Terminal B, executing 11 increment instructions (Command
Instruction 12) moves the wiper in 6 dB steps from 0% of the R
(Terminal B) position to 100% of the R
position of the
BA
ADN2850 10-bit resistor. When the wiper position is near the
maximum setting, the last 6 dB increment instruction causes
the wiper to go to the full-scale 1023 code position. Further 6
dB per increment instructions do not change the wiper position
beyond its full scale (see Tabl e 9).
The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively. The
following information explains the nonideal ±6 dB step adjustment
under certain conditions. Table 9 illustrates the operation of the
shifting function on the RDAC register data bits. Each table row
represents a successive shift operation. Note that the left-shift
12 and 13 instructions were modified such that, if the data in
the RDAC register is equal to zero and the data is shifted left,
BA
the RDAC register is then set to Code 1. Similarly, if the data in
the RDAC register is greater than or equal to midscale and the data
is shifted left, then the data in the RDAC register is automatically
set to full scale. This makes the left-shift function as ideal a
logarithmic adjustment as possible.
The Right-Shift 4 instruction and Right-Shift 5 instruction are
ideal only if the LSB is 0 (ideal logarithmic = no error). If the
LSB is 1, the right-shift function generates a linear half-LSB
error, which translates to a number-of-bits dependent logarithmic
error, as shown in Figure 31. Figure 31 shows the error of the odd
numbers of bits for the ADN2850.
Table 9. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right-Shift 4 command and Right-Shift 5 command execution
contains an error only for odd numbers of bits. Even numbers of
bits are ideal.
Figure 31 shows plots of log error [20 × log10
(error/code)] for the ADN2850. For example, Code 3 log error =
20 × log
(0.5/3) = −15.56 dB, which is the worst case. The log
10
error plot is more significant at the lower codes (see Figure 31).
Figure 31. Log Error Conformance for Odd Numbers of Bits Only
(Even Numbers of Bits Are Ideal)
Rev. E | Page 17 of 28
ADN2850 Data Sheet
SW
(1)
SW
(0)
SW
B
B
R
S
R
S
SW(2
N
–
1)
W
SW(2
N
–
2)
RDAC
WIPER
REGISTER
AND
DECODER
R
S
= R
WB_NOMINAL
/2
N
R
S
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
02660-044
Using CS to Re-Execute a Previous Command
Another subtle feature of the ADN2850 is that a subsequent AA
CS
strobe, without clock and data, repeats a previous command.
Using Additional Internal Nonvolatile EEMEM
The ADN2850 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other components,
look-up tables, or system identification information. Table 10 provides an address map of the internal storage registers shown in the
functional block diagram (see Figure 1) as EEMEM1, EEMEM2,
and 26 bytes (13 addresses × 2 bytes each) of User EEMEM.
Table 10. EEMEM Address Map
EEMEM No. Address EEMEM Content for …
1
2
0000 RDAC11
0001 RDAC2
3 0010 USER12
4
0011 USER2
… … …
15
16 1111 R
1
RDAC data stored in EEMEM locations is transferred to the corresponding
RDAC register at power-on, or when Instruction 1, Instruction 8, and
executed.
2
USERx are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using Instruction 3 and
Instruction 9, respectively.
3
Read only.
1110 USER13
tolerance3
WB1
AA
PR
EE
AA are
Calculating Actual End-to-End Terminal Resistance
The resistance tolerance is stored in the EEMEM register during
factory testing. The actual end-to-end resistance can, therefore,
be calculated, which is valuable for calibration, tolerance matching,
and precision applications. Note that this value is read only and
the R
at full scale matches with R
WB2
at full scale, typically
WB1
0.1%.
The resistance tolerance in percentage is contained in the last
16 bits of data in EEMEM Register 15. The format is the sign
magnitude binary format with the MSB designate for sign
(0 = negative and 1 = positive), the next 7 MSB designate the
integer number, and the 8 LSB designate the decimal number
(see Table 12).
For example, if R
EE
AA
shows XXXX XXXX 1001 1100 0000 1111, R
be calculated as follows:
The RDAC contains multiple strings of equal resistor segments
with an array of analog switches that acts as the wiper
connection. The number of positions is the resolution of the device.
The ADN2850 has 1024 connection points, allowing it to provide
better than 0.1% setability resolution. Figure 32 shows an
equivalent structure of the connections among the three
terminals of the RDAC. The SW
switches, SW(0) to SW(2
the resistance position decoded from the data bits. Because the
switch is not ideal, there is a 30 Ω wiper resistance, R
resistance is a function of supply voltage and temperature. The
lower the supply voltage or the higher the temperature, the
higher the resulting wiper resistance. Users should be aware of
the wiper resistance dynamics, if accurate prediction of the
output resistance is needed.
Sign 26 25 24 23 22 21 20
7 Bits for Integer Number
Rev. E | Page 18 of 28
Device Resolution 25 kΩ 250 kΩ
1024-Step
24.4Ω 244Ω
.
2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8
Decimal
Point
8 Bits for Decimal Number
Data Sheet ADN2850
CODE (Decimal)
100
75
0
01023256
R
WB
(D) (% R
WF
)
512768
50
25
R
WB
02660-045
0
30
Zero scale (wiper contact resistor)
SDI
SDO
Action
PROGRAMMING THE VARIABLE RESISTOR
The nominal resistance of the RDAC between Terminal W and
Terminal B, R
1024 positions (10-bit resolution). The final digits of the part
number determine the nominal resistance value, for example,
25 kΩ = 24.4 Ω; 250 kΩ = 244 Ω.
The 10-bit data-word in the RDAC latch is decoded to select one of
the 1024 possible settings. The following description provides the
calculation of resistance, R
The first connection of the wiper starts at Terminal B for
Data 0x000. R
it is independent of the nominal resistance. The second connection
is the first tap point where R
for Data 0x001. The third connection is the next tap point
representing R
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at R
25006 Ω. See Figure 32 for a simplified diagram of the equivalent
RDAC circuit.
, is available with 25 kΩ and 250 kΩ with
WB
, at different codes of a 25 kΩ part.
WB
(0) is 30 Ω because of the wiper resistance, and
WB
(1) becomes 24.4 Ω + 30 Ω = 54.4 Ω
WB
(2) = 48.8 Ω + 30 Ω = 78.8 Ω for Data 0x002,
WB
(1023) =
WB
of 30 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal switches.
The typical distribution of R
from channel to channel is
WB_NOM
±0.2% within the same package. Device-to-device matching is
process lot dependent upon the worst case of ±30% variation.
However, the change in R
at full scale with temperature has a
WB
35 ppm/°C temperature coefficient.
PROGRAMMING EXAMPLES
The following programming examples illustrate a typical sequence
of events for various features of the ADN2850. See Table 8 for
the instructions and data-word format. The instruction numbers,
addresses, and data appearing at the SDI and SDO pins are in
hexadecimal format.
Table 14. Scratchpad Programming
SDI SDO Action
0xB00100
0xB10200
0xXXXXXX Writes Data 0x100 into RDAC1 register,
Wiper W1 moves to 1/4 full-scale
position.
0xB00100 Loads Data 0x200 into RDAC2 register,
Wiper W2 moves to 1/2 full-scale
position.
Table 15. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM
0xB00100 0xXXXXXX Writes Data 0x100 into RDAC1
register, Wiper W1 moves to 1/4 fullscale position.
0xE0XXXX
0xB00100 Increments RDAC1 register by one to
0x101.
0xE0XXXX
0xE0XXXX Increments RDAC1 register by one to
0x102. Continue until desired wiper
position is reached.
EEMEM1. Optionally, tie
EE
AA
AA to GND to
WP
protect EEMEM values.
EE
PR
AA
AA pin, or by the two commands shown in
Figure 33. R
(D) vs. Decimal Code
WB
The general equation that determines the programmed output
resistance between Terminal Bx and Terminal Wx is
)(
DR+×=
D
1024
_
(1)
RR
WNOMWBWB
0x20XXXX
0xXXXXXX Stores RDAC2 register data into
The EEMEM values for the RDACs can be restored by poweron, by strobing the
Table 16.
where:
Table 16. Restoring the EEMEM Values to RDAC Registers
SDI SDO Action
0x10XXXX
0xXXXXXX Restores the EEMEM1 value to the
RDAC1 register.
D is the decimal equivalent of the data contained in the RDAC
register.
R
is the nominal resistance value
WB_NOM
R
is the wiper resistance.
W
Table 13. R
(D) at Selected Codes for R
WB
= 25 kΩ
WB_NOM
D (Dec) RWB(D) (Ω) Output State
1023
25,006 Full scale
512 12,530 Midscale
1
54.4 1 LSB
Note that, in the zero-scale condition, a finite wiper resistance
Rev. E | Page 19 of 28
ADN2850 Data Sheet
Table 17. Using Left-Shift by One to Increment 6 dB Steps
SDI SDO Action
0xC0XXXX
0xC1XXXX
0xXXXXXX Moves Wiper 1 to double the
present data contained in the
RDAC1 register.
0xC0XXXX Moves Wiper 2 to double the
present data contained in the
RDAC2 register.
Table 19. Reading Back Data from Memory Locations
SDI SDO Action
0x92XXXX
0x00XXXX 0x92AAAA NOP Instruction 0 sends a 24-bit word
0xXXXXXX Prepares data read from USER1
EEMEM location.
out of SDO, where the last 16 bits
contain the contents in USER1 EEMEM
location.
Table 18. Storing Additional User Data in EEMEM
SDI SDO Action
0x32AAAA
0x335555
0xXXXXXX Stores Data 0xAAAA in the extra
EEMEM location USER1. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
0x32AAAA Stores Data 0x5555 in the extra
EEMEM location USER2. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
Table 20. Reading Back Wiper Settings
SDI SDO Action
0xB00200
0xC0XXXX 0xB00200 Doubles RDAC1 from midscale to full
0xA0XXXX 0xC0XXXX Prepares reading wiper setting from
0xXXXXXX 0xA003FF Reads back full-scale value from SDO.
0xXXXXXX Writes RDAC1 to midscale.
scale.
RDAC1 register.
EVAL-ADN2850SDZ EVALUATION KIT
Analog Devices, Inc., offers a user-friendly EVA LADN2850SDZ evaluation kit that can be controlled by a PC in
conjunction with the DSP platform. The driving program is
self-contained; no programming languages or skills are needed.
Rev. E | Page 20 of 28
Data Sheet ADN2850
U1
V
O
R2
250kΩ
V
I
R1
47kΩ
C1
11pF
W
B
C2
2.2pF
02660-047
B
V
I
AD8601
+2.5V
V
O
ADJUSTED
CONCURRENTLY
–2.5V
V+
V–
W
R
R2R1
B
W
R
C1
C2
U1
02660-055
C2C1R2R1
O
1
=ω
C2R2
1
C1R1
+
1
D1
D2
OP1177
V+
V–
+2.5V
+
–
–2.5V
V
O
U1
R2A
2.1kΩ
R2B
10kΩ
BA
W
R1
1kΩ
AMPLITUDE
ADJUSTMENT
R = R' = ADN2850
R2B = AD5231
D1 = D2 = 1N4148
R'
25kΩ
A
B
W
C'
VP
R
25kΩ
B
W
C
2.2nF
FREQUENCY
ADJUSTMENT
2.2nF
02660-056
APPLICATIONS INFORMATION
GAIN CONTROL COMPENSATION
A digital resistor is commonly used in gain control such as the
noninverting gain amplifier shown in Figure 34.
Figure 34. Typical Noninverting Gain Amplifier
When the RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a zero for the 1/β
term with 20 dB/dec, whereas a typical op amp gain bandwidth
product (GBP) has −20 dB/dec characteristics. A large R2 and
finite C1 can cause the frequency of this zero to fall well below
the crossover frequency. Therefore, the rate of closure becomes
40 dB/dec, and the system has a 0° phase margin at the crossover
frequency. If an input is a rectangular pulse or step function, the
output can ring or oscillate. Similarly, it is also likely to ring when
switching between two gain values; this is equivalent to a stop
change at the input.
Depending on the op amp GBP, reducing the feedback resistor
might extend the frequency of the zero far enough to overcome
the problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option because of the variation of R2. As a result, one can
use the previous relationship and scale C2 as if R2 were at its
maximum value. Doing this might overcompensate and
compromise the performance when R2 is set at low values.
Alternatively, it avoids the ringing or oscillation at the worst
case. For critical applications, find C2 empirically to suit the
oscillation. In general, C2 in the range of a few picofarads to no
more than a few tenths of picofarads is usually adequate for the
compensation.
Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.
PROGRAMMABLE LOW-PASS FILTER
In analog-to-digital conversions (ADCs), it is common to
include an antialiasing filter to band limit the sampling signal.
Therefore, the dual-channel ADN2850 can be used to construct
a second-order Sallen-Key low-pass filter, as shown in Figure 35.
The design equations are
O
First, users should select convenient values for the capacitors.
To achieve maximally flat bandwidth, where Q = 0.707, let C1
be twice the size of C2 and let R1 equal R2. As a result, the user
can adjust R1 and R2 concurrently to the same setting to
achieve the desirable bandwidth.
PROGRAMMABLE OSCILLATOR
In a classic Wien bridge oscillator, the Wien network (R||C, R'C')
provides positive feedback, whereas R1 and R2 provide negative
feedback (see Figure 36).
Rev. E | Page 21 of 28
Figure 35. Sallen-Key Low-Pass Filter
2
V
O
=
V
I
ω
f
ω
f
2
S
S
+
Q
(10)
2
ω+
f
(11)
Q =
Figure 36. Programmable Oscillator with Amplitude Control
(12)
ADN2850 Data Sheet
RC
O
1
=ω
RC
f
O
π=2
1
WNOMWBWB
RR
D
DR+×=
_
1024
)(
DDO
VIV+=R2B
3
2
CS
CLK
SDI
W1
B1
EEMEM
ADN2841
PSET
ERSET
IMODP
IBIAS
IMPD
DATAP
DATAN
CLKP
CLKN
CLKN
CLKP
DATAP
DATAN
W2
B2
EEMEM
CONTROL
ADN2850
V
CC
V
CC
RDAC1
RDAC2
02660-057
1
1
11
ln
S
C
TBE
I
I
VVV==
2
S
I
V
PD
REF
T
I
I
VVVln
12
=−
At the resonant frequency, fO, the overall phase shift is zero, and
the positive feedback causes the circuit to oscillate. With R = R
C = C
', and R2 = R2A /(R2B + R
), the oscillation frequency is
DIODE
',
or
where R is equal to R
WA
(13)
such that :
(14)
At resonance, setting R2/R1 = 2 balances the bridge. In practice,
R2/R1 should be set slightly larger than 2 to ensure that the
oscillation can start. On the other hand, the alternate turn-on
of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2,
momentarily stabilizing the oscillation.
When the frequency is set, the oscillation amplitude can be
turned by R2B because
(15)
V
, ID, and VD are interdependent variables. With proper
O
selection of R2B, an equilibrium is reached such that V
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.
In Figure 35 and Figure 36, the frequency tuning requires that
both RDACs be adjusted concurrently to the same settings.
Because the two channels might be adjusted one at a time, an
intermediate state occurs that might not be acceptable for some
applications. Of course, the increment/decrement instructions
(Instruction 5, Instruction 7, Instruction 13, and Instruction 15)
can all be used. Different devices can also be used in daisy-chain
mode so that parts can be programmed to the same settings
simultaneously.
OPTICAL TRANSMITTER CALIBRATION WITH
ADN2841
The ADN2850, together with the multirate 2.7 Gbps laser diode
driver, ADN2841, forms an optical supervisory system in which
the dual digital resistor can be used to set the laser average optical
power and extinction ratio (see Figure 37). The ADN2850 is
particularly suited for the optical parameter settings because of
its high resolution and superior temperature coefficient
characteristics.
Figure 37. Optical Supervisory System
The ADN2841 is a 2.7 Gbps laser diode driver that uses a
unique control algorithm to manage the average power and
extinction ratio of the laser after its initial factory calibration.
The ADN2841 stabilizes the data transmission of the laser by
continuously monitoring its optical power and correcting the
O
variations caused by temperature and the degradation of the
laser over time. In the ADN2841, the IMPD monitors the laser
diode current. Through its dual-loop power and extinction
ratio control calibrated by the dual RDACs of the ADN2850, the
internal driver controls the bias current, IBIAS, and consequently
the average power. It also regulates the modulation current,
IMODP, by changing the modulation current linearly with slope
efficiency. Therefore, any changes in the laser threshold current or
slope efficiency are compensated for. As a result, the optical
supervisory system minimizes the laser characterization efforts
and, therefore, enables designers to apply comparable lasers
from multiple sources.
INCOMING OPTICAL POWER MONITORING
The ADN2850 comes with a pair of matched diode connected
PNPs, Q1 and Q2, that can be used to configure an incoming
optical power monitoring function. With a reference current
source, an instrumentation amplifier, this feature can be used to
monitor the optical power by knowing the dc average photodiode
current from the following relationships:
(16)
VV
==
22
Knowing I
therefore α and I
= α1 × IPD, IC2 = α2 x I
C1
are matched. Combining Equation 16 and
S
Equation 17 theoretically yields:
Rev. E | Page 22 of 28
2
C
(17)
ln
TBE
I
, and Q1-Q2 are matched,
REF
(18)
Data Sheet ADN2850
where:
and IS2 are saturation current.
I
S1
V
, V2 are VBE, base-emitted voltages of the diode connector
1
transistors.
V
is the thermal voltage, which is equal to k × T/q
T
= 26 mV @ 25°C)
(V
T
k is the Boltzmann’s constant, 1.38e-23 Joules/Kelvin.
q is the electron charge, 1.6e-19 coulomb.
T is the temperature in Kelvin.
I
is the photodiode current.
PD
I
is the reference current.
REF
Figure 38 shows a conceptual circuit.
POST
AMP
CDR
VT COMPENSATION
°C
PRC
THERMISTOR
ADN2850
W
V
DD
LPF
TIA
Q
R
G
V
2
2
0.75 BIT RATE
AD623
IN AMP
(1 + 100k/RG)×(V1–V2)
10nF
I
PDIREF
W2V
1
1
Q
1
DATA
CLOCK
LOG
AVERAGE
POWER
0.30
0.25
0.20
(V)
1
0.15
–V
2
V
0.10
0.05
0
0.1µ1µ10µ100µ1m
Figure 39. V
DEVICE 1
DEVICE 2
DEVICE 3
CURVE FIT
IPD(A)
– V1 Error Versus Input Current.
2
I
T
REF
= 25°C
A
=1mA
ERROR
12
9
6
3
0
APPROXIMATING ERROR (%)
–3
–6
RESISTANCE SCALING
The ADN2850 offers 25 kΩ or 250 kΩ nominal resistance.
When users need lower resistance but must maintain the
number of adjustment steps, they can parallel multiple devices. For
example, Figure 40 shows a simple scheme of paralleling two
channels of RDACs. To adjust half the resistance linearly per
step, program both RDACs concurrently with the same settings.
02660-138
V
SS
B
B
1
2
GND
LOG AMP
–5V
Figure 38. Conceptual Incoming Optical Power Monitoring Circuit
The output voltage represents the average incoming optical
power. The output voltage of the log stage does not have to be
accurate from device to device, as the responsivity of the
photodiode will change between devices. An op amp stage is
shown after the log amp stage, which compensates for V
T
variation over temperature.
Equation 19 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V
and V1. A curve fit approximation
2
yields
VV
12
001.0
ln026.0
I
PD
03.0
(19)
The offset is caused by the transistors self-heating and the
thermal gradient effect. As seen in Figure 39, the error between
an approximation and the actual performance ranges is less
than 0% to –4% from 0.1 mA to 0.1 μA.
W1
02660-137
B1
B2
W2
02660-058
Figure 40. Reduce Resistance by Half with Linear Adjustment Characteristics
Figure 40 shows that the digital rheostat change steps linearly.
Alternatively, pseudo log taper adjustment is usually preferred in
applications such as audio control. Figure 41 shows another type
of resistance scaling. In this configuration, the smaller the R2
with respect to R
, the more the pseudo log taper characteristic
AB
of the circuit behaves.
W1
B1
R
02660-060
Figure 41. Resistor Scaling with Pseudo Log Adjustment Characteristics
The equation is approximated as
R
R
QUIVALENT
E
WB
WB
200,51
1024200,51
(17)
RR
Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the components.
Rev. E | Page 23 of 28
ADN2850 Data Sheet
AD8601
+
–
V
i
U1
V
O
C1
B
W
R2
R1*
*REPLACED WITH ANOTHER
CHANNEL OF RDAC
02660-061
RDAC
25kΩ
W
80pF
C
B
11pF
B
02660-063
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS
In operation, such as gain control, the tolerance mismatch
between the digital resistor and the discrete resistor can cause
repeatability issues among various systems (see Figure 42).
Because of the inherent matching of the silicon process, it is
practical to apply the dual-channel device in this type of
application. As such, R1 can be replaced by one of the channels
of the digital resistor and programmed to a specific value. R2 can
be used for the adjustable gain. Although it adds cost, this approach
minimizes the tolerance and temperature coefficient mismatch
between R1 and R2. This approach also tracks the resistance
drift over time. As a result, these less than ideal parameters
become less sensitive to system variations.
Figure 42. Linear Gain Control with Tracking Resistance Tolerance,
Drift, and Temperature Coefficient
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. A parasitic
simulation model is shown in Figure 43.
Figure 43. RDAC Circuit Simulation Model (RDAC = 25 kΩ)
The following code provides a macro model net list for the
25 kΩ RDAC:
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT ( W, B)
*
CW W 0 80E-12
RWB W B {D/1024 * RDAC + 50}
CB B 0 11E-12
*
.ENDS DPOT
Rev. E | Page 24 of 28
Data Sheet ADN2850
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGC
05-09-2012-A
1
0.80
BSC
PIN 1
INDICATOR
2.40 REF
0.75
0.60
0.50
TOP VIEW
12° MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
COPLANARITY
0.08
1.00
0.85
0.80
0.35
0.30
0.25
0.05 MAX
0.02 NOM
0.20 REF
3.25
3.10 SQ
2.95
16
5
13
8
9
12
4
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
4.75 BSC
SQ
EXPOSED
PAD
FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
0.25 MIN
BOTTOM VIEW
16
9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLI ANT TO JEDEC STANDARDS MO-153-AB
OUTLINE DIMENSIONS
Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 × 5 mm Body, Very Thin Quad
(CP-16-6)
Dimensions shown in millimeters
Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
1, 2
Model
ADN2850BRUZ25 25 −40°C to +85°C 16-Lead TSSOP RU-16
ADN2850BRUZ25-RL7 25 −40°C to +85°C 16-Lead TSSOP RU-16
ADN2850BCPZ25 25 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-6
ADN2850BCPZ25-RL7 25 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-6
ADN2850BCPZ250 250 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-6
ADN2850BCPZ250-RL7 250 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-6
EVAL-ADN2850SDZ Evaluation Board
1
Z = RoHS Compliant Part.
2
The evaluation board is shipped with the 25 kΩ RWB resistor option; however, the board is compatible with all available resistor value options.
RWB (kΩ) Temperature Range Package Description Package Option