ANALOG DEVICES ADN2850 Service Manual

1024-Position Digital Resistor

ADN2850

Rev. E

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ADDR

DECODE

ADN2850

RDAC1

SERIAL

INTERFACE

CS

CLK

SDI

SDO

PR

WP

RDY

RDAC1

REGISTER

EEMEM1

CURRENT
MONITOR

EEMEM2

26 BYTES

RTOL*

USER EEMEM

POWER-ON

RESET

W1
B1

RDAC2

W2
B2

V

DD

V

1

V

2

EEMEM

CONTROL

*R

WB

FULL SCALE TOLERANCE.

02660-001

V

SS

GND

RDAC1

REGISTER

I

1

I

2

Data Sheet

FEATURES

Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C

2.7 V to 5 V single supply or ±2.5 V dual supply
Current monitoring configurable function
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined

information
1M programming cycles
100-year typical data retention

APPLICATIONS

SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode

driver, optical supervisory systems
Mechanical rheostat replacement
Instrumentation gain adjustment
Programmable filters, delays, time constants
Sensor calibration

GENERAL DESCRIPTION

The ADN2850 is a dual-channel, nonvolatile memory1, digitally
controlled resistors
guaranteed maximum low resistor tolerance error of ±8%. The
device performs the same electronic adjustment function as a
mechanical rheostat with enhanced resolution, solid state
reliability, and superior low temperature coefficient
performance. The versatile programming of the ADN2850 via
an SPI®-compatible serial interface allows 16 modes of
operation and adjustment including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up table, or system identification
information.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital resistor and RDAC are used interchangeably.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

2

with 1024-step resolution, offering

Nonvolatile Memory, Dual

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC

2

register, which sets the
resistance between Terminal W and Terminal B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.

The EEMEM content can be restored dynamically or through
external

EE

PR

AA strobing, and a AA

EE

WP

AA function protects EEMEM

contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.

The ADN2850 patterned resistance tolerance is stored in the
EEMEM. The actual full scale resistance can, therefore, be
known by the host processor in readback mode. The host can

1

execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.

The ADN2850 is available in the 5 mm × 5 mm 16-lead frame
chip scale LFCSP and thin, 16-lead TSSOP package. The part is
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

ADN2850 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—25 kΩ, 250 kΩ Vers io n s ............... 3

Interface Timing and EEMEM Reliability Characteristics—

25 kΩ, 250 kΩ Versions ............................................................... 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Test Circuits ................................................................................. 12

Theory of Operation ...................................................................... 13

Scratchpad and EEMEM Programming .................................. 13

Basic Operation .......................................................................... 13

EEMEM Protection .................................................................... 14

Digital Input and Output Configuration................................. 14

Serial Data Interface ................................................................... 14

Daisy-Chain Operation ............................................................. 14

Terminal Voltage Operating Range ......................................... 15

Advanced Control Modes ......................................................... 17

RDAC Structure.......................................................................... 18

Programming the Variable Resistor ......................................... 19

Programming Examples ............................................................ 19

EVA L-ADN2850SDZ Evaluation Kit ....................................... 20

Applications Information .............................................................. 21

Gain Control Compensation .................................................... 21

Programmable Low-Pass Filter ................................................ 21

Programmable Oscillator .......................................................... 21

Optical Transmitter Calibration with ADN2841 ................... 22

Incoming Optical Power Monitoring ...................................... 22

Resistance Scaling ...................................................................... 23

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations ......................................................... 24

RDAC Circuit Simulation Model ............................................. 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

6/12—Rev. D to Rev. E

Changes to Table 1 Conditions ....................................................... 4

Removed Positive Supply Current RDY and/or SDO Floating
Parameters and Negative Supply Current RDY and/or SDO

Floating Parameters, Table 1 ........................................................... 4

Updated Outline Dimensions ....................................................... 25

Added Endnote 2 to Ordering Guide .......................................... 25

4/11—Rev. C to Rev. D

Changes to Figure 10 ...................................................................... 10

4/11—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to EEMEM Performance ................................... Universal

Changes to Features Section............................................................ 1

Changes to Applications Section .................................................... 1

Changes to General Description Section ...................................... 1

Changes to Figure 1 .......................................................................... 1

Changes to Specifications Section .................................................. 3

Changes to Table 2 ............................................................................ 5

Changes to Absolute Maximum Ratings Section ......................... 7

Changes to Pin Configuration and Function Descriptions

Section ................................................................................................ 8

Changes to Typical Performance Characteristics Section ........ 10

Added Figure 15, Figure 16, Figure 17 ........................................ 11

Changes to Figure 21 ...................................................................... 12

Changes to Theory of Operation Section.................................... 13

Changes to Figure 25 ...................................................................... 14

Changes to Programming Variable Resister Section ................. 19

Changes to Table 13 ....................................................................... 19

Changes to EVAL-ADN2850EBZ Evaluation Kit Section ........ 20

Added Gain Control Compensation Section.............................. 21

Added Programmable Low-Pass Filter Section .......................... 21

Added Programmable Oscillator Section .................................... 21

Added Resistance Tolerance, Drift, and Temperature Coeffcient

Mistmatch Considerations Section .............................................. 24

Changes to Outline Dimensions Section .................................... 25

Changes to Ordering Guide .......................................................... 25

9/02—Rev. A to Rev. B

Changes to General Description ..................................................... 1

Changes to Electrical Characteristics ............................................. 2

Changes to Calculating Actual Full-Scale Resistance Section ..... 9

Changes to Table VI .......................................................................... 9

Updated Outline Dimensions ....................................................... 18

Rev. E | Page 2 of 28

Data Sheet ADN2850

Capacitance Wx3

CW

f = 1 MHz, measured to GND,

80 pF
DIGITAL INPUTS AND OUTPUTS

Dual-Supply Power Range

VDD/VSS

±2.25

±2.75

V

Power Dissipation6

P

VIH = VDD or VIL = GND

10

30

µW

Power Supply Sensitivity3

PSS

∆VDD = 5 V ± 10%

0.006

0.01

%/%

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted. These
specifications apply to versions with a date code 1209 or later.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT

MODE (All RDACs)
Resolution N 10
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB
Nominal Resistor Tolerance ∆RWB/RWB Code = full scale −8 +8 %
Resistance Temperature Coefficient3 (∆RWB/RWB)/

Wiper Resistance RW Code = half scale
VDD = 5 V 30 60 Ω

VDD = 3 V 50 Ω

Nominal Resistance Match3 R

RESISTOR TERMINALS

Terminal Voltage Range3 VB, VW VSS VDD V
Capacitance Bx3 CB f = 1 MHz, measured to GND,

6

∆T × 10

Code = full scale ±0.1 %

WB1/RWB2

Code = full scale 35 ppm/°C

11 pF

code = half-scale

Common-Mode Leakage Current

3, 4

ICM VW = VDD/2 0.01 ±1 µA

Input Logic 3

High VIH VDD = 5 V 2.4 V
VDD = 2.7 V 2.1 V
VDD = +2.5 V, VSS = −2.5 V 2.0 V
Low VIL VDD = 5 V 0.8 V
VDD = 2.7 V 0.6 V

VDD = +2.5 V, VSS = −2.5 V 0.5 V

code = half-scale

Output Logic High (SDO, RDY) VOH R
Output Logic Low VOL IOL = 1.6 mA, V

= 2.2 kΩ to 5 V (see Figure 25) 4.9 V

PULL-UP

= 5 V (see Figure 25) 0.4 V

LOGIC

Input Current IIL VIN = 0 V or VDD ±1 µA
Input Capacitance3 CIL 5 pF

POWER SUPPLIES

Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V

Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA
Negative Supply Current ISS VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND −4 −2 µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,

= GND, ISS ≈ 0

V

SS

2 mA

ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current5 IDD (restore) VIH = VDD or VIL = GND,

V

= GND, ISS ≈ 0

SS

320 µA

ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA

DISS

Rev. E | Page 3 of 28

ADN2850 Data Sheet

Parameter Symbol Conditions Min Typ1 Max Unit

CURRENT MONITOR TERMINALS

Current Sink at V1 I1 0.0001 10 mA
Current Sink at V2 I2 0.0001 10 mA

DYNAMIC CHARACTERISTICS

Resistor Noise Density e

RWB = 25 kΩ/250 kΩ, TA = 25°C 20/64

Analog Crosstalk CT VBX = GND, Measured VW1 with VW2 =

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum current in each code is defined by I
(see Figure 20).

3

Guaranteed by design and not subject to production test.

4

Common-mode leakage current is a measure of the dc leakage from any Terminal B, or Terminal W to a common-mode bias level of VDD/2.

5

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.

6

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

7

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

3, 7

Code= full scale

N_WB

−95/−80

1 V

, f = 1 kHz, Code 1 = midscale,

RMS

Code 2 = midscale,

= 25 kΩ/250 kΩ

R

WB

WB = (VDD − 1)/RWB.

nV/√Hz
dB

Rev. E | Page 4 of 28

Data Sheet ADN2850

Input Clock Pulse Width

t4, t5

Clock level high or low

10

ns

CLK to SDO Propagation Delay

t10

RP = 2.2 kΩ, CL < 20 pF

50

ns

CLK to SDO Data Hold Time

t11

RP = 2.2 kΩ, CL < 20 pF

0

ns

Read EEMEM Time4

t16

Applies to instructions 0x8, 0x9, 0x10

7 30

µs

Data Retention

100 Years

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V

= 3 V and VDD = 5 V.

DD

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t

EE

AA Setup Time

CS
CLK Shutdown Time to AA

) t1 20 ns

CYC

EE

AA Rise t

CS

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

EE

AA

AA to SDO-SPI Line Acquire t

CS

EE

AA

AA to SDO-SPI Line Release t

CS

= tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are

R

t2 10 ns

1 t

3

40 ns

8

50 ns

2

10F

9

CYC

EE

AA

AA High Pulse Width11F

CS

AA

EE AAHigh to AA

CS
RDY Rise to AA

EE

AA

AA Rise to RDY Fall Time t

CS

CS

CS

Store EEMEM Time

EE

AA

AA Rise to Clock Rise/Fall Setup t

CS
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY

Endurance

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;

CMD_2, CMD_3 ~ 15 ms,

5

Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.

6

Not shown in Figure 2 and Figure 3.

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.

8

Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

3

t12

EE

3

AA High

t13 4 t

EE

AA Fall t

4,

5

12F

13F

t16 Applies to instructions 0x2, 0x3 15 50 ms

6

14F

t

6

6

t

0 ns

14

0.15 0.3 ms

15

10 ns

17

50 ns

PRW

t

PRESP

EEMEM

AA

EE

pulsed low to refresh wiper positions

AA

PR

10 ns

30 µs

30 µs

7

15F

TA = 25°C 1

100

8

16F

, and CL.

PULL-UP

PR

hardware pulse ~ 30 µs.

derates with junction temperature in the Flash/EE memory.

CYC

MCycles
kCycles

Rev. E | Page 5 of 28

ADN2850 Data Sheet

CPOL = 1

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

t

8

B24*

B23 (MSB) B0 (LSB)

B23 (MSB)

HIGH
OR LOW

HIGH
OR LOW

B23 B0

B0 (LSB)

RDY

CPHA = 1

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLYTHE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATATO THE POSITIVE EDGE OF THE CLOCK.

SDO

SDI

CS

02660-002

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

CPOL = 0

t

8

B23 (MSB OUT) B0 (LSB)

SDO

B23 (MSB IN)

B23 B0

HIGH
OR LOW

HIGH
OR LOW

B0 (LSB)

SDI

RDY

CPHA = 0

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

*

CS

02660-003

Timing Diagrams

Figure 2. CPHA = 1 Timing Diagram

Figure 3. CPHA = 0 Timing Diagram

Rev. E | Page 6 of 28

Data Sheet ADN2850

Vapor Phase (60 sec)

215°C

Junction-to-Case θJC, TSSOP-16

28°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V

to VSS 7 V

V

DD

VB, VW to GND VSS − 0.3 V to VDD + 0.3 V

, IW

I

B

Pulsed0F0F1 ±20 mA
Continuous

±2 mA

Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V

2

1F1F

Operating Temperature Range

−40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range

−65°C to +150°C

Lead Temperature, Soldering

Infrared (15 sec) 220°C

Thermal Resistance

Junction-to-Ambient θJA,TSSOP-16 150°C/W
Junction-to-Ambient θ

,LFSCP-16 35°C/W

JA

Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 7 of 28

ADN2850 Data Sheet

SDI
SDO
GND

V1

V

SS

W1

CLK

B1

CS
PR
WP
V

DD

V2
W2
B2

RDY

1

2

3

4

5

6

7

8

16

15

14

13
12

11

10

9

ADN2850

TOP VIEW

(Not to Scale)

02660-005

Pin No.

Mnemonic

Description

2

SDI

Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.

7

W1

Wiper Terminal of RDAC1. ADDR (RDAC1) = 0x0.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.

3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO

output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up

resistor in the range of 1 kΩ to 10 kΩ is needed.
4 GND Ground Pin, Logic Ground Reference.
5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink

2 mA for 15 ms when storing data to EEMEM.
6 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor.

8 B1 Terminal B of RDAC1.
9
10

B2 Terminal B of RDAC2.

W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
12
13

14 AA

15 AA
16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

VDD Positive Power Supply.

EE

AA

Optional Write Protect. When active low, AA

WP

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie AA

EE

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

PR

register. Factory default loads midscale 512
at the logic high transition. Tie AA

EE

Serial Register Chip Select Active Low. Serial register operation takes place when AA

CS

Instruction 9, Instruction 10, and

PR

EE

AA to V

AA

PR

EE

AA.

EE

AA

prevents any changes to the present contents, except AA

WP

until EEMEM is loaded with a new value by the user. AA

10

, if not used.

DD

WP

EE

AA to V

, if not used.

DD

CS

EE

AA returns to logic high.

PR

PR

EE

AA

strobe.

EE

AA is activated

Rev. E | Page 8 of 28

Data Sheet ADN2850

A

DN2850

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

SS

1

SDI
16

1SDO
2GND

(EXPOSED

3V
4V

5
1

W

CLK
15

PAD)

6
B1

CS

RDY
14

13

12 PR
11 WP
10 V

DD

9V

2

8

7

2

B2

W

02660-105

NOTES

1. THE EXPOSED PAD IS LEFT FLOATING

SS

OR IS TIED TO V

.

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 SDO

Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up

resistor in the range of 1 kΩ to 10 kΩ is needed.
2 GND Ground Pin, Logic Ground Reference.
3 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual supply, it must be able to sink

SS

2 mA for 15 ms when storing data to EEMEM.
4 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
5 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
6 B1 Terminal B of RDAC1.
7 B2 Terminal B of RDAC2.
8 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
9 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
10 VDD Positive Power Supply.
11

12

13

E

AWP

Optional Write Protect. When active low, AWP

E

APR

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

E

ACS

Serial Register Chip Select Active Low. Serial register operation takes place when ACS

14 RDY

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie

register. Factory default loads midscale until EEMEM is loaded with a new value by the user.

at the logic high transition. Tie

Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

Instruction 9, Instruction 10, and

E

A

APR

to VDD, if not used.

E

A

APR

.

E

A

prevents any changes to the present contents, except APR

E

A

AWP

to VDD, if not used.

E

A

returns to logic high.

15 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
16 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
EP Exposed Pad. The exposed pad is left floating or is tied to VSS.

E

A

APR

is activated

E

A

strobe.

Rev. E | Page 9 of 28