Analog Devices ADN2849 prg Datasheet

10.7 Gbps Electro-Absorption Modulator Driver

Preliminary Technical Data

FEATURES

Data Rates up to 10.709Gb/s
Typical Rise/Fall Time 27ps
Power Dissipation 900mW (at 2V swing, 1V offset)
Programmable Modulation Voltage up to 3V
Programmable Bias Offset Voltage up to 2V
Voltage-input control for offset, modulation
Cross Point Adjust Range 30%- 85%
Selectable Data Retiming
PECL/CML Data & Clock Inputs

50Ω on Chip Data & Clock Terminations
Modulation Ebnable/Disable

|<-10dB , |S22|<-8dB at 10GHz

|S

11

Positive or negative 5.2 or 5.0V single supply operation
Available in dice and 4x4mm 24 Lead LFCSP package

APPLICATIONS

SONET OC-192 Optical Transmitters
SDH STM-64 Optical Transmitters
10Gb Ethernet IEEE802.3
XFP/X2/XENPACK/MSA-300 Optical Modules

PRODUCT DESCRIPTION

The ADN2849 is a low power 10.7Gbps driver for electro­absorption modulator (EAM) applications. The modulation
voltage is programmable via an external voltage up to a
maximum swing of 3V when driving 50Ω. The bias offset
voltage and output eye cross point are also programmable. On­chip 50Ω resistor is provided for back termination of the
output. The ADN2849 is driven by AC coupled differential
CML level data and has selectable data retiming to remove jitter
from data input signal. The modulation voltage can be enabled
or disabled by driving the MOD_ENB pin with the proper logic
levels. It can operate with positive or negative (5.2V or 5.0V)
supply voltage.
The ADN284949 is available in a compact 4x4mm plastic
package or dice format.

CPAP CPAN MOD_SET

BIAS_SET VTERM

GND MODN_TERM

ADN2849

ADN2849

DATAP

DAT AN

VBB

CLKP

CLKN

Rev. Pr. G August 2004

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

50

Ω

50

Ω

MUX

D

Q

50

Ω

50

Ω

VEE

CLK_SELB MOD_ENB

CROSS

POINT

ADJUST

Figure 1. Functional Block Diagram

GND

R
R

50

Ω

VEE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

MODP

ADN2849

Preliminary Technical Data

Specifications

(Electrical Specifications (VEE=VEE

0

specified at 25

Table 1.

C)

MIN

to VEE

. All specifications T

MAX

min

to T

, ZL=50Ω unless otherwise noted. Typical values

max

Parameter Min Typ Max Unit Conditions
Bias Offset Voltage(MODP)

Bias offset voltage -0.25 -2.0 V Note 1
BIAS_SET voltage to bias offset voltage gain 0.9 1.1 V/V Ta=250C, VEE=-5.2V
Bias offset voltage drift over temperature and VEE -5 5 %

Modulation Voltage(MODP)

Modulation voltage swing 0.6 3.0 V Note1
MOD_SET voltage to modulation voltage swing gain 1.5 1.9 V/v Ta=250C, VEE=-5.2V
Modulation voltage drift over temperature and VEE -5 5 %
Back termination resistance 40 60

Ω

Rise time (20% - 80%) 27 36 ps
Fall time (20% - 80%) 27 36 ps
Random jitter 0.75 ps RMS
Total jitter 10 ps

p-p

Cross point adjust range 30 85 %
Cross point drift over temperature and VEE -5 5 %
Minimum output voltage(single ended) VEE+1.7 V Note1
|S22|

-8 dB At 10GHz
Modulation enable time 100 ns
Modulation disable time 100 ns

Data Inputs (DATAP, DATAN)

Differential Input voltage 600 1600 mV
Termination resistance 40 60

p-p

Ω

Setup time (see figure 2) 25 ps CLK_SELB=’0’
Hold time (see figure 2) 25 ps CLK_SELB=’0’
|S11| -10 DB At 10GHz

Clock Inputs (CLKP, CLKN)

Differential Input voltage 600 1600 mV
Termination resistance 40 60

p-p

Ω

|S11| -10 dB At 10GHz

Cross point adjust (CPAN, CPAP)

Input voltage range -0.85 -1.85 V
CPAP, CPAN differential voltage 0.6 V
Input current 85 115

Logic Inputs (MOD_ENB, CLK_SELB)

V

IH

V

IL

I

IL

I

IH

VEE+2 V
VEE+0.8 V

-400

20

200

Supply

p-p

µA

µA
µA
µA

VI=VEE+0.4V
VI=VEE+2.4V
VI=0V

VEE -4.75 -5.2 -5.5 V IMOD=0
I

EE

Notes:
Minimum supply voltage and minimum output voltage determine maximum output swing and maximum bias offset that can be achieved concurrently.
Measured using the characterization circuit shown in figure 3.

52 mA V

MODP/MODN

=0

Rev. Pr. G | Page 2 of 17

Preliminary Technical Data

ADN2849

SETUP HOLD

t

S

t

H

DATAP/N

CLKP/N

Figure 2. Setup and hold time

Figure 3. High-speed characterization circuit

Rev. Pr. G | Page 3 of 17

ADN2849

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Min Max Units Conditions

VEE to GND TBD TBD V
VBB to GND TBD TBD V
DATAP, DATAN to GND TBD TBD V
CLKP, CLKN to GND TBD TBD V
CPAP, CPAN to GND TBD TBD V
MOD_SET to GND TBD TBD V
BIAS_SET to GND TBD TBD V
MOD_ENB to GND TBD TBD V
CLK_SELB to GND TBD TBD V
Staorage temperature range -60 +150 0C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

PACKAGE THERMAL SPECIFICATIONS

Table 3.
PARAMETER MIN TYP MAX UNITS CONDITIONS/COMMENTS

θ

θ

J-TOP

J-PAD

TBD TBD TBD 0C/W Thermal resistance from junction to top of package

TBD TBD TBD 0C/W

Thermal resistance from junction to bottom of exposed pad

ORDERING GUIDE

Table 4.
Model Temperature range Package description

ADN2849ACP -400C to +850C 24 Lead LFCSP
ADN2849ACP-RL -400C to +850C 24 Lead LFCSP
ADN2849ACP-RL7 -400C to +850C 24 Lead LFCSP
ADN2849SURF -400C to +850C Bare die

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Rev. Pr. G | Page 4 of 17

Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS (TA=250C, VEE=-5.2V)

000

000

ADN2849

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 4. Rise time vs. Swing

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

TBD

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 7. Total jitter vs. Swing

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

TBD

000

000 000 000 000 000 000

ALL CAPS (Initial cap)

Figure 5. Fall time vs. Swing

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 6. Random jitter vs. Swing

000

000 000 000 000 000 000

ALL CAPS (Initial cap)

Figure 8. Cross point vs. differential voltage at CPAP/CPAN pins

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

Figure 9. Differential S11 vs. frequency

TBD

ALL CAPS (Initial cap)

Rev. Pr. G | Page 5 of 17

ADN2849

Preliminary Technical Data

000

000

000

)
p

a

c
l

000

a

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 10. Single-ended S22 vs. frequency

000

000

)
p

a

c
l

000

a

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

TBD

000

)
p

a

c
l

000

a

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 00 0 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 13. Electrical eye diagram

(2.5V swing, 0.5V offset, PRBS31 at 10.7Gbps)

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

TBD

000

000 000 000 000 000 000

ALL CAPS (Initial cap)

Figure 21. Total supply current vs. Swing with retiming disabled

000

000

)
p

a

c
l

a

000

i

t

i
n

I

(
S

P
A

000

C
L

L
A

000

000

000 000 000 000 000 000

TBD

ALL CAPS (Initial cap)

Figure 12. Total supply current vs. Swing with retiming enabled

000

000 000 000 000 000 000

Figure 14. Optical eye diagram using the FLD5F20NP EML

ALL CAPS (Initial cap)

(Pav=0dBm, ER=10dB, PRBS31 pattern at 9.95328Gbps, SONET

OC192 mask test)

Rev. Pr. G | Page 6 of 17