Analog Devices ADN2847 Datasheet

3V Dual-Loop 50 Mbps to 3.3 Gbps

a

FEATURES
50 Mbps to 3.3 Gbps Operation
Single 3.3 V Operation
Typical Rise/Fall Time 80 ps
Bias Current Range 2 mA to 100 mA
Modulation Current Range 5 mA to 80 mA
Monitor Photodiode Current 50 A to 1200 A
Dual MPD Functionality for DWDM
50 mA Supply Current at 3.3 V
Closed-Loop Control of Power and Extinction Ratio
Full Current Parameter Monitoring
Laser Fail and Laser Degrade Alarms
Automatic Laser Shutdown, ALS
Optional Clocked Data
Supports FEC Rates
48-Lead (7 mm  7 mm) LFCSP Package
32-Lead (5 mm  5 mm) LFCSP Package
Available in Die Form

Laser Diode Driver

ADN2847

APPLICATIONS
SONET OC-1/3/12/48
SDH STM-0/1/4/16
Fibre Channel
Gigabit Ethernet
DWDM Dual MPD Wavelength Control

GENERAL DESCRIPTION

The ADN2847 uses a unique control algorithm to control both
average power and extinction ratio of the laser diode, LD, after
initial factory setup. External component count and PCB area are
low as both power and extinction ratio control are fully integrated.
Programmable alarms are provided for laser fail (end of life) and
laser degrade (impending fail).

Optional dual MPD current monitoring is designed into the
ADN2847 specifically for DWDM wavelength control.

MPD

GND

GND

GND

V

CC

IMPD

IMPD2

PSET

ERSET

FUNCTIONAL BLOCK DIAGRAM

V

IBMON

IMMON

IMPDMON

IMPDMON2

ALS

FAIL

DEGRADE

I

MOD

CONTROL

I

BIAS

PAV CAPERCAP

GNDGND

CC

IMODN

CLKSEL

ADN2847

LBWSETIDTONE

CC

V

GND

IMODP

I

BIAS

ASET

GND

DATAP

DATAN

CLKP

CLKN

V

CC

LD

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADN2847

–SPECIFICATIONS

(VCC = 3.0 V to 3.6 V. All specifications T
otherwise noted.1 Typical values as specified at 25C.)

MIN

to T

, unless

MAX

Parameter Min Typ Max Unit Conditions/Comments

LASER BIAS (BIAS)

Output Current I

BIAS

Compliance Voltage 1.2 V

during ALS 0.1 mA

I

BIAS

ALS Response Time 5 µsI
CCBIAS Compliance Voltage 1.2 V

MODULATION CURRENT (IMODP, IMODN)

Output Current I

MOD

Compliance Voltage 1.5 V

during ALS 0.1 mA

I

MOD

Rise Time (See Figure 4 for Typical Distribution)
Fall Time (See Figure 5 for Typical Distribution)
Random Jitter
Pulsewidth Distortion

3

3

2 100 mA

CC

CC

2

V

V

580mA

CC

3

3

80 120 ps
80 120 ps

V

1 1.5 ps RMS
15 ps I

< 10% of nominal

BIAS

= 40 mA

MOD

MONITOR PD (MPD, MPD2)

Current 50 1200 µAAverage Current
Compliance Voltage 1.65 V

POWER SET INPUT (PSET)

Capacitance 80 pF
Monitor Photodiode Current into RPSET Resistor 50 1200 µAAverage Current
Voltage 1.1 1.2 1.3 V

EXTINCTION RATIO SET INPUT (ERSET)

Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V

ALARM SET (ASET)

Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
Hysteresis 5 %

CONTROL LOOP Low Loop Bandwidth Selection

Time Constant 0.22 s LBWSET

2.25 s LBWSET = V

DATA INPUTS (DATAP, DATAN, CLKP, CLKN)

4

= GND

CC

V p-p (Single-Ended, Peak-to-Peak) 100 500 mV Data and Clock Inputs Are
Input Impedance (Single-Ended) 50 Ω AC-Coupled

5

(See Figure 1) 50 ps

t

SETUP

5

t

(See Figure 1) 100 ps

HOLD

LOGIC INPUTS (ALS, LBWSET, CLKSEL)

V

IH

V

IL

2.4 V

0.8 V

ALARM OUTPUTS (Internal 30 kΩ Pull-Up)

V

OH

V

OL

2.4 V

0.8 V

IDTONE

Compliance Voltage V





I

OUT




f

Ratio



I



IN

6

IN

0.01 1 MHz

–1.5 V

CC

2

User to Supply Current Sink
in the Range of 50 µA to 4 mA

IBMON, IMMON, IMPDMON, IMPDMON2

IBMON, IMMON Division Ratio 100 A/A
IMPDMON, IMPDMON2 1 A/A
IMPDMON to IMPDMON2 Matching 2 % I
Compliance Voltage 0 V

–1.2 V

CC

= 1200 µA

MPD

REV. 0–2–

ADN2847

Parameter Min Typ Max Unit Conditions/Comments

SUPPLY

7

I

CC

8

V

CC

NOTES

1

Temperature range: –40∞C to +85∞C.

2

The high speed performance for the die version of ADN2847 can be achieved when using the bonding diagram shown in Figure 3.

3

Measured into a 25 W load using a 11110000 pattern at 2.5 Gbps.

4

When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.

5

Guaranteed by design and characterization. Not production tested.

6

IDTONE may cause eye distortion.

7

I

for power calculation on page 8 is the typical ICC given.

CCMIN

8

All VCC pins should be shorted together.

Specifications subject to change without notice.

3.0 3.3 3.6 V

50 mA I

BIAS

= I

MOD

= 0

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

1

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V

Digital Inputs (ALS, LBWSET, CLKSEL) . . –0.3 V to V

IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . V

+ 0.3 V

CC

+ 1.2 V

CC

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . .–40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature (T
48-Lead LFCSP Package

Power Dissipation

q

Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 25∞C/W

JA

max) . . . . . . . . . . . . . . . . . . . 150∞C

J

2

. . . . . . . . . . . . . . . . (TJ max – TA)/qJA W

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . 300∞C

32-Lead LFCSP Package

Power Dissipation

q

Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 32∞C/W

JA

2

. . . . . . . . . . . . . . . . (TJ max – TA)/qJA W

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . 300∞C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Power consumption formulae are provided on page 8.

3

q

is defined when part is soldered on a 4-layer board.

JA

ORDERING GUIDE

Temperature Package

Model Range Description

ADN2847ACP-32 –40∞C to +85∞C 32-Lead LFCSP
ADN2847ACP-48 –40∞C to +85∞C 48-Lead LFCSP
ADN2847ACP-32-RL –40∞C to +85∞C 32-Lead LFCSP
ADN2847ACP-32-RL7 –40∞C to +85∞C 32-Lead LFCSP
ADN2847ACP-48-RL –40∞C to +85∞C 48-Lead LFCSP

HOLD

t

H

DATAP/DATAN

CLKP

SETUP

t

S

Figure 1. Setup and Hold Time

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN2847 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADN2847

2280m

2620m

3 GNDCLKSEL

GND2

GND2

GND2

2

V

CC

IMODN

IMODN

GND2

IMODP
IMODP

GND2

GND2

I

BIAS

I

BIAS

CCBIAS

GND GND4

LBWSET

ASET

IBMON

ERSET

IMMON

PSET

GND

V

CC

IMPD

FAIL

ALS

IMPDMON2

Figure 2. Metallization Photograph

2280m

DEGRADEIDTONE

GNDGND3

GND

VCC4IMPD2IMPDMON

CLKN

CLKP

GND1

DATAP

DATAN

GND1

V

1

CC

GND

PAVCAP

ERCAP

DIE ROTATED 90 IN PACKAGE

1

BOTTOM

LEFT RIGHT

TOP

2620m

Figure 3. Bonding Diagram

DIE PAD COORDINATES*

Pad Number Pad Name x[m] Y[m]

1 TP1 (GND) –996 1026
2 LBWSET –996 853
3 ASET –996 679
4 ERSET –996 506
5 PSET –996 332

6 TP2 (GND) –996 159
7 IMPD –996 –15

8IMPDMON –996 506
9 IMPDMON2 –996 –361
10 IMPD2 –996 –534
11 GND4 –996 –724
12 V

4 –995 –964

CC

13 ERCAP –925 –1191
14 PAVCAP –777 –1191
15 TP3 (GND) –606 –1191
16 V

1 –389 –1191

CC

17 GND1 –200 –1191
18 DATAN –70 –1191
19 DATAP 83 –1191
20 GND1 263 –1191
21 CLKP 442 –1191
22 CLKN 596 –1191
23 TP4 (GND) 762 –1191
24 TP5 (GND) 996 –1109
25 TP6 (GND) 996 –935
26 CLKSEL 996 –762
27 DEGRADE 996 –589
28 FAIL 996 –415
29 ALS 996 –242

Pad Number Pad Name x[m] Y[m]

30 V

3 996 –19

CC

31 GND3 996 251
32 IMMON 996 441
33 IBMON 996 614
34 GND2 996 804
35 IDTONE 995 993
36 GND2 995 1133
37 GND2 867 1191
38 V

2 713 1191

CC

39 IMODN 500 1191
40 IMODN 396 1191
41 GND2 242 1191
42 IMODP 88 1191
43 IMODP –16 1191
44 GND2 –239 1191
45 GND2 –443 1191
46 I
47 I

BIAS

BIAS

–633 1191
–772 1191

48 CCBIAS –912 1191

*With the origin in the center of the die (see Figure 2).

REV. 0–4–

48-Lead LFCSP

ADN2847

PIN CONFIGURATION

32-Lead LFCSP

29 GND2

28 IMODP

27 GND2

GND1 14

DATAP 13

DATAN 12

2

CC

26 IMODN

25 V

24 IBMON
23 IMMON
22 GND3
21 V
20 ALS
19 FAIL
18 DEGRADE
17 CLKSEL

CLKP 15

CLKN 16

3

CC

TP1 1

LBWSET 2

ASET 3

ERSET 4

PSET 5

TP2 6

IMPD 7

IMPDMON 8

IMPDMON2 9

IMPD2 10

GND4 11

4 12

V

CC

BIAS

BIAS

48 CCBIAS

47 I

46 I

45 GND2

PIN 1
INDICATOR

ADN2847

TOP VIEW

1 16

CC

TP3 15

V

ERCAP 13

PAVCAP 14

44 GND2

43 IMODP

42 IMODP

GND1 17

DATAP 19

DATAN 18

41 GND2

40 IMODN

39 IMODN

CLKP 21

CLKN 22

GND1 20

2

CC

37 GND2

38 V

TP5 24

TP4 23

36 GND2
35 IDTONE
34 GND2
33 IBMON
32 IMMON
31 GND3

3

30 V

CC

29 ALS
28 FAIL
27 DEGRADE
26 CLKSEL
25 TP6

LBWSET 1

ASET 2

ERSET 3

PSET 4
IMPD 5

IMPDMON 6

GND4 7

4 8

V

CC

BIAS

32 CCBIAS

31 I

30 GND2

PIN 1
INDICATOR

ADN2847

TOP VIEW

1 11

CC

V

ERCAP 9

PAVCAP 10

PIN FUNCTION DESCRIPTIONS

Pin Number
48-Lead 32-Lead Mnemonic Function

1 TP1 Test Pin. In normal operation, TP1 = GND.
21 LBWSET Select Low Loop Bandwidth
32 ASET Alarm Current Threshold Setting Pin
43 ERSET Extinction Ratio Set Pin
54 PSET Average Optical Power Set Pin
6 TP2 Test Pin. In normal operation, TP2 = GND.
75 IMPD Monitor Photodiode Input
86 IMPDMON Mirrored Current from Monitor Photodiode
9 IMPDMON2 Mirrored Current from Monitor Photodiode2 (for Use with Two MPDs)
10 IMPD2 Monitor Photodiode Input 2 (for Use with Two MPDs)
11 7 GND4 Supply Ground
12 8 V

4 Supply Voltage

CC

13 9 ERCAP Extinction Ratio Loop Capacitor
14 10 PAVCAP Average Power Loop Capacitor
15 TP3 Test Pin. In normal operation, TP3 = GND.
16 11 V

1 Supply Voltage

CC

17 GND1 Supply Ground
18 12 DATAN Data, Negative Differential Terminal
19 13 DATAP Data, Positive Differential Terminal
20 14 GND1 Supply Ground
21 15 CLKP Data Clock Positive Differential Terminal, Used if CLKSEL = V
22 16 CLKN Data Clock Negative Differential Terminal, Used if CLKSEL = V

CC

CC

23 TP4 Test Pin. In normal operation, TP4 = GND.
24 TP5 Test Pin. In normal operation, TP5 = GND.
25 TP6 Test Pin. In normal operation, TP6 = GND.
26 17 CLKSEL Clock Select (Active = V

), Used if Data Is Clocked into Chip

CC

27 18 DEGRADE DEGRADE Alarm Output
28 19 FAIL FAIL Alarm Output
29 20 ALS Automatic Laser Shutdown
30 21 V

3 Supply Voltage

CC

31 22 GND3 Supply Ground
32 23 IMMON Modulation Current Mirror Output
33 24 IBMON Bias Current Mirror Output

REV. 0

–5–

ADN2847

PIN FUNCTION DESCRIPTIONS (continued)

Pin Number
48-Lead 32-Lead Mnemonic Function

34 GND2 Supply Ground
35 IDTONE IDTONE (Requires External Current Sink to Ground)
36 GND2 Supply Ground
37 GND2 Supply Ground
38 25 V
39 26 IMODN Modulation Current Negative Output. Connect via a matching resistor to V
40 26 IMODN Modulation Current Negative Output. Connect via a matching resistor to V
41 27 GND2 Supply Ground
42 28 IMODP Modulation Current Positive Output. Connect to laser diode.
43 28 IMODP Modulation Current Positive Output. Connect to laser diode.
44 29 GND2 Supply Ground
45 30 GND2 Supply Ground
46 31 I
47 31 I
48 32 CCBIAS Extra Laser Diode Bias when AC-Coupled Current Sink

2 Supply Voltage

CC

BIAS

BIAS

Laser Diode Bias Current
Laser Diode Bias Current

CC

CC

.

.

40

30

20

COUNT – %

10

0

76

78 80 82 84 86 88 90 92 94 96 98 100

RISE TIME – ps

Figure 4. Rise Time Distribution Under Worst­Case Operating Conditions

40

30

20

COUNT – %

10

0

82 84 86 88 90 92 94 96 98 100 102 104

80

FA LL TIME – ps

Figure 5. Fall Time Distribution Under Worst­Case Operating Conditions

GENERAL

Laser diodes have current-in to light-out transfer functions as
shown in Figure 6. Two key characteristics of this transfer function
are the threshold current, I

, and slope in the linear region

TH

beyond the threshold current, referred to as slope efficiency, LI.

P1

ER =

P0

P1 + P0

P

=

AV

2

P

P

LI =

I

I

TH

I

CURRENT

P

OPTICAL POWER

P1

AV

P0

Figure 6. Laser Transfer Function

Control

A monitor photodiode, MPD, is required to control the LD.
The MPD current is fed into the ADN2847 to control the power
and extinction ratio, continuously adjusting the bias current and
modulation current in response to the laser’s changing threshold
current and light-to-current slope efficiency.

The ADN2847 uses automatic power control, APC, to maintain
a constant average power over time and temperature.

The ADN2847 uses closed-loop extinction ratio control to allow
optimum setting of extinction ratio for every device. Thus
SONET/SDH interface standards can be met over device
variation, temperature, and laser aging. Closed-loop modulation
control eliminates the need to either overmodulate the LD or
include external components for temperature compensation.
This reduces research and development time and second
sourcing issues caused by characterizing LDs.

Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected between
these pins and ground. The potentiometer R
change the average power. The potentiometer R

is used to

PSET

ERSET

is used to

adjust the extinction ratio. Both PSET and ERSET are kept

1.2 V above GND.

REV. 0–6–

ADN2847

The R

PSET

and R

potentiometers can be calculated using the

ERSET

following formulas.

12.

V

I

12

×

AV

.

ER

ER

Ω

()

V

−
+

Ω

1

×

1

()

P

AV

R

ERSET

=

R

PSET

I

MPD CW

P

CW

=

_

where:

IAV is the average MPD current.

P

is the dc optical power specified on the laser data sheet.

CW

is the MPD current at that specified PCW.

I

MPD_CW

PAV is the average power required.

ER is the desired extinction ratio (ER = P1/P0).

Note that I

ERSET

and I

will change from device to device;

PSET

however, the control loops will determine actual values. It is not
required to know exact values for LI or MPD optical coupling.

Loop Bandwidth Selection

For continuous operation, the user should hardwire the LBWSET
pin high and use 1 µF capacitors to set the actual loop bandwidth.
These capacitors are placed between the PAVCAP and ERCAP
pins and ground. It is important that these capacitors are low
leakage multilayer ceramics with an insulation resistance greater
than 100 GΩ or a time constant of 1000 sec, whichever is less.

Operation Recommended Recommended
Mode LBWSET PAVCAP ERCAP

Continuous High 1 µF1 µF
50 Mbps to

3.3 Gbps
Optimized Low 22 nF 22 nF
for 2.5 Gbps

to 3.3 Gbps

Setting LBSET low and using 22 nF capacitors results in a
shorter loop time constant (a 10× reduction over using 1 µF
capacitors and keeping LBWSET high.)

Alarms

The ADN2847 is designed to allow interface compliance to ITU­T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and section

10.3.1.1.3 (transmitter degrade). The ADN2847 has two active
high alarms, DEGRADE and FAIL. A resistor between ground
and the ASET pin is used to set the current at which these
alarms are raised. The current through the ASET resistor is a
ratio of 100:1 to the FAIL alarm threshold. The DEGRADE
alarm will be raised at 90% of this level.

Example:

ImAsoI mA

==50 45

FAIL DEGRADE

ImA

I

ASET

*

R

ASET

* The smallest valid value for R

maximum of 100 mA.

REV. 0

FAIL

== =

10050100

V

12 12

..

== =

IA

ASET

ASET

500



is 1.2 kΩ, since this corresponds to the I

500 µ

2.4 Ω

A

k

BIAS

–7–

The laser degrade alarm, DEGRADE, is provided to give a warning
of imminent laser failure if the laser diode degrades further or
environmental conditions continue to stress the LD, such as
increasing temperature.

The laser fail alarm, FAIL, is activated when the transmitter can no
longer be guaranteed to be SONET/SDH compliant. This occurs
when one of the following conditions arises:

•

The ASET threshold is reached.

•

The ALS pin is set high. This shuts off the modulation and bias
currents to the LD, resulting in the MPD current dropping
to zero. This gives closed-loop feedback to the system that
ALS has been enabled.

DEGRADE will be raised only when the bias current exceeds
90% of ASET current.

Monitor Currents

IBMON, IMMON, IMPDMON, and IMPDMON2 are current
controlled current sources from VCC. They mirror the bias, modu­lation, and MPD current for increased monitoring functionality.
An external resistor to GND gives a voltage proportional to the
current monitored.

If the monitoring functions IMPDMON and IMPDMON2 are
not required, the IMPD and IMPD2 pins must be grounded
and the monitor photodiode output must be connected directly
to the PSET pin.

Dual MPD DWDM Function (48-Lead LFCSP Only)

The ADN2847 has circuitry for a second monitor photodiode,
MPD2. The second photodiode current is mirrored to IMPDMON2
for wavelength control purposes and is summed internally with
the first monitor photodiode current for the power control loop.
For single MPD circuits, the MPD2 pin is tied to GND.

This enables the system designer to use the two currents to
control the wavelength of the laser diode using various optical
filtering techniques inside the laser module.

If the monitor current functions IMPDMON and IMPDMON2
are not required, then the IMPD and IMPD2 pins can be
grounded and the monitor photodiode output can be connected
directly to PSET.

IDTONE (48-Lead LFCSP Only)

The IDTONE pin is supplied for fiber identification/supervisory
channels or control purposes in WDM. This pin modulates the
optical one level over a possible range of 2% of minimum I
to 10% of maximum I

. The level of modulation is set by

MOD

MOD

connecting an external current sink between the IDTONE pin and
ground. There is a gain of two from this pin to the I

MOD

current.

Figure 9 shows how an AD9850/AD9851 or the AD9834 may be
used with the ADN2847 to allow fiber identification.

If the ID_TONE function is not used, the IDTONE pin should
be tied to V

. Note that using IDTONE during transmission

CC

may cause optical eye degradation.

Data, Clock Inputs

Data and clock inputs are ac-coupled (10 nF capacitors are
recommended) and terminated via a 100 Ω internal resistor between
DATAP and DATAN, and also between the CLKP and CLKN
pins. There is a high impedance circuit to set the common-mode
voltage that is designed to allow for maximum input voltage

ADN2847

headroom over temperature. It is necessary that ac coupling is
used to eliminate the need for matching between common­mode voltages.

ADN2847

DATAP

DATAN

(TO FLIP-FLOPS)

50 50

V

REG

R

R = 2.5k, DATA
R = 3k, CLK

400A TYP

Figure 7. AC Coupling of Data Inputs

For input signals that exceed 500 mV p-p single ended, it is
necessary to insert an attenuation circuit as shown in Figure 8.

R1

R2

NOTE THAT RIN = 100 = THE DIFFERENTIAL
INPUT IMPEDANCE OF THE ADN2847

DATAP /CLKP

R3

DATAN /CLKN

ADN2847

R

IN

Figure 8. Attenuation Circuit

CCBIAS

When the laser is used in ac-coupled mode, the CCBIAS and

pins should be tied together (Figure 12). In dc-coupled

I

BIAS

mode, CCBIAS should be tied to V

CC

.

Automatic Laser Shutdown

The ADN2847 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both bias and modulation

currents are turned off. Correct operation of ALS can be
confirmed by the FAIL alarm being raised when ALS is as­serted. Note that this is the only time DEGRADE will be low
while FAIL is high.

Alarm Interfaces

The FAIL and DEGRADE outputs have an internal pull-up
resistor of 30 kΩ used to pull the digital high value to V

CC

.
However, the alarm can be overdriven with an external resistor
allowing alarm interfacing to non-V

output levels must be below the V

levels. Non-VCC alarm

CC

used for the ADN2847.

CC

Power Consumption

The ADN2847 die temperature must be kept below 125oC. Both
LFCSP packages have an exposed paddle, which should be
connected in such a manner that is is at the same potential as
the ADN2847 ground pins. The θ

for both packages is shown

JA

in the Absolute Maximum Ratings. Power consumption can be
calculated using

II I

= + 0.3

CC CCMIN MOD

PV I I V I V V

=×+ ×

CC CC BIAS BIAS PIN MOD MODP PIN MODN PIN

TT P

=×+

DIE AMBIENT A

Thus, the maximum combination of I

()

___

θ

J

()

+ I

BIAS

+

must be calcu-

MOD

/+2

lated. Where:

I

=

CCMIN

with I

T

DIE

T

AMBIENT

V

BIAS_PIN

V

MODP_PIN

V

MODN_PIN

50 mA, the typical value of ICC provided on page 3

BIAS

= I

MOD

= 0

= die temperature

= ambient temperature

= voltage at I

BIAS

pin

= average voltage at IMODP pin

= average voltage at IMODN pin

Laser Diode Interfacing

Many laser diodes designed for 2.5 Gbs operation are packaged
with an internal resistor to bring the effective impedance up to
25 Ω in order to minimize transmission line effects. In high current
applications, the voltage drop across this resistor combined with
the laser diode forward voltage makes direct connection between
the laser and the driver impractical in a 3 V system. AC coupling
the driver to the laser diode removes this headroom constraint.

REF CLOCK

20MHz–180MHz

10kHz–1MHz

0.125mA–2mA

BC550

500

50A–800A

1000

35

IDTONE

ADN2847

32

IMMON

CLKIN

AD9850/AD9851

AD9834

R

CONTROLLER

9

DDS

SET

1.25mA–20mA

21

20

12

37.5A–600A

I

OUT

I

OUT

50

50

LP FILTER

(DC-COUPLED)

BC550

AD8602

AD8602

1300

1/2

1/2

Figure 9. Application Curcuit to Allow Fiber Identification Using the AD9850/AD9851

REV. 0–8–

Caution must be taken when choosing component values for
ac coupling to ensure that the time constants (L/R and RC, see
Figure 12) are sufficiently long for the data rate and expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.

For designs with low series resistance, or where external components
become impractical, the ADN2847 supports direct connection
to the laser diode (see Figure 11). In this case, care must be
taken to ensure that the voltage drop across the laser diode does
not violate the minimum compliance voltage on the IMODP pin.

Optical Supervisor

The PSET and ERSET potentiometers may be replaced with a
dual-digital potentiometer, the ADN2850 (see Figure 10). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent stability
over temperature.

ALS

ADN2847

V

CC

V

V

CC

IMPD

ADN2847

CLK

TX

RX

CS

ADN2850

SDI

SDO

CLK

CS

DAC1

DAC2

PSET

ERSET

DATAP
DATAN

IDTONE

DATAP

IMODP

I

BIAS

DATAN

IDTONE

Figure 10. Application Using the ADN2850 a Dual 10-Bit
Digital Potentiometer with an Extremely Low Temperature
Coefficient as an Optical Supervisor

FAIL
DEGRADE

CC

V

CC

MPD LD

36

37

GND2

2

V

*

V

CC

*

*

*

10H

V

LD = LASER DIODE
MPD = MONITOR PHOTODIODE

CC

IMODN

IMODN

GND2

IMODP

IMODP

GND2

GND2

I

BIAS

I

BIAS

CCBIAS

48

CC

1

V

GND2

GND

CC

IDTONE

LBWSET

GND2

ASET

IBMON

IMMON

ERSET

** **

1k

1.5k1.5k

3

V

GND3

ADN2847

IMPD

GND

PSET

25

CC

ALS

FAIL

IMPDMON2

IMPDMON

1.5k

100nF 100nF 100nF 100nF

CLKSEL

DEGRADE

IMPD2

GND4

GND

GND

GND

CLKN

CLKP

GND1

DATAP

DATAN

GND1

V

CC

GND

PAV CAP

ERCAP

4

CC

V

12

V

CC

1

24

GND

10nF

CLKN

10nF

CLKP

10nF

DATAP

10nF

DATAN

22nF

22nF

13

VCCs SHOULD HAVE BYPASS CAPACITORS AS
CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS

ON THE ADN2847 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE
100pF CAPACITORS IN PARALLEL WITH 10nF
CAPACITORS.

10F

REV. 0

NOTES

* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
**FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.

GND

Figure 11. DC-Coupled 3.3 Gbps Test Circuit, Data Not Clocked

–9–

ADN2847

ALS

FAIL

DEGRADE

V

CC

MPD LD

V

CC

*

*

*

*

1H

LD = LASER DIODE
MPD = MONITOR PHOTODIODE

*

*

*

37

GND2

V

IMODN

IMODN

*

*

*

GND2

IMODP

IMODP

GND2

GND2

I

I

CCBIAS

48

CC

BIAS

BIAS

1

V

CC

1.5k

36

GND2

GND2

IBMON

IDTONE

2

ERSET

ASET

LBWSET

GND

** **

1k

1.5k

GND3

IMMON

ADN2847

GND

PSET

25

3

CC

ALS

FAIL

V

IMPDMON2

IMPDMON

IMPD

1.5k

100nF 100nF 100nF 100nF

CLKSEL

DEGRADE

IMPD2

GND4

GND

GND

GND

CLKN

CLKP

GND1

DATAP

DATAN

GND1

V

CC

GND

PAV CAP

ERCAP

4

CC

V

12

V

CC

1

24

GND

10nF

CLKN

10nF

CLKP

10nF

DATAP

10nF

DATAN

1F

1F

13

VCCs SHOULD HAVE BYPASS CAPACITORS AS

CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS
ON THE ADN2847 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE
100pF CAPACITORS IN PARALLEL WITH 10nF
CAPACITORS.

10F

NOTES

* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED
**FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.

Figure 12. AC-Coupled 50 Mbps to 3.3 Gbps Test Circuit, Data Not Clocked

Figure 13. A 2.5 Gbps Optical Eye at 25°C. Average
Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31
Pattern. Eye Obtained Using a DFB Laser.

GND

Figure 14. A 2.5 Gbps Optical Eye at 85°C. Average
Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31
Pattern. Eye Obtained Using a DFB Laser.

REV. 0–10–

OUTLINE DIMENSIONS

48-Lead Frame Chip Scale Package [LFCSP]

(CP-48)

Dimensions shown in millimeters

ADN2847

1.00

0.90

0.80

0.25
REF

12 MAX

SEATING
PLANE

BSC SQ

PIN 1
INDICATOR

VIEW

7.00

0.60 MAX

TOP

0.70 MAX

0.65 NOM

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

0.50

0.40

0.30

0.05 MAX

0.02 NOM

COPLANARITY

0.08

37

36

25

24

0.60 MAX

BOTTOM

VIEW

5.50

REF

32-Lead Frame Chip Scale Package [LFCSP]

(CP-32)

Dimensions shown in millimeters

0.30

0.23

0.18

PIN 1
INDICATOR

48

1

5.25

4.70

2.25

12

13

PIN 1

INDICATOR

1.00

0.90

0.80

12 MAX

SEATING
PLANE

5.00

BSC SQ

0.30

0.23

0.18

4.75

BSC SQ

0.25 REF

TOP

VIEW

0.70 MAX

0.65 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

0.60 MAX

25

24

17

16

BOTTOM

VIEW

3.50
REF

PIN 1

32

9

INDICATOR

1

3.25
SQ

3.10

2.95

8

REV. 0

–11–

C02745–0–1/03(0)

–12–

PRINTED IN U.S.A.