ANALOG DEVICES ADN2817 Service Manual

Continuous Rate 10 Mbps to 2.7 Gbps Clock

www.BDTIC.com/ADI

FEATURES

Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier

5 mV sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate Bit error rate monitor (BERMON) or sample phase adjust options Rate selectivity without the use of a reference clock

2

I

C interface to access optional features Single-supply operation: 3.3 V Low power

650 mW (ADN2817) 600 mW (ADN2818)

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates Fibre Channel, 2× Fibre Channel, GbE, HDTV, and others WDM transponders Regenerators/repeaters Test equipment

FUNCTIONAL BLOCK DIAGRAM

REFCLKP/REFCLKN

(OPTIO NAL)

LOL

and Data Recovery ICs

ADN2817/ADN2818

GENERAL DESCRIPTION

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.

The ADN2817/ADN2818 have many optional features available through an I the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.

The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.

CF1 CF2

2

C® interface. For example, the user can read back

VCC VEE

SLICE

THRADJ

ADJUST

(ADN2817

ONLY)

LOS

DETECT

(ADN2817

ONLY)

LOS DATAOUTP/

PHASE

SHIFTER

DATA

RETIMING

DATAOUTN

SLICEP/

SLICEN

NIN

VREF

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FREQ/ LOCK

DET

PHASE

DET

ΔФ

CLKOUTP/

CLKOUTN

Figure 1.

ADN2817/ADN2818

LOOP

FILTER

LOOP

FILTER

BERMON

VBER BERMODE

VCO

I2C

REGISTERS

SCK SDA

06001-001

ADN2817/ADN2818

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REVISION HISTORY

8/08—Rev. 0 to Rev. A

Changes to Features Section, General Description Section, and

Figure 1 .............................................................................................. 1

Added Bit Rate Monitor Specifications Section and Table 4;

Renumbered Sequentially ................................................................ 7

Changes to Figure 5 and Table 6 ................................................... 10

Changes to Table 7 and Table 8 ..................................................... 14

Changes to Table 14 ........................................................................ 15

Added Table 15 ............................................................................... 15

Added Table 16 ............................................................................... 16

Added Sample Phase Adjust Section and Bit Error Rate (BER)

Monitor Section .............................................................................. 23

Added Figure 32; Renumbered Sequentially .............................. 24

Changes to Figure 36 ...................................................................... 29

Added Exposed Pad Notation to Outline Dimensions ............. 37

7/07—Revision 0: Initial Version

Rev. A | Page 2 of 40

ADN2817/ADN2818

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SPECIFICATIONS

TA = T unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

QUANTIZER—AC CHARACTERISTICS

QUANTIZER—SLICE ADJUSTMENT ADN2817 only

LOSS OF SIGNAL DETECT (LOS) ADN2817 only

R

LOSS OF LOCK DETECT (LOL)

ACQUISITION TIME

DATA RATE READBACK ACCURACY

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 2.0 V Input Common-Mode Level DC-coupled (see Figure 40, Figure 41, and Figure 42) 2.3 2.5 2.8 V Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10

−10

ADN2817 10 5 mV p-p ADN2818 200 mV p-p

Data Rate 10 2700 Mbps S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF

Gain SLICEP − SLICEN = ±0.5 V 0.10 0.11 0.13 V/V Differential Control Voltage Input SLICEP − SLICEN −0.95 +0.95 V Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V Slice Threshold Offset ±1 mV

Loss of Signal Detect Range (See Figure 6) R

= 0 Ω 14.2 20.0 mV

Thresh

= 100 kΩ 2.1 5.0 mV

Thresh

Hysteresis (Electrical)

OC-48 R

OC-1 R

LOS Assert Time DC-coupled LOS Deassert Time DC-coupled

= 0 Ω 6.2 8.2 dB

Thresh

= 100 kΩ 4.7 7.7 dB

Thresh

= 0 Ω 4.9 7.5 dB

Thresh

= 10 kΩ 3.0 7.3 dB

Thresh

2

500 ns

450 ns

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time

OC-48 1.0 μs OC-12 1.0 μs 10 Mbps 500 μs

Lock to Data Mode

OC-48 1.3 ms OC-12 2.0 ms OC-3 3.4 ms OC-1 9.8 ms 10 Mbps 40.0 ms

Optional Lock to REFCLK Mode 10.0 ms

Coarse Readback See Tab le 19 10 % Fine Readback In addition to REFCLK accuracy 100 ppm

Rev. A | Page 3 of 40

ADN2817/ADN2818

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Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Voltage 3.0 3.3 3.6 V Current

ADN2817 210 247 mA ADN2818 180 217 mA

OPERATING TEMPERATURE RANGE −40 +85 °C

1

PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.

2

When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817

input stage.

JITTER SPECIFICATIONS

TA = T unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

1

Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 F, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Jitter Transfer Bandwidth

OC-48 548 839 kHz OC-12 93 137 kHz OC-3 30 40 kHz

Jitter Peaking

OC-48 0 0.03 dB OC-12 0 0.03 dB OC-3 0 0.03 dB

Jitter Generation

OC-48 12 kHz to 20 MHz 0.001 0.003 UI rms

0.02 0.046 UI p-p OC-12 12 kHz to 5 MHz 0.001 0.004 UI rms

0.01 0.036 UI p-p OC-3 12 kHz to 1.3 MHz 0.001 0.004 UI rms

0.01 0.023 UI p-p Jitter Tolerance 223 − 1 PRBS

OC-48 600 Hz 6 kHz

1

20.0 UI p-p

92.0 UI p-p

100 kHz 7.0 UI p-p 1 MHz

1

1.00 UI p-p

20 MHz 0.53 UI p-p OC-12 30 Hz 300 Hz

1

100.0 UI p-p

1

44.0 UI p-p

25 kHz 7.35 UI p-p 250 kHz

1

1.00 UI p-p

5 MHz 0.52 UI p-p OC-3 30 Hz

300 Hz

1

50.0 UI p-p

1

23.5 UI p-p

6500 Hz 6.71 UI p-p 65 kHz

1

1.00 UI p-p

130 kHz 0.54 UI p-p

Rev. A | Page 4 of 40

ADN2817/ADN2818

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OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN,

DATAOUTP/DATAOUTN) Single-Ended Output Swing, VSE See Figure 3 300 350 600 mV Differential Output Swing, V

See Figure 3 600 700 1200 mV

DIFF

Output Voltage

High, VOH VCC V Low, VOL VCC − 0.6 VCC − 0.35 VCC − 0.3 V

CML Outputs Timing

Rise Time 20% to 80% 80 112 ps Fall Time 80% to 20% 80 123 ps Setup Time, tS See Figure 2, OC-48 150 200 250 ps Hold Time, tH See Figure 2, OC-48 150 200 250 ps Setup Time, t Hold Time, t

See Figure 4, OC-48 140 170 200 ps

DDRS

See Figure 4, OC-48 200 230 260 ps

DDRH

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input Voltage

High, VIH 0.7 VCC V

Low, VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V

I2C INTERFACE TIMING See Figure 22

SCK Clock Frequency 400 kHz SCK Pulse Width High

High, t

Low, t

600 ns

HIGH

1300 ns

LOW

Start Condition

Hold Time, t

Setup Time, t

600 ns

HD;STA

600 ns

SU;STA

Data

Setup Time, t

Hold Time, t

100 ns

SU;DAT

300 ns

HD;DAT

SCK/SDA Rise/Fall Time, tR/tF 20 + 0.1 Cb 300 ns Stop Condition Setup Time, t Bus Free Time Between a Stop and a Start, t

600 ns

SU;STO

1300 ns

BUF

REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN

VIL 0 V

VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 200 MHz Required Accuracy 100 ppm

Rev. A | Page 5 of 40

ADN2817/ADN2818

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Parameter Conditions Min Typ Max Unit

LVTTL DC INPUT CHARACTERISTICS

Input Voltage

High, VIH 2.0 V Low, VIL 0.8 V

Input Current

High IIH, VIN = 2.4 V +5 μA Low IIL, VIN = 0.4 V −5 μA

LVTTL DC OUTPUT CHARACTERISTICS

Output Voltage

High VOH, IOH = −2.0 mA 2.4 V Low VOL, IOL = +2.0 mA 0.4 V

Rev. A | Page 6 of 40

ADN2817/ADN2818

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BIT ERROR RATE MONITOR SPECIFICATIONS

TA = T unless otherwise noted.

Table 4.

Parameter Conditions Min Typ Max Unit

BERMON Extrapolation Mode I2C controlled eye profiling

BERMON Voltage Output Mode Analog voltage output

Sample Phase Adjust Mode

to T

MIN

Final Computed BER Accuracy

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Input BER range 1 × 10

−3

to 1 × 10

−12

,

±1 Decades input deterministic jitter (DJ) < 0.4 UI, DJ ceiling > 1 × 10−2; asymmetry < 0.1 UI; requires external data processing algorithms to implement Q factor extrapolation

18

Number of Bits (NUMBITS)

Number of data bits to collect pseudo errors; user programmable in increment factors of

3

over the range 218 to 239

2

PBER Measurement Time

2

239 UI

Numbits/

sec

data rate BER Range 5 × 10−2 BER Sample Phase Adjust Resolution 6 Degrees Sample Phase Adjust Accuracy <6 Degrees Sample Phase Adjust Range With respect to normal sampling instant −0.5 +0.5 UI Minimum Input Signal Level Differential peak to peak 4 mV Power Increase BER enabled 160 mW BER standby 77 mW

BER Accuracy

Input BER range 1 × 10 input DJ = 0 UI, DJ ceiling > 1 × 10

−3

to 1 × 10−9,

−2

;

±1 Decades

asymmetry = 0 UI; BER is read as a voltage on the VBER pin, when the BER mode pin = VEE

−3

Input BER range 1 × 10

to 1 × 10−9,

input DJ = 0.2 UI, DJ ceiling > 1 × 10

−2

;

+1/−2 Decades

asymmetry = 0 UI; BER is read as a voltage on

the VBER pin, when the BER mode pin = VEE Numbits Number of data bits to collect pseudo errors 227 UI Measurement Time 2.5 Gbps 0.054 sec 1 Gbps 0.134 sec 155 Mbps 0.865 sec 10 Mbps 1.34 sec VBER Voltage Range Via 3 kΩ resistor to VEE 0.1 0.9 V Minimum Input Signal Level Differential peak to peak 4 mV Power Increase BER voltage mode 160 mW

Sample Phase Adjust Step Size Monotonic 6 Degrees Sample Phase Adjust Accuracy <6 Degrees Sample Phase Adjust Range With respect to normal sampling instant −0.5 +0.5 UI Power Increase 160 mW

Rev. A | Page 7 of 40

ADN2817/ADN2818

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TIMING CHARACTERISTICS

CLKOUTP

t

S

DATAOUTP/

DATAOUTN

Figure 2. Default Mode Output Timing

OUTP

OUTN

OUTP – OUTN

V

CML

V

0V

SE

V

DIFF

Figure 3. Single-Ended vs. Differential Output Specifications

CLKOUTP/

CLKOUTN

DATAOUT P/

CLKOUTN

t

DDRS

Figure 4. Double Data Rate Mode Output Timing

H

t

DDRH

06001-002

V

SE

06001-003

06001-042

Rev. A | Page 8 of 40

ADN2817/ADN2818

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ABSOLUTE MAXIMUM RATINGS

TA = T C

F

Table 5.

Parameter Rating

Supply Voltage (VCC) 4.2 V Input Voltage (All Inputs)

Junction Temperature, Maximum 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

to T

MIN

= 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted.

Minimum VEE − 0.4 V Maximum VCC + 0.4 V

, VCC = V

MAX

MIN

to V

, VEE = 0 V,

MAX

THERMAL CHARACTERISTICS

Thermal Resistance

32-lead LFCSP, 4-layer board with exposed paddle soldered to VEE: θ

= 28°C/W.

JA

ESD CAUTION

Rev. A | Page 9 of 40

ADN2817/ADN2818

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VBER

VCC

VEE

DATAOUTP

DATAOUTN

SQUELCH

CLKOUTP

CLKOUTN

25

26

27

28

29

31

30

32

VCC

VREF

NIN PIN

SLICEP

SLICEN

VEE

1 2 3 4 5 6 7 8

PIN 1 INDICATOR

ADN2817/

ADN2818

TOP VIEW

(Not to Scale)

9

11

12

10

VCC

THRADJ

REFCLKP

REFCLKN

13

VEE

BERMODE

NOTES

1. EXPOSE D PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECT ED TO VEE.

24

VCC

23

VEE

22

LOS

21

SDA

20

SCK

19

SADDR5

18

VCC

17

VEE

16

15

14

CF2

CF1

LOL

06001-004

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 BERMODE DI Set this pin to logic low to enable analog voltage output mode for BER monitor. 2 VCC P Power for Input Stage, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 SLICEP AI Differential Slice Level Adjust Input. 7 SLICEN AI Differential Slice Level Adjust Input. 8 VEE P GND for the Limiting Amplifier (Lim Amp), LOS. 9 THRADJ AI LOS Threshold Setting Resistor. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 200 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 200 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss of Lock Indicator. Active high, LVTTL. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 22 LOS DO Loss of Signal Detect Output. Active high, LVTTL. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. CML. 26 CLKOUTP DO Differential Recovered Clock Output. CML. 27 SQUELCH DI Disable Clock and Data Outputs. Active high, LVTLL. 28 DATAOUTN DO Differential Recovered Data Output. CML. 29 DATAOUTP DO Differential Recovered Data Output. CML. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 VBER AO This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE. EP EPAD P Connect exposed pad to VEE. Note that the exposed pad must be connected to VEE.

1

P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

Rev. A | Page 10 of 40

ADN2817/ADN2818

V

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TYPICAL PERFORMANCE CHARACTERISTICS

0.020

0.018

0.016

0.014

0.012

0.010

0.008

TRIP POINT (mV p-p)

0.006

0.004

0.002

0

110100

1k 100k10k 1M

R

(Ω)

TH

Figure 6. LOS Comparator Trip Point Programming

6001-005

200mV/DI

50ps/DIV

06001-040

Figure 9. Output Eye, OC-48

5

0

–5

GAIN (dB)

–10

–15

–20

100 1k 10k 100k 1M

ADN2817

JITTER F REQUENCY (Hz)

SONET

Figure 7. Jitter Transfer, OC-1

5

0

–5

GAIN (dB)

–10

–15

–20

100 1k 10k 100k 1M 10M

ADN2817

JITTER FREQUENCY (Hz)

SONET

Figure 8. Jitter Transfer, OC-3

100

10

1

JITTER AMPL ITUDE (UI)

ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004

0.1 10 100 1k 10k 100k 1M

6001-032

JITTER FREQUENCY (Hz)

06001-039

Figure 10. Jitter Tolerance, OC-1

100

10

1

JITTER AMPLITUDE (UI)

ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004

0.1 10 100 1k 10k 100k 10M1M

06001-034

JITTER FREQUENCY (Hz)

06001-038

Figure 11. Jitter Tolerance, OC-3

Rev. A | Page 11 of 40

ADN2817/ADN2818

www.BDTIC.com/ADI

5

0

SONET

–5

GAIN (dB)

–10

–15

–20

1k 10k 100k 1M 10M

ADN2817

JITTER F REQUENCY (Hz)

Figure 12. Jitter Transfer, OC-12

5

0

SONET

–5

GAIN (dB)

–10

ADN2817

06001-033

1000

100

10

JITTER AMP LITUDE (UI)

1

ADN2817 EQUIPMENT LIMIT SONET GR- 253 CORE 004

0.1 10 100 1k 10k 100k 10M1M

JITTER F REQUENCY (Hz)

Figure 15. Jitter Tolerance, OC-12

1000

100

10

06001-037

–15

–20

10k 100k 1M 10M 100M

JITTER FRE QUENCY (Hz)

Figure 13. Jitter Transfer, OC-48

0.70

0.65

0.60

0.55

0.50

0.45

OUTPUT SWING (V)

0.40

CLKOUTP ADN2817 BOOST

0.35

CLKOUTN ADN2817 BOOS T CLKOUTP ADN2817 NO BOOST CLKOUTN ADN2817 NO BO OST

0.30 100M 600M 1.1G 1.6G 2.1G 2.6G 3.1G

DATA RATE (Hz)

Figure 14. Output Swing vs. Data Rate

JITTER AMPLITUDE (UI)

1

ADN2817 EQUIPMENT LIMIT SONET GR- 253 CORE 004

0.1 10 100 1k 10k 100k 100M10M1M

06001-035

JITTER F REQUENCY (Hz)

06001-036

Figure 16. Jitter Tolerance, OC-48

1

0.1

0.01

0.001

0.0001

0.00001

0.000001

BIT ERROR RATE

0.0000001

0.00000001

0.000000001

06001-043

1.01.52.02.53.03.54.04.5

INPUT LEVEL (mV)

06001-041

Figure 17. Bit Error Rate vs. Input Level

Rev. A | Page 12 of 40

ANALOG DEVICES ADN2817 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

JITTER SPECIFICATIONS

OUTPUT AND TIMING SPECIFICATIONS

BIT ERROR RATE MONITOR SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Thermal Resistance

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS