ANALOG DEVICES ADN2815 Service Manual

Continuous Rate 10 Mb/s to 1.25 Gb/s

FEATURES

Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/

generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator

2

I

C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free

APPLICATIONS

SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband crossconnects and routers

Clock and Data Recovery IC

ADN2815

GENERAL DESCRIPTION

The ADN2815 provides the receiver functions of quantization
and clock and data recovery for continuous data rates from
10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all
data rates without the need for an external reference clock or
programming. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.

The ADN2815 is available in a compact 5 mm × 5 mm 32-lead
LFCSP.

FUNCTIONAL BLOCK DIAGRAM

REFCLKP/REFCLKN

(OPTIONAL)

PIN

NIN

VREF

BUFFER

SHIFTER

RE-TIMING

DATAOUTP/

DATAOUTN

PHASE

DATA

2

LOL

FREQUENCY

DETECT

PHASE

DETECT

2

CLKOUTP/

CLKOUTN

Figure 1.

LOOP

FILTER

LOOP

FILTER

ADN2815

DRVEE DVCCDRVCC DVEE

VCC VEECF1 CF2

VCO

04952-0-001

Rev. #

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ices is believed to be accurate and reliable. However, no

vices for its use, nor for any infringements of patents or other

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ood, MA 02062-9106, U.S.A.

ADN2815

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 12

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Jitter Specifications ....................................................................... 4

Output and Timing Specifications ............................................. 5

Absolute Maximum Ratings ............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution .................................................................................. 6

Timing Characteristics ..................................................................... 7

Pin Configuration and Function Descriptions ............................. 8

I2C Interface Timing and Internal Register Description ............. 9

Jitter Specifications ......................................................................... 11

Functional Description .................................................................. 14

Frequency Acquisition ............................................................... 14

Input Buffer ................................................................................. 14

Lock Detector Operation .......................................................... 14

Harmonic Detector .................................................................... 15

SQUELCH Mode ........................................................................ 15

I2C Interface ................................................................................ 15

Reference Clock (Optional) ...................................................... 16

Applications Information .............................................................. 19

PCB Design Guidelines ............................................................. 19

Coarse Data Rate Readback Look-Up Table ............................... 22

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

5/10—Rev. A to Rev. B

Changes to Figure 5 and Table 5 ..................................................... 8

Changes to Figure 19 ...................................................................... 19

2/09—Rev. 0 to Rev. A

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

9/05—Revision 0: Initial Version

Rev. B | Page 2 of 24

ADN2815

SPECIFICATIONS

TA = T
unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

QUANTIZER—AC CHARACTERISTICS

LOSS-OF-LOCK (LOL) DETECT

ACQUISITION TIME

OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms
10 Mb/s 40.0 ms

DATA RATE READBACK ACCURACY

POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 1.25 Gb/s 118 131 mA
OPERATING TEMPERATURE RANGE –40 +85 °C

to T

MIN

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V
Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V

Data Rate 10 1250 Mb/s
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time 10 Mb/s 4 ms
OC-12 200 μs
GbE 200 μs

Lock-to-Data Mode GbE 1.5 ms

Optional Lock to REFCLK Mode 20.0 ms

Coarse Readback See Table 13 10 %
Fine Readback In addition to REFCLK accuracy
Data rate ≤ 20 Mb/s 200 ppm
Data rate > 20 Mb/s 100 ppm

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Rev. B | Page 3 of 24

ADN2815

JITTER SPECIFICATIONS

TA = T
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

637 kHz 0.749 UI p-p
OC-12, 223 − 1 PRBS
30 Hz1 100 UI p-p
300 Hz1 44 UI p-p
25 kHz 2.5 UI p-p
250 kHz1 1.0 UI p-p
OC-3, 223 − 1 PRBS
30 Hz1 50 UI p-p
300 Hz1 24 UI p-p
6500 Hz 3.5 UI p-p
65 kHz1 1.0 UI p-p

1

Jitter tolerance of the ADN2815 at these jitter frequencies is better than what the test equipment is able to measure.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Jitter Transfer BW OC-12 75 130 kHz
OC-3 26 42 kHz
Jitter Peaking OC-12 0 0.03 dB
OC-3 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms

0.011 0.026 UI p-p
OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms

0.005 0.010 UI p-p

Jitter Tolerance GbE, IEEE 802.3

Rev. B | Page 4 of 24

ADN2815

OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

LVDS OUTPUT CHARACTERISTICS

(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)

Output Voltage High VOH (see Figure 3), 655 Mb/s 1475 mV
Output Voltage Low VOL (see Figure 3), 655 Mb/s 925 mV
Differential Output Swing VOD (see Figure 3), 655 Mb/s 250 320 400 mV
Differential Output Swing VOD (see Figure 3), 1.25 Gb/s 240 300 400 mV
Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω

LVDS Outputs Timing

Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), GbE 360 400 440 ps
Hold Time TH (see Figure 2), GbE 360 400 440 ps

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, I

I2C INTERFACE TIMING See Figure 10

SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t

REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V

1

Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.

= 3.0 mA 0.4 V

OL

600 ns

HIGH

1300 ns

LOW

600 ns

HD;STA

600 ns

SU;STA

100 ns

SU;DAT

300 ns

HD;DAT

600 ns

SU;STO

1300 ns

BUF

0 V

IL

VCC V

IH

1

300 ns

Rev. B | Page 5 of 24

ADN2815

ABSOLUTE MAXIMUM RATINGS

TA = T

0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted.

Table 4.

Parameter Rating

Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF =

MAX

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

32-LFCSP, 4-layer board with exposed paddle soldered to VEE,
θ

= 28°C/W.

JA

Rev. B | Page 6 of 24

ADN2815

TIMING CHARACTERISTICS

CLKOUTP

T

T

S

DATAOUTP/

DATAOUTN

V

OH

H

Figure 2. Output Timing

DIFFERENTIAL CLKOUTP/N, DATAOUTP/N

04952-0-002

V

OS

V

OL

|V |

OD

04952-0-032

Figure 3. Differential Output Specifications

5mA

R

LOAD

100Ω

5mA

SIMPLIFIED LVDS

OUTPUT STAGE

100Ω

Figure 4. Differential Output Stage

V

DIFF

04952-0-033

Rev. B | Page 7 of 24

ADN2815

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 VCC

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

VCC 1
VCC 2

VREF 3

NIN 4
PIN 5

NC 6
NC 7

VEE 8

* THERE IS AN EXPOSED PAD ON THE BOTTOM OF

THE PACKAGE THAT MUST BE CONNECT ED TO GND.

PIN 1
INDICATOR

ADN2815*

TOP VIEW

(Not to Scale)

NC 9

VCC 12

REFCLKP 10

REFCLKN 11

CF2 14

VEE 13

CF1 15

LOL 16

24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE

04952-0-004

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 VCC AI Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6, 7 NC No Connect.
8 VEE P GND for Limiting Amplifier, LOS.
9 NC No Connect.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 NC No Connect.
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 VCC AI Connect to VCC.
Exposed Pad Pad P Connect to GND. Works as a heat sink.

1

Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

Rev. B | Page 8 of 24