Continuous Rate 10 Mb/s to 1.25 Gb/s
FEATURES
Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
2
I
C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband crossconnects and routers
Clock and Data Recovery IC
ADN2815
GENERAL DESCRIPTION
The ADN2815 provides the receiver functions of quantization
and clock and data recovery for continuous data rates from
10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all
data rates without the need for an external reference clock or
programming. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The ADN2815 is available in a compact 5 mm × 5 mm 32-lead
LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
PIN
NIN
VREF
BUFFER
SHIFTER
RE-TIMING
DATAOUTP/
DATAOUTN
PHASE
DATA
2
LOL
FREQUENCY
DETECT
PHASE
DETECT
2
CLKOUTP/
CLKOUTN
Figure 1.
LOOP
FILTER
LOOP
FILTER
ADN2815
DRVEE DVCCDRVCC DVEE
VCC VEECF1 CF2
VCO
04952-0-001
Rev. #
Information furnished by Analog Dev
responsibility is assumed by Analog De
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ices is believed to be accurate and reliable. However, no
vices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norw
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–20 Analog Devices, Inc. All rights reserved.
ood, MA 02062-9106, U.S.A.
ADN2815
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Jitter Specifications ....................................................................... 4
Output and Timing Specifications ............................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Timing Characteristics ..................................................................... 7
Pin Configuration and Function Descriptions ............................. 8
I2C Interface Timing and Internal Register Description ............. 9
Jitter Specifications ......................................................................... 11
Functional Description .................................................................. 14
Frequency Acquisition ............................................................... 14
Input Buffer ................................................................................. 14
Lock Detector Operation .......................................................... 14
Harmonic Detector .................................................................... 15
SQUELCH Mode ........................................................................ 15
I2C Interface ................................................................................ 15
Reference Clock (Optional) ...................................................... 16
Applications Information .............................................................. 19
PCB Design Guidelines ............................................................. 19
Coarse Data Rate Readback Look-Up Table ............................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Figure 5 and Table 5 ..................................................... 8
Changes to Figure 19 ...................................................................... 19
2/09—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
9/05—Revision 0: Initial Version
Rev. B | Page 2 of 24
ADN2815
SPECIFICATIONS
TA = T
unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS
QUANTIZER—AC CHARACTERISTICS
LOSS-OF-LOCK (LOL) DETECT
ACQUISITION TIME
OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms
10 Mb/s 40.0 ms
DATA RATE READBACK ACCURACY
POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 1.25 Gb/s 118 131 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
to T
MIN
Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V
Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V
Data Rate 10 1250 Mb/s
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF
VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time 10 Mb/s 4 ms
OC-12 200 μs
GbE 200 μs
Lock-to-Data Mode GbE 1.5 ms
Optional Lock to REFCLK Mode 20.0 ms
Coarse Readback See Table 13 10 %
Fine Readback In addition to REFCLK accuracy
Data rate ≤ 20 Mb/s 200 ppm
Data rate > 20 Mb/s 100 ppm
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
Rev. B | Page 3 of 24
ADN2815
JITTER SPECIFICATIONS
TA = T
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
637 kHz 0.749 UI p-p
OC-12, 223 − 1 PRBS
30 Hz1 100 UI p-p
300 Hz1 44 UI p-p
25 kHz 2.5 UI p-p
250 kHz1 1.0 UI p-p
OC-3, 223 − 1 PRBS
30 Hz1 50 UI p-p
300 Hz1 24 UI p-p
6500 Hz 3.5 UI p-p
65 kHz1 1.0 UI p-p
1
Jitter tolerance of the ADN2815 at these jitter frequencies is better than what the test equipment is able to measure.
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
Jitter Transfer BW OC-12 75 130 kHz
OC-3 26 42 kHz
Jitter Peaking OC-12 0 0.03 dB
OC-3 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms
0.011 0.026 UI p-p
OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms
0.005 0.010 UI p-p
Jitter Tolerance GbE, IEEE 802.3
Rev. B | Page 4 of 24
ADN2815
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High VOH (see Figure 3), 655 Mb/s 1475 mV
Output Voltage Low VOL (see Figure 3), 655 Mb/s 925 mV
Differential Output Swing VOD (see Figure 3), 655 Mb/s 250 320 400 mV
Differential Output Swing VOD (see Figure 3), 1.25 Gb/s 240 300 400 mV
Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω
LVDS Outputs Timing
Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), GbE 360 400 440 ps
Hold Time TH (see Figure 2), GbE 360 400 440 ps
I2C INTERFACE DC CHARACTERISTICS LVCMOS
Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, I
I2C INTERFACE TIMING See Figure 10
SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V
1
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
= 3.0 mA 0.4 V
OL
600 ns
HIGH
1300 ns
LOW
600 ns
HD;STA
600 ns
SU;STA
100 ns
SU;DAT
300 ns
HD;DAT
600 ns
SU;STO
1300 ns
BUF
0 V
IL
VCC V
IH
1
300 ns
Rev. B | Page 5 of 24
ADN2815
ABSOLUTE MAXIMUM RATINGS
TA = T
0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF =
MAX
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-LFCSP, 4-layer board with exposed paddle soldered to VEE,
θ
= 28°C/W.
JA
Rev. B | Page 6 of 24
ADN2815
TIMING CHARACTERISTICS
CLKOUTP
T
T
S
DATAOUTP/
DATAOUTN
V
OH
H
Figure 2. Output Timing
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
04952-0-002
V
OS
V
OL
|V |
OD
04952-0-032
Figure 3. Differential Output Specifications
5mA
R
LOAD
100Ω
5mA
SIMPLIFIED LVDS
OUTPUT STAGE
100Ω
Figure 4. Differential Output Stage
V
DIFF
04952-0-033
Rev. B | Page 7 of 24
ADN2815
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 VCC
31 VCC
30 VEE
29 DATAOUTP
28 DATAOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
VCC 1
VCC 2
VREF 3
NIN 4
PIN 5
NC 6
NC 7
VEE 8
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECT ED TO GND.
PIN 1
INDICATOR
ADN2815*
TOP VIEW
(Not to Scale)
NC 9
VCC 12
REFCLKP 10
REFCLKN 11
CF2 14
VEE 13
CF1 15
LOL 16
24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
04952-0-004
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 VCC AI Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6, 7 NC No Connect.
8 VEE P GND for Limiting Amplifier, LOS.
9 NC No Connect.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 NC No Connect.
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 VCC AI Connect to VCC.
Exposed Pad Pad P Connect to GND. Works as a heat sink.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. B | Page 8 of 24
ADN2815
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SLAVE ADDRESS [6...0] CTRL.
1A500000X
MSB = 1 SET BY
PIN 19
Figure 6. Slave Address Configuration
R/W
0 = WR
1 = RD
04952-0-007
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
2
Figure 7. I
C Write Data Transfer
04952-0-008
S
S = START BIT P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
2
Figure 8. I
C Read Data Transfer
START BIT STOP BIT
SDA
SCK
S P
SLAVE ADDRESS SUB ADDRESS DATA
SLADDR[4...0] SUB ADDR[6...1] DATA[6...1]
Figure 9. I
2
C Data Transfer Timing
D0D7A0A7A5A6
ACKACKWR ACK
SDA
t
F
t
SU;DAT
t
HD;STA
t
BUF
04952-0-009
04952-0-010
SCK
t
t
t
R
t
LOW
t
SSPS
HD;STA
t
HD;DAT
t
HIGH
Figure 10. I
t
F
t
SU;STA
2
C Port Timing Diagram
SU;STO
R
04952-0-011
Rev. B | Page 9 of 24
ADN2815
Table 6. Internal Register Map1
Reg Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB
FREQ1 R 0x1 MSB LSB
FREQ2 R 0x2 0 MSB LSB
RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1]
MISC R 0x4 x x x
Static
LOL
LOL
Status
Data Rate
Measure
Complete
CTRLA W 0x8 F
CTRLB W 0x9
Range Data Rate/DIV_F
REF
Config
LOL
Reset
MISC[4]
System
Reset
Ratio Measure Data Rate Lock to Reference
REF
0
Reset
0 0 0
MISC[2]
CTRLC W 0x11 0 0 0 0 0 0 SQUELCH Mode Output Boost
1
All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Static LOL LOL Status Data Rate Measurement Complete Coarse Rate Readback LSB
D7 D6 D5 D4 D3 D2 D1 D0
x x x 0 = Waiting for next LOL 0 = Locked 0 = Measuring data rate x COARSE_RD[0]
1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete
x COARSE_RD[0] LSB
Table 8. Control Register, CTRLA
F
Range Data Rate/Div_F
REF
1
Ratio Measure Data Rate Lock to Reference
REF
D7 D6 D5 D4 D3 D2 D1 D0
0 0 10 MHz to 20 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 = Lock to input data
0 1 20 MHz to 40 MHz 0 0 0 1 2 1 = Lock to reference clock
1 0 40 MHz to 80 MHz 0 0 1 0 4
1 1 80 MHz to 160 MHz n 2n
1 0 0 0 256
1
Where DIV_F
is the divided down reference referred to the 10 MHz to 20 MHz band (see the R section). eference Clock (Optional)
REF
Table 9. Control Register, CTRLB
Config LOL Reset MISC[4] System Reset Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by
0 to reset ADN2815
Set to 0
Write a 1 followed by
0 to reset MISC[2]
Set to 0 Set to 0 Set to 0
Table 10. Control Register, CTRLC
SQUELCH Mode Output Boost
D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = SQUELCH CLK and DATA 0 = Default output swing
1 = SQUELCH CLK or DATA 1 = Boost output swing
Rev. B | Page 10 of 24
ADN2815
JITTER SPECIFICATIONS
The ADN2815 CDR is designed to achieve the best bit-errorrate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2815 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms, and must be less than 0.1 UI p-p.
0.1
SLOPE = –20dB/DECADE
04952-0-015
JITTER GAIN (dB)
ACCEPTABLE
RANGE
JITTER FREQUENCY (kHz)
Figure 11. Jitter Transfer Curve
f
C
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 12).
15.00
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 11).
1.50
0.15
INPUT JITTER AMPLITUDE (UI p-p)
f
0
Figure 12. SONET Jitter Tolerance Mask
f
1
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
f
f
2
3
f
4
04952-0-016
Rev. B | Page 11 of 24
ADN2815
THEORY OF OPERATION
The ADN2815 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
(PLL) controls the VCO by the fine-tuning control.
The delay and phase loops together track the phase of the input
data signal. For example, when the clock lags input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while the delayed data
loses phase. Because the loop filter is an integrator, the static
phase error is driven to zero.
X(s)
T
INPU
DATA
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN JITTER TRANSFER FUNCTION
o = VCO GAIN
c = LOOP INTEGRATO
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
Figure 13. ADN2815 PLL/DLL Architecture
Z(s)
R
psh
e(s)
d/sc
Z(s)
=
X(s)
TRACKING ERROR TRANSFER FUNCTION
e(s)
X(s)
cn
2
s
do
=
2
s
JITTER PEAKING
IN ORDINARY PLL
o/s
1/n
1
n psh
+
s+ 1
o
2
s
d psh
do
s++
c
cn
04952-0-017
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay and phase loops together simultaneously provide
wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 13 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL has virtually zero jitter peaking (see
Figure 14). This makes this circuit ideal for signal regenerator
applications where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
ADN2815
JITTER GAIN (dB)
o
n psh
FREQUENCY (kHz)
Figure 14. ADN2815 Jitter Response vs. Conventional PLL
d psh
c
Z(s)
X(s)
The delay and phase loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
04952-0-018
Rev. B | Page 12 of 24
ADN2815
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or at the
other. The size of the VCO tuning range, therefore, has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and therefore the phase shifter
takes on the burden of tracking the input jitter. The phase
shifter range, in UI, can be seen as a broad plateau on the jitter
tolerance curve. The phase shifter has a minimum range of 2 UI
at all data rates.
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
make the loop control voltage large enough to tune the range of
the phase shifter. Large phase errors at high jitter frequencies
cannot be tolerated. In this region, the gain of the integrator
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter accommodation is
determined by the eye opening of the input data, the static
phase error, and the residual loop jitter generation. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is
the closed loop bandwidth of the delay-locked loop, which is
roughly 1.5 MHz at 1.25 Gb/s.
Rev. B | Page 13 of 24
ADN2815
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2815 acquires frequency from the data over a range of
data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 10 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisition. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.
INPUT BUFFER
The input buffer has differential inputs (PIN/NIN), which are
internally terminated with 50 Ω to an on-chip voltage reference
(VREF = 2.5 V typically). The minimum differential input level
required to achieve a BER of 10
−10
is 200 mV p-p.
LOCK DETECTOR OPERATION
The lock detector on the ADN2815 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2815 is a continuous rate CDR that
locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency, and deasserts the loss-oflock signal, which appears on Pin 16 (LOL), when the VCO is
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
acquires phase lock. Once locked, if the input frequency error
exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted
and control returns to the frequency loop, which begins a new
frequency acquisition starting at the lowest point in the VCO
operating range, 10 MHz. The LOL pin remains asserted until
the VCO locks onto a valid input data stream to within
250 ppm frequency error. This hysteresis is shown in Figure 15.
LOL
1
–1000
0–250 250 1000 f
Figure 15. Transfer Function of LOL
VCO
(ppm)
ERROR
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2815 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16 (LOL), is
deasserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss-of-lock
signal is reasserted and control returns to the frequency loop,
which reacquires with respect to the reference clock. The LOL
pin remains asserted until the VCO frequency is within
250 ppm of the desired frequency. This hysteresis is shown in
Figure 15.
Static LOL Mode
The ADN2815 implements a static LOL feature, which indicates
if a loss-of-lock condition has ever occurred and remains
asserted, even if the ADN2815 regains lock, until the static LOL
bit is manually reset. The I
2
C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2815 has
reacquired lock to a new data rate. This bit can be reset by
writing a 1 followed by 0 to I
2
C Register Bit CTRLB[6]. Once
reset, the MISC[4] bit remains deasserted until another loss-oflock condition occurs.
Writ i ng a 1 to I
2
C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph.
04952-0-020
Rev. B | Page 14 of 24
ADN2815
The CTRLB[7] bit defaults to 0. In this mode, the LOL pin
operates in the normal operating mode, that is, it is asserted
only when the ADN2815 is in acquisition mode and deasserts
when the ADN2815 has reacquired lock.
HARMONIC DETECTOR
The ADN2815 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-12,
622.08Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be
perceived as a valid OC-12 bit stream, because the OC-3 data
pattern is exactly 4× slower than the OC-12 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-3
would be perceived by the ADN2815 as a 111100001111 pattern
at OC-12. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2815 implements a harmonic detector that automatically identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2815 automatically locks onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate, then the VCO is currently
locked onto, the VCO loses lock, the LOL pin is asserted, and a
new frequency acquisition is initiated. The ADN2815
automatically locks onto the new data rate.
The time to detect lock to harmonic is
16
2
× (Td/ρ)
where:
1/T
is the new data rate. For example, if the data rate is
d
switched from OC-12 to OC-3, then T
= 1/155.52 MHz.
d
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2815 is placed in lock to reference mode, the
harmonic detector is disabled.
SQUELCH MODE
Two SQUELCH modes are available with the ADN2815.
SQUELCH DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the
SQUELCH input, Pin 27, is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If the SQUELCH function is not
required, Pin 27 should be tied to VEE.
SQUELCH DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN/DATAOUTP pins are
squelched. When the SQUELCH input is driven to a low state,
the CLKOUT pins are squelched. This is especially useful in
repeater applications, where the recovered clock may not be
needed.
I2C INTERFACE
The ADN2815 supports a 2-wire, I2C compatible, serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2815 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word either sets a read or write
operation (see Figure 6). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start
condition and shift the next eight bits (the 7-bit address and the
R/W bit). The bits are transferred from MSB to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCK lines
waiting for the start condition and correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information to
the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADN2815 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses, plus the R/W bit. The ADN2815 has eight subaddresses
to enable the user-accessible internal registers (see Tab le 6
through Tab le 1 0 ). It, therefore, interprets the first byte as the
device address and the second byte as the starting subaddress.
Autoincrement mode is supported, allowing data to be read
from or written to the starting subaddress and each subsequent
address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Rev. B | Page 15 of 24
ADN2815
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCK high
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2815 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
reading back in autoincrement mode, then the highest subaddress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a
read. In a no-acknowledge condition, the SDATA line is not
pulled low on the ninth pulse. See Figure 7 and Figure 8 for
sample read and write data transfers and Figure 9 for a more
detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2815. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 16 through Figure 18 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical
and 100 ppm accuracy is sufficient.
ADN2815
REFCLKP
10
11
REFCLKN
Figure 16. Differential REFCLK Configuration
VCC
CLK
OSC
REFCLKP
OUT
REFCLKN
Figure 17. Single-Ended REFCLK Configuration
ADN2815
100kΩ
BUFFER
100kΩ100kΩ
100kΩ
BUFFER
VCC/2
VCC/2
0-021
04952-
04952-0-022
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2815 to lock onto data or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive because, in
the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Lock-to-reference mode is enabled by writing a 1 to I
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2815 locks onto a frequency derived
from the reference clock according to
The user must know exactly what the data rate is and provide a
reference clock that is a function of this rate. The ADN2815 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 10 MHz and
160 MHz. By default, the ADN2815 expects a reference clock of
between 10 MHz and 20 MHz. If it is between 20 MHz and
40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the
user needs to configure the ADN2815 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio
00 10 to 20 0000 1
01 20 to 40 0001 2
10 40 to 80 n 2n
11 80 to 160 1000 256
VCC
REFCLKP
NC
REFCLKN
Data Rate/2
ADN2815
10
BUFFER
11
100kΩ
Figure 18. No REFCLK Configuration
2
C Register Bit CTRLA[1]. Writing a 1 to both of
CTRLA[5:2]
= REFCLK/2
100kΩ
CTRLA[7:6]
VCC/2
04952-0-023
2
C Register
Rev. B | Page 16 of 24
ADN2815
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
, where DIV_F
REF
represents the
REF
divided-down reference referred to the 10 MHz to 20 MHz
band. For example, if the reference clock frequency is
38.88 MHz and the input data rate is 622.08 Mb/s, then
CTRLA[7:6] is set to [01] to give a divided-down reference
clock of 19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5,
because
622.08 Mb/s/19.44 MHz = 2
5
In this mode, if the ADN2815 loses lock for any reason, it
relocks onto the reference clock and continues to output a stable
clock.
While the ADN2815 is operating in lock-to-reference mode, if
the user ever changes the reference frequency, the F
(CTRLA[7:6]) or the F
ratio (CTRLA[5:2]), this must be
REF
REF
range
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock-to-reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2815 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2815 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
The reference clock can range from 10 MHz and 160 MHz. The
ADN2815 expects a reference clock between 10 MHz and
20 MHz by default. If it is between 20 MHz and 40 MHz,
40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs
to configure the ADN2815 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2815. This bit is level
sensitive and does not need to be reset to perform subsequent
frequency measurements.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the data
rate can be read back on FREQ[22:0]. The time for a data rate
measurement is typically 80 ms.
4. Read back the data rate from Registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
The data rate can be determined by
DATARATE
( )
[]
fFREQf
REFCLK
+×=14
/..
2022
)_(
RATESEL
where:
FREQ[22:0] is the reading from FREQ2[6:0] MSByte,
FREQ1[7:0], and FREQ0[7:0] LSByte.
f
is the data rate (Mb/s).
DATARATE
is the REFCLK frequency (MHz).
f
REFCLK
SEL_RATE is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because
the reference frequency falls into the 20 MHz to 40 MHz range.
Assume for this example that the input data rate is 1.25 Gb/s
(GbE). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x138800, which is equal to 128 × 10
6
Plugging this value into the equation yields
128e6 × 32e6/2
(14+1)
= 1.25 Gb/s
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Table 12.
D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0
FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]
Rev. B | Page 17 of 24
ADN2815
Additional Features Available via the I2C Interface Coarse Data Rate Readback
The data rate can be read back over the I2C interface to
approximately ±10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Tabl e 13 provides coarse data rate readback to within ±10%.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2815 in the
operating mode that it was previously programmed to in
Registers CTRL[A], CTRL[B], and CTRL[C].
2
C Register Bit CTRLB[5]. This initiates a new
Rev. B | Page 18 of 24
ADN2815
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 19 for the
recommended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
PLANE
880
pFε. A/dC
r
where:
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2815 VCC pins.
VCC
+
0.1µF
TRANSCEIVER
1nF
0.1µF
OPTI CAL
MODULE
50Ω
50Ω
0.1µF22µF 1nF
VCC
VCC
VREF
NIN
PIN
NC
NC
VEE
VCC
VCC
VEE
31
32
1
2
EXPOSED PAD
3
TIED OFF TO
4
VEE PLANE
5
WITH VIAS
6
7
8
9
10
EFCLKP
R
REFCLKN
NC
is the dielectric constant of the PCB material.
r
A is the area of the overlap of power and GND planes (cm
d is the separation between planes (mm).
For FR-4,
50Ω TRANSMISSIO N LINES
OUTN
DATA
SQUELCH
DATAOUTP
CLKOUTP
29
28
27
30
11
12
13
14
F1
CF2
C
VEE
VCC
NC
= 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.
r
DATAOUTP
DATAOUTN
CLKOUT P
CLKOUT N
CLKOUTN
25
26
VCC
24
VEE
23
NC
22
SDA
21
SCK
20
SADDR5
19
VCC
18
VEE
17
15
LOL
1nF
16
µC
VCC
0.1µF1nF
2
C CONTROLL ER
I
2
I
C CONTROLL ER
VCC
0.1µF
2
).
VCC
0.1µF
0.47µF ±20%
>300MΩ INSUL ATION RESISTANCE
1nF
04952-0-031
Figure 19. Typical ADN2815 Applications Circuit
Rev. B | Page 19 of 24
ADN2815
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP and DATAOUTN (also
REFCLKP and REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN output traces to be
matched in length to avoid skew between the differential traces.
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 20).
A 0.1 μF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
VCC
C
50
TIA
50
Figure 20. ADN2815 AC-Coupled Input Configuration
0.1F
IN
C
IN
ADN2815
PIN
NIN
50
VREF
50
3k
2.5V
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
04952-0-026
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2815 must be chosen
such that the device works properly over the full range of data
rates used in the application. When choosing the capacitors, the
time constant formed with the two 50 Ω resistors in the signal
path must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 21), causing patterndependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection can
require some trade-offs between droop and PDJ.
For example, assuming 2% droop can be tolerated, then the
maximum differential droop is 4%. Normalizing to V p-p:
Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e
–t/τ
); therefore, τ = 12t
where:
τ is the RC time constant (C is the ac coupling capacitor, R =
100 Ω seen by C).
t is the total discharge time, which is equal to nT.
n is the number of CIDs.
T is the bit period.
The capacitor value can then be calculated by combining the
equations for τ and t:
C = 12 nT/R
Once the capacitor value is selected, the PDJ can be
approximated as
pspp
etPDJ
r
6.0/15.0
nT/RC
where:
PDJ
is the amount of pattern-dependent jitter allowed;
pspp
< 0.01 UI p-p typical.
is the rise time, which is equal to 0.22/BW,
t
r
where BW ~ 0.7 (bit rate).
Note that this expression for t
is accurate only for the inputs.
r
The output rise time for the ADN2815 is ~100 ps, regardless of
data rate.
Rev. B | Page 20 of 24
ADN2815
V1
V1b
V2
V2b
V
DIFF
V
= V2–V2b
DIFF
VTH = ADN2815 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2815. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
VCC
C
IN
V1
TIA BUFFER
1
V1b
V2
C
IN
V2b
234
PIN
50Ω
50Ω
NIN
ADN2815
+
V
REF
–
CDR
C
OUT
C
OUT
DATAOUTP
DATAOUTN
VREF
VTH
04952-0-027
Figure 21. Example of Baseline Wander
Rev. B | Page 21 of 24
ADN2815
COARSE DATA RATE READBACK LOOK-UP TABLE
Code is the 9-bit value read back from COARSE_RD[8:0].
Table 13. Look-Up Table
Code F
0 5.3745e+06
1 5.3741e+06
2 5.4793e+06
3 5.5912e+06
4 5.7111e+06
5 5.8391e+06
6 5.9760e+06
7 6.1215e+06
8 6.2780e+06
9 6.4565e+06
10 6.6391e+06
11 6.8372e+06
12 7.0520e+06
13 7.2868e+06
14 7.5424e+06
15 7.8220e+06
16 7.6663e+06
17 7.6659e+06
18 7.8217e+06
19 7.9880e+06
20 8.1667e+06
21 8.3570e+06
22 8.5616e+06
23 8.7805e+06
24 9.0166e+06
25 9.2849e+06
26 9.5608e+06
27 9.8591e+06
28 1.0183e+07
29 1.0535e+07
30 1.0918e+07
31 1.1332e+07
32 1.0749e+07
33 1.0748e+07
34 1.0959e+07
35 1.1182e+07
36 1.1422e+07
37 1.1678e+07
38 1.1952e+07
39 1.2243e+07
40 1.2556e+07
41 1.2913e+07
42 1.3278e+07
43 1.3674e+07
44 1.4104e+07
45 1.4574e+07
46 1.5085e+07
47 1.5644e+07
MID
Code F
48 1.5333e+07
49 1.5332e+07
50 1.5643e+07
51 1.5976e+07
52 1.6333e+07
53 1.6714e+07
54 1.7123e+07
55 1.7561e+07
56 1.8033e+07
57 1.8570e+07
58 1.9122e+07
59 1.9718e+07
60 2.0367e+07
61 2.1070e+07
62 2.1835e+07
63 2.2664e+07
64 2.1498e+07
65 2.1496e+07
66 2.1917e+07
67 2.2365e+07
68 2.2844e+07
69 2.3357e+07
70 2.3904e+07
71 2.4486e+07
72 2.5112e+07
73 2.5826e+07
74 2.6556e+07
75 2.7349e+07
76 2.8208e+07
77 2.9147e+07
78 3.0170e+07
79 3.1288e+07
80 3.0665e+07
81 3.0664e+07
82 3.1287e+07
83 3.1952e+07
84 3.2667e+07
85 3.3428e+07
86 3.4246e+07
87 3.5122e+07
88 3.6066e+07
89 3.7140e+07
90 3.8243e+07
91 3.9436e+07
92 4.0733e+07
93 4.2140e+07
94 4.3671e+07
95 4.5328e+07
MID
Code F
96 4.2996e+07
97 4.2993e+07
98 4.3834e+07
99 4.4729e+07
100 4.5688e+07
101 4.6713e+07
102 4.7808e+07
103 4.8972e+07
104 5.0224e+07
105 5.1652e+07
106 5.3113e+07
107 5.4698e+07
108 5.6416e+07
109 5.8295e+07
110 6.0339e+07
111 6.2576e+07
112 6.1331e+07
113 6.1328e+07
114 6.2574e+07
115 6.3904e+07
116 6.5334e+07
117 6.6856e+07
118 6.8493e+07
119 7.0244e+07
120 7.2133e+07
121 7.4279e+07
122 7.6486e+07
123 7.8872e+07
124 8.1467e+07
125 8.4279e+07
126 8.7341e+07
127 9.0657e+07
128 8.5991e+07
129 8.5986e+07
130 8.7668e+07
131 8.9458e+07
132 9.1377e+07
133 9.3426e+07
134 9.5616e+07
135 9.7944e+07
136 1.0045e+08
137 1.0330e+08
138 1.0623e+08
139 1.0940e+08
140 1.1283e+08
141 1.1659e+08
142 1.2068e+08
143 1.2515e+08
MID
Code F
144 1.2266e+08
145 1.2266e+08
146 1.2515e+08
147 1.2781e+08
148 1.3067e+08
149 1.3371e+08
150 1.3699e+08
151 1.4049e+08
152 1.4427e+08
153 1.4856e+08
154 1.5297e+08
155 1.5774e+08
156 1.6293e+08
157 1.6856e+08
158 1.7468e+08
159 1.8131e+08
160 1.7198e+08
161 1.7197e+08
162 1.7534e+08
163 1.7892e+08
164 1.8275e+08
165 1.8685e+08
166 1.9123e+08
167 1.9589e+08
168 2.0089e+08
169 2.0661e+08
170 2.1245e+08
171 2.1879e+08
172 2.2566e+08
173 2.3318e+08
174 2.4136e+08
175 2.5030e+08
176 2.4532e+08
177 2.4531e+08
178 2.5029e+08
179 2.5562e+08
180 2.6134e+08
181 2.6742e+08
182 2.7397e+08
183 2.8098e+08
184 2.8853e+08
185 2.9712e+08
186 3.0594e+08
187 3.1549e+08
188 3.2587e+08
189 3.3712e+08
190 3.4936e+08
191 3.6263e+08
MID
Rev. B | Page 22 of 24
ADN2815
Code F
192 3.4397e+08
193 3.4394e+08
194 3.5067e+08
195 3.5783e+08
196 3.6551e+08
197 3.7370e+08
198 3.8247e+08
199 3.9177e+08
200 4.0179e+08
201 4.1322e+08
202 4.2490e+08
203 4.3758e+08
204 4.5133e+08
205 4.6636e+08
206 4.8272e+08
207 5.0061e+08
MID
Code F
MID
208 4.9064e+08
209 4.9062e+08
210 5.0059e+08
211 5.1123e+08
212 5.2267e+08
213 5.3485e+08
214 5.4794e+08
215 5.6195e+08
216 5.7706e+08
217 5.9423e+08
218 6.1189e+08
219 6.3098e+08
220 6.5173e+08
221 6.7423e+08
222 6.9873e+08
223 7.2525e+08
Code F
MID
224 6.8793e+08
225 6.8789e+08
226 7.0135e+08
227 7.1567e+08
228 7.3102e+08
229 7.4741e+08
230 7.6493e+08
231 7.8355e+08
232 8.0358e+08
233 8.2643e+08
234 8.4981e+08
235 8.7516e+08
236 9.0266e+08
237 9.3272e+08
238 9.6543e+08
239 1.0012e+09
Code F
MID
240 9.8129e+08
241 9.8124e+08
242 1.0012e+09
243 1.0225e+09
244 1.0453e+09
245 1.0697e+09
246 1.0959e+09
247 1.1239e+09
248 1.1541e+09
249 1.1885e+09
250 1.2238e+09
251 1.2620e+09
252 1.3035e+09
253 1.3485e+09
254 1.3975e+09
255 1.4505e+09
Rev. B | Page 23 of 24
ADN2815
C
OUTLINE DIMENSIONS
0.08
0.60 MAX
25
24
EXPOSED
PAD
(BOTTOM VIEW)
17
16
3.50 REF
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
32
9
INDICATOR
1
3.25
3.10 SQ
2.95
8
0.25 MIN
011708-A
INDI
1.00
0.85
0.80
PIN 1
ATO R
12° MAX
SEATING
PLANE
5.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARIT Y
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADN2815ACPZ −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2815ACPZ-500RL7 −40°C to +85°C 32-Lead LFCSP_VQ, Tape-Reel, 500 pieces CP-32-2
ADN2815ACPZ-RL7 −40°C to +85°C 32-Lead LFCSP_VQ, Tape-Reel, 1,500 pieces CP-32-2
EVAL-ADN2815EBZ Evaluation Board
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04952-0-5/10(B)
Rev. B | Page 24 of 24
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