Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and
S
Preliminary Technical Data
FEATURES
Serial data input: 12.3 Mb/s to 675 Mb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator
2
C™ interface to access optional features
I
Single-supply operation: 3.3 V
Low power: 350 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb Free
APPLICATIONS
SONET OC-1/3/12 and all associated FEC rates
ESCON, Fast Ethernet, Serial Digital Interface (DTV)
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
FUNCTIONAL BLOCK DIAGRAM
Data Recovery IC with Integrated Limiting Amp
ADN2814
PRODUCT DESCRIPTION
The ADN2814 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 675 Mb/s. The ADN2814
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance. All specifications are quoted for −40°C to
+85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a useradjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2814 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.
REFCLKP/N
(OPTIONAL)
LOL
VCC VEECF1 CF2
LICEP/N
PIN
NIN
VREF
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
2
QUANTIZER
LOS
DETECT
PHASE
SHIFTER
DATA
RE-TIMING
2
DATAOUTP/NLOSTHRADJ CLKOUTP/N
FREQUENCY
DETECT
PHASE
DETECT
Figure 1.
LOOP
FILTER
LOOP
FILTER
2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
VCO
04949-0-001
ADN2814 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 4
Output and Timing Specifications............................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
I2C Interface Timing and Internal Register Description........... 10
Terminology .................................................................................... 12
Jitter Specifications ......................................................................... 13
Jitter Generation .........................................................................13
Jitter Transfer............................................................................... 13
Jitter Tolerance............................................................................ 13
Functional Description.................................................................. 16
Frequency Acquisition............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust.................................................................................. 16
Loss of Signal (LOS) Detector .................................................. 16
Lock Detector Operation .......................................................... 16
Harmonic Detector.................................................................... 17
Squelch Mode ............................................................................. 17
I2C Interface ................................................................................ 18
Reference Clock (Optional) ...................................................... 18
Applications Information.............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application.......................................................... 23
Coarse Data Rate Readback Look-Up Table............................... 24
Outline Dimensions....................................................................... 26
Theory of Operation ...................................................................... 14
REVISION HISTORY
6/04—Revision PrA: Initial Version
Ordering Guide .......................................................................... 26
Rev. PrA | Page 2 of 28
Preliminary Technical Data ADN2814
SPECIFICATIONS
TA = T
unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS
QUANTIZER—AC CHARACTERISTICS
QUANTIZER—SLICE ADJUSTMENT
LOSS OF SIGNAL DETECT (LOS)
R
R
R
OC-1
R
R
LOSS OF LOCK DETECT (LOL)
ACQUISITION TIME
Lock to Data Mode OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms
12.3 Mb/s 40.0 ms
DATA RATE READBACK ACCURACY
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2814 input stage.
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
MAX
Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN – NIN 2.0 V
Input Common Mode Level
Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 x 10
DC-coupled (see Figure 26, Figure 27,
and Figure 28)
2.3 2.5 2.8 V
–10
10 6 mV p-p
Input Overdrive (see Figure 11) 5 3 mV p-p
Input Offset 500 µV
Input RMS Noise BER = 1 x 10
–10
290 µV rms
Data Rate 12.3 675 Mb/s
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100
Ω
Input Capacitance 0.65 pF
Gain SLICEP – SLICEN = ±0.5 V 0.08 0.1 0.12 V/V
Differential Control Voltage Input SLICEP – SLICEN –0.95 +0.95 V
Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset 1 mV
Loss of Signal Detect Range (see Figure 5) R
= 0 Ω 12 15 17 mV
Thresh
= 100 kΩ 2.0 3.0 4.0 mV
Thresh
Hysteresis (Electrical) GbE
= 0 Ω 5.0 6 7.0 dB
Thresh
= 100 kΩ 3.0 6 8.0 dB
Thresh
= 0 Ω 5.6 6 7.2 dB
Thresh
= 10 kΩ 2.0 4 6.7 dB
Thresh
LOS Assert Time DC-coupled2 500 ns
LOS De-Assert Time DC-coupled2 400 ns
VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL De-Assert With respect to nominal 250 ppm
LOL Response Time 12.3 Mb/s 4 ms
OC-12 1.0 µs
Optional Lock to REFCLK Mode 10.0 ms
Coarse Readback (See Table 13) 10 %
Rev. PrA | Page 3 of 28
ADN2814 Preliminary Technical Data
Parameter Conditions Min Typ Max Unit
Fine Readback In addition to REFCLK accuracy
Data rate < 20 Mb/s 200 ppm
Data rate > 20 Mb/s 100 ppm
POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT 106 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
JITTER SPECIFICATIONS
TA = T
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
30 Hz1 100 UI p-p
300 Hz1 44 UI p-p
25 kHz 2.5 UI p-p
250 kHz1 1.0 UI p-p
OC-3, 223 − 1 PRBS
30 Hz1 50 UI p-p
300 Hz1 24 UI p-p
6500 Hz 3.5 UI p-p
65 kHz 1.0 UI p-p
1
Jitter tolerance of the ADN2814 at these jitter frequencies is better than what the test equipment is able to measure.
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
MAX
Jitter Transfer BW OC-12 71 108 kHz
OC-3 23 35 kHz
Jitter Peaking OC-12 0 0.03 dB
OC-3 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.002 UI rms
0.01 0.019 UI p-p
OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms
0.01 0.011 UI p-p
Jitter Tolerance OC-12, 223 − 1 PRBS
Rev. PrA | Page 4 of 28
Preliminary Technical Data ADN2814
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
LVDS OUPUT CHARACTERISTICS
(CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing VSE (see Figure 3) 250 400 mV
Differential Output Swing V
Output Offset Voltage 1125 1200 1275 mV
Output Impedance Differential 100
LVDS Ouputs Timing
Rise Time 20% to 80% TBD ps
Fall Time 80% to 20% TBD ps
Setup Time TS (see Figure 2), OC12 800 ps
Hold Time TH (see Figure 2), OC12 800 ps
I2C INTERFACE DC CHARACTERISTICS LVCMOS
Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA
Output Low Voltage VOL, I
I2C INTERFACE TIMING (See Figure 10)
SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time between a Stop and a Start t
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 12.3 200 MHz
Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 µA
Input Low Current IIL, VIN = 0.4 V −5 µA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V
1
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
(see Figure 3) 500 800 mV
DIFF
Ω
= 3.0 mA 0.4 V
OL
600 ns
HIGH
1300 ns
LOW
600 ns
HD;STA
600 ns
SU;STA
100 ns
SU;DAT
300 ns
HD;DAT
600 ns
SU;STO
1300 ns
BUF
0 V
IL
VCC V
IH
1
300 ns
Rev. PrA | Page 5 of 28
ADN2814 Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = T
µF, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering 10 s) 300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47
MAX
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-LFCSP, 4-layer board with exposed paddle soldered to VEE
= 28°C/W.
θ
JA
Rev. PrA | Page 6 of 28
Preliminary Technical Data ADN2814
TIMING CHARACTERISTICS
CLKOUTP
T
T
S
H
DATAOUTP/N
04949-0-002
Figure 2. Output Timing
OUTP
OUTN
OUTP–OUTN
V
CML
V
0V
SE
V
DIFF
V
SE
04949-0-003
Figure 3. Single-Ended vs. Differential Output Specifications
Rev. PrA | Page 7 of 28
ADN2814 Preliminary Technical Data
*
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 TEST2
31 VCC
30 VEE
29 DATAOUTP
28 DATAOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
TEST1 1
VCC 2
VREF 3
NIN 4
PIN 5
SLICEP 6
SLICEN 7
VEE 8
THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
PIN 1
INDICATOR
ADN2814*
TOP VIEW
(Not to Scale)
VCC 12
THRADJ 9
REFCLKP 10
REFCLKN 11
CF2 14
VEE 13
CF1 15
LOL 16
24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
04949-0-004
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 TEST1 Connect to VCC.
2 VCC P Power for Limamp, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limamp, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss of Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I
21 SDA DI I
22 LOS DO Loss of Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I
24 VCC P Output Buffer, I
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
2
C Clock Input.
2
C Data Input.
2
C GND.
2
C Power.
Rev. PrA | Page 8 of 28
Preliminary Technical Data ADN2814
TYPICAL PERFORMANCE CHARACTERISTICS
16
14
12
10
8
TRIP POINT (mV p-p)
6
4
2
1 10 100
1k 10k 100k
R
(Ω)
TH
04949-0-005
Figure 5. LOS Comparator Trip Point Programming
Rev. PrA | Page 9 of 28
ADN2814 Preliminary Technical Data
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SLAVE ADDRESS [6...0]
1A500000X
MSB = 1 SET BY
PIN 19
Figure 6. Slave Address Configuration
R/W
CTRL.
0 = WR
1 = RD
04949-0-007
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
2
Figure 7. I
C Write Data Transfer
04949-0-008
S
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
A(M) = LACK OF ACKNOWLEDGE BY MASTER
2
Figure 8. I
C Read Data Transfer
04949-0-009
SDA
SCK
START BIT
S
SLAVE ADDRESS SUB ADDRESS DATA
SLADDR[4...0]
Figure 9. I
SUB ADDR[6...1] DATA[6...1]
2
C Data Transfer Timing
D0D7A0A7A5A6
STOP BIT
ACKACKWR ACK
P
04949-0-010
t
F
SDA
t
SCK
SSPS
LOW
t
HD;STA
t
R
t
HD;DAT
t
SU;DAT
Figure 10. I
t
F
t
HIGH
t
SU;STA
2
C Port Timing Diagram
t
HD;STA
t
SU;STO
t
BUF
t
R
04949-0-011
Rev. PrA | Page 10 of 28
Preliminary Technical Data ADN2814
Table 6. Internal Register Map1
Reg Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB
FREQ1 R 0x1 MSB LSB
FREQ2 R 0x2 0 MSB LSB
RATE R 0x3 COARSE_RD[8] MSB Coarse datarate readback COARSE_RD[1]
Datarate
measure
complete
x
Measure
datarate
COARSE_
RD[0] LSB
Lock to
reference
0 0 0
Squelch
mode
0
Coarse Rate
Readback LSB
Set
to 0
Set
to 0
Set
to 0
MISC R 0x4 x x
CTRLA W 0x8 F
CTRLB W 0x9
range Datarate/DIV_F
REF
Config
LOL
Reset
MISC[4]
LOS
status
System
reset
Static
LOL
0
LOL
status
ratio
REF
Reset
MISC[2]
CTRLC W 0x11 0 0 0 0 0 Config LOS
1
All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Datarate Measurement
LOS Status Static LOL LOL Status
Complete
D7 D6 D5 D4 D3 D2 D1 D0
x x 0 = No loss of signal 0 = Waiting for next LOL 0 = Locked 0 = Measuring datarate x COARSE_RD[0]
1 = Loss of signal 1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete
1
Table 8. Control Register, CTRLA
F
Range Datarate/Div_F
REF
Ratio Measure Datarate Lock to Reference
REF
D7 D6 D5 D4 D3 D2 D1 D0
0 0 12.3 MHz to 25 MHz 0 0 0 0 1 Set to 1 to measure datarate 0 = Lock to input data
0 1 25 MHz to 50 MHz 0 0 0 1 2 1 = Lock to reference clock
1 0 50 MHz to 100 MHz 0 0 1 0 4
1 1 100 MHz to 200 MHz n 2n
1 0 0 0 256
1
Where DIV_F
is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
REF
Table 9. Control Register, CTRLB
Config LOL Reset MISC[4] System Reset Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by
0 to reset ADN2814
Set
to 0
Write a 1 followed by
0 to reset MISC[2]
Table 10. Control Register, CTRLC
Config LOS Squelch Mode
D7 D6 D5 D4 D3 D2 D1 D0
0 = Active high LOS 0 = Squelch CLK and DATA Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0
1 = Active low LOS 1 = Squelch CLK or DATA
Rev. PrA | Page 11 of 28
ADN2814 Preliminary Technical Data
TERMINOLOGY
VREF
10mV p-p
ADN2814
PIN
NIN
50Ω
SCOPE
PROBE
VREF
+
QUANTIZER
–
50Ω
3kΩ
50Ω
VREF
2.5V
+
QUANTIZER
–
50Ω
3kΩ
04949-0-013
2.5V
04949-0-014
Input Sensitivity and Input Overdrive
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 11. For sufficiently large positive input voltage,
the output is always Logic 1 and, similarly for negative inputs,
the output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this range of input voltages, the output might be either 1 or 0, or
it might even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage.
Input overdrive is the magnitude of signal required to guarantee
−10
the correct logic level with 1 × 10
OUTPUT
1
0
SENSITIVITY
(2× OVERDRIVE)
Figure 11. Input Sensitivity and Input Overdrive
confidence level.
NOISE
OFFSET
OVERDRIVE
INPUT (V p-p)
04949-0-012
Single-Ended vs. Differential
AC coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a commonmode potential of ~2.5 V. Driving the ADN2814 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 12 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 12, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2814 quantizer typically has
6 mV p-p sensitivity.
SCOPE
PROBE
PIN
Figure 12. Single-Ended Sensitivity Measurement
Driving the ADN2814 differentially (see Figure 13), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2814 quantizer. However, the single-ended probe
measures only half the signal. The true quantizer input signal is
twice this value, because the other quantizer input is a complementary signal to the signal being observed.
5mV p-p
VREF
VREF
5mV p-p
Figure 13. Differential Sensitivity Measurement
LOS Response Time
LOS response time is the delay between removal of the input
signal and indication of loss of signal (LOS) at the LOS output,
Pin 22. When the inputs are dc-coupled, the LOS assert time of
the AD2814 is 500 ns typically and the de-assert time is 400 ns
typically,. In practice, the time constant produced by the ac
coupling at the quantizer input and the 50 Ω on-chip input
termination determines the LOS response time.
Rev. PrA | Page 12 of 28
Preliminary Technical Data ADN2814
JITTER SPECIFICATIONS
The ADN2814 CDR is designed to achieve the best bit-errorrate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2814 performance with respect to those specifications.
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms, and must be less than 0.1 UIp-p.
JITTER TRANSFER
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
signal (see Figure 14).
0.1
ACCEPTABLE
RANGE
JITTER GAIN (dB)
f
C
JITTER FREQUENCY (kHz)
Figure 14. Jitter Transfer Curve
SLOPE = –20dB/DECADE
04949-0-015
JITTER TOLERANCE
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 15).
15.00
SLOPE = –20dB/DECADE
1.50
0.15
INPUT JITTER AMPLITUDE (UI p-p)
f
0
Figure 15. SONET Jitter Tolerance Mask
f
1
JITTER FREQUENCY (kHz)
f
2
f
3
f
4
04949-0-016
Rev. PrA | Page 13 of 28
ADN2814 Preliminary Technical Data
THEORY OF OPERATION
The ADN2814 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
The delay- and phase-loops together track the phase of the
input data signal. For example, when the clock lags input data,
the phase detector drives the VCO to higher frequency, and also
increases the delay through the phase shifter; both these actions
serve to reduce the phase error between the clock and data. The
faster clock picks up phase, while the delayed data loses phase.
Because the loop filter is an integrator, the static phase error is
driven to zero.
X(s)
INPUT
DATA
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
Figure 16. ADN2814 PLL/DLL Architecture
Z(s)
psh
e(s)
d/sc
JITTER TRANSFER FUNCTION
Z(s)
=
X(s)
2
s
TRACKING ERROR TRANSFER FUNCTION
e(s)
=
X(s)
2
s
o/s
1/n
1
cn
n psh
+
s+ 1
do
o
2
s
d psh
do
s++
c
cn
JITTER PEAKING
IN ORDINARY PLL
04949-0-017
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase-loops together simultaneously provide
wide-band jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 16 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 17). This makes this circuit ideal for signal regenerator applications, where jitter peaking in a cascade of
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wide-band jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
ADN2814
JITTER GAIN (dB)
o
n psh
d psh
FREQUENCY (kHz)
c
Z(s)
X(s)
04949-0-018
Figure 17. ADN2814 Jitter Response vs. Conventional PLL
The delay- and phase-loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors, so the phase shifter remains close to the center of
its range and thus contributes little to the low frequency jitter
accommodation.
Rev. PrA | Page 14 of 28
Preliminary Technical Data ADN2814
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or the other.
The size of the VCO tuning range, therefore, has only a small
effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and so the phase shifter takes on
the burden of tracking the input jitter. The phase shifter range,
in UI, can be seen as a broad plateau on the jitter tolerance
curve. The phase shifter has a minimum range of 2 UI at all
data rates.
The gain of the loop integrator is small for high jitter
frequencies, so that larger phase differences are needed to make
the loop control voltage big enough to tune the range of the
phase shifter. Large phase errors at high jitter frequencies
cannot be tolerated. In this region, the gain of the integrator
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter
accommodation is determined by the eye opening of the input
data, the static phase error, and the residual loop jitter
generation. The jitter accommodation is roughly 0.5 UI in this
region. The corner frequency between the declining slope and
the flat region is the closed loop bandwidth of the delay-locked
loop, which is roughly 1.0 MHz at 622 Mb/s.
Rev. PrA | Page 15 of 28
ADN2814 Preliminary Technical Data
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2814 acquires frequency from the data over a range of
data frequencies from 12.3 Mb/s to 675 Mb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 12.3 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisition. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is de-asserted.
Once LOL is de-asserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
ADN2814 drops below the programmed LOS threshold, the
output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.
The LOS detector’s response time is ~500 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
The LOS pin defaults to active high. However, by setting Bit
CTRLC[2] to 1, the LOS pin is configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means
that, if the input level drops below the programmed LOS
threshold causing the LOS pin to assert, the LOS pin is not deasserted until the input level has increased to 6 dB (2×) above
the LOS threshold (see Figure 18).
LOS OUTPUT
)
DIFF
INPUT LEVEL
The frequency loop requires a single external capacitor between
CF1 and CF2, Pins 14 and 15. A 0.47 µF ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 µF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 uF capacitor should be greater than 300 MΩ.
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN), which
are internally terminated with 50 Ω to an on-chip voltage
reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common mode voltage remains above 2.5 V (see
Figure 26, Figure 27, and Figure 28 in the Applications
Information section). Input offset is factory trimmed to achieve
better than 6 mV typical sensitivity with minimal drift. The
limiting amplifier can be driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/N inputs. If no adjustment of the slice
level is needed, SLICEP/N should be tied to VEE. The gain of
the slice adjustment is ~0.1 V/V.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point-versusresistor value is illustrated in Figure 5. If the input level to the
HYSTERESIS
INPUT VOLTAGE (V
Figure 18. LOS Detector Hysteresis
LOS THRESHOLD
t
04949-0-019
The LOS detector and the SLICE level adjust can be used
simultaneously on the ADN2814. This means that any offset
added to the input signal by the SLICE adjust pins does not
affect the LOS detector’s measurement of the absolute input
level.
LOCK DETECTOR OPERATION
The lock detector on the ADN2814 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2814 is a continuous rate CDR that
locks onto any data rate from 12.3 Mb/s to 675 Mb/s without
the use of a reference clock as an acquisition aid. In this mode,
the lock detector monitors the frequency difference between the
VCO and the input data frequency, and de-asserts the loss of
lock signal, which appears on LOL Pin 16, when the VCO is
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
also acquires phase lock. Once locked, if the input frequency
error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which
begins a new frequency acquisition starting at the lowest point
in the VCO operating range, 12.3 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
Rev. PrA | Page 16 of 28
Preliminary Technical Data ADN2814
within 250 ppm frequency error. This hysteresis is shown in
Figure 19.
LOL
1
–1000
Figure 19. Transfer Function of LOL
0–250 250 1000 f
VCO
(ppm)
ERROR
04949-0-020
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2814 VCO. Lock to reference mode is enabled by
setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits in order to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss of lock signal, which appears on the LOL Pin 16, is deasserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
re-acquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 19.
Static LOL Mode
The ADN2814 implements a static LOL feature, which indicates
if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2814 regains lock, until the static LOL
2
bit is manually reset. The I
C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2814 has reacquired lock to a new data rate. This bit can be reset by writing
2
a 1 followed by 0 to I
C Register Bit CTRLB[6]. Once reset, the
MISC[4] bit remains de-asserted until another loss of lock
condition occurs.
2
Writ i ng a 1 to I
C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2814 is in acquisition mode and de-asserts when the
ADN2814 has re-acquired lock.
HARMONIC DETECTOR
The ADN2814 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-12,
622.08Mb/s, to an OC-3, 155.52 Mb/s bit stream, this could be
perceived as a valid OC-12 bit stream, because the OC-3 data
pattern is exactly 4× slower than the OC-12 pattern. So, if the
change in data rate is instantaneous, a 101 pattern at OC-3
would be perceived by the ADN2814 as a 111100001111 pattern
at OC-12. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2814 implements a harmonic detector that automatically identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2814 automatically locks onto the new data rate, and the
LOL pin is de-asserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate the VCO is currently locked
onto, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2814 automatically
locks onto the new data rate.
The time to detect lock to harmonic is
16,384 × (T
d
/ρ)
where:
1/T
is the new data rate. For example, if the data rate is
d
switched from OC-12 to OC-3, then T
= 1/155.52 MHz.
d
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2814 is placed in lock to reference mode, the
harmonic detector is disabled.
SQUELCH MODE
Two squelch modes are available with the ADN2814. Squelch
DATAOUT AND CLKOUT mode is selected when CTRLC[1] =
0 (default mode). In this mode, when the squelch input, Pin 27,
is driven to a TTL high state, both the clock and data outputs
are set to the zero state to suppress downstream processing. If
the squelch function is not required, Pin 27 should be tied to
VEE.
Squelch DATAOUT OR CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
Rev. PrA | Page 17 of 28
ADN2814 Preliminary Technical Data
I2C INTERFACE
The ADN2814 supports a 2-wire, I2C compatible, serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2814 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave address bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word sets either a read or write
operation (see Figure 6). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establishing a start condition, defined by a high to low transition on
SDA while SCK remains high. This indicates that an
address/data stream follows. All peripherals respond to the start
condition and shift the next eight bits (the 7-bit address and the
R/W bit). The bits are transferred from MSB to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCK lines
waiting for the start condition and correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on
the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first
byte means that the master reads information from the
peripheral.
The ADN2814 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. The ADN2814 has 8 subaddresses to enable
the user-accessible internal registers (see Table 1 through
Table 7). It, therefore, interprets the first byte as the device
address and the second byte as the starting subaddress.
Autoincrement mode is supported, allowing data to be read
from or written to the starting subaddress and each subsequent
address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCK high
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2814 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
reading back in autoincrement mode, then the highest subaddress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a
read. In a no-acknowledge condition, the SDATA line is not
pulled low on the ninth pulse. See Figure 7 and Figure 8 for
sample read and write data transfers and Figure 9 for a more
detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2814. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 20 through Figure 22 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical
and 100 ppm accuracy is sufficient.
ADN2814
REFCLKP
10
11
REFCLKN
100kΩ
Figure 20. Differential REFCLK Configuration
VCC
REFCLKP
CLK
OSC
OUT
REFCLKN
Figure 21. Single-Ended REFCLK Configuration
VCC
REFCLKP
NC
REFCLKN
Figure 22. No REFCLK Configuration
ADN2814
ADN2814
10
11
100kΩ
100kΩ
BUFFER
100kΩ
100kΩ
BUFFER
100kΩ
BUFFER
VCC/2
VCC/2
VCC/2
04949-0-021
04949-0-022
04949-0-023
Rev. PrA | Page 18 of 28
Preliminary Technical Data ADN2814
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2814 to lock onto data, or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive, because,
in the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
2
Lock to reference mode is enabled by writing a 1 to I
C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
2
writing a 1 to I
C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2814 locks onto a frequency derived
from the reference clock according to the following equation:
Data Rate/2
CTRLA[5:2]
= REFCLK/2
CTRLA[7:6]
The user must know exactly what the data rate is, and provide a
reference clock that is a function of this rate. The ADN2814 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 12.3 MHz and
200 MHz. By default, the ADN2814 expects a reference clock of
between 12.3 MHz and 25 MHz. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
user needs to configure the ADN2814 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio
00 12.3 to 25 0000 1
01 25 to 50 0001 2
10 50 to 100 n 2n
11 100 to 200 1000 256
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
, where DIV_F
REF
represents the
REF
divided-down reference referred to the 12.3 MHz to 25 MHz
band. For example, if the reference clock frequency was
38.88 MHz and the input data rate was 622.08 Mb/s, then
CTRLA[7:6] would be set to [01] to give a divided-down
reference clock of 19.44 MHz. CTRLA[5:2] would be set to
[0101], that is, 5, because
5
622.08 Mb/s/19.44 MHz = 2
In this mode, if the ADN2814 loses lock for any reason, it
relocks onto the reference clock and continues to output a stable
clock.
While the ADN2814 is operating in lock to reference mode, if
the user ever changes the reference frequency, the F
(CTRLA[7:6]), or the F
ratio (CTRLA[5:2]), this must be
REF
REF
range
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock to reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2814 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2814 data rate measurement. For example, if a 100-ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
The reference clock can range from 12.3 MHz and 200 MHz.
The ADN2814 expects a reference clock between 12.3 MHz and
25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2814 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2814. This bit is level
sensitive and does not need to be reset to perform subsequent
frequency measurements.
Step 2: Reset MISC[2] by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
Step 3: Read back MISC[2]. If it is 0, then the measurement is
not complete. If it is 1, then the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Step 4: Read back the data rate from registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
Rev. PrA | Page 19 of 28
ADN2814 Preliminary Technical Data
(
)
Use the following equation to determine the data rate:
DATARATE
()
[]
fFREQf
×=
REFCLK
+
2/0..22
)_14(
RATESEL
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),
FREQ1[7:0], and FREQ0[7:0] (LSByte).
Table 12.
D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0
FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]
f
is the data rate (Mb/s).
DATA RATE
f
is the REFCLK frequency (MHz).
REFCLK
SEL_RATE is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting would be [01],
because the reference frequency would fall into the 25 MHz to
50 MHz range. Assume for this example that the input data rate
is 622.08 Mb/s (OC12). After following Steps 1 through 4, the
value that is read back on FREQ[22:0] = 0x9B851, which is
equal to 637 x 10
()
3
. Plugging this value into the equation yields
)114(
+
b/s08.6222/6e3237e36
M=×
Additional Features Available via the I2C Interface
Coarse Data Rate Readback
The data rate can be read back over the I2C interface to
approximately +
10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is de-asserted. The 8 MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 13 provides coarse data rate readback to within ±10%.
LOS Configuration
The LOS detector output, LOS Pin 22, can be configured to be
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures the
LOS pin to be active low when a loss of signal condition is
detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
2
C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2814 in the
operating mode that it was previously programmed to in
registers CTRL[A], CTRL[B], and CTRL[C].
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Steps 2 through 4 to read back the new data rate.
Note: A data rate readback is valid only if LOL is low. If LOL is
high, the data rate readback is invalid.
Rev. PrA | Page 20 of 28
Preliminary Technical Data ADN2814
(
=
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias
so that solder does not leak
through the vias during reflow.
Use of a 22 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2814 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to the schematic in Figure
23 for recommended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
)
pFε88.0 A/dC
plane
r
where:
ε
is the dielectric constant of the PCB material.
r
A is the area of the overlap of power and GND planes (cm
2
).
d is the separation between planes (mm).
For FR-4,
ε
= 4.4 mm and 0.25 mm spacing, C ~15 pF/cm
r
2
.
VCC
0.1µF
VCC
TIA
+
1nF
0.1µF
50Ω
50Ω
0.1µF22µF 1nF
SLICEP
SLICEN
C
IN
TEST1
VCC
VREF
NIN
PIN
VEE
VCC
R
0.1µF
2
T
S
E
T
1
2
3
4
5
6
7
8
J
D
A
R
H
T
TH
Figure 23. Typical ADN2814 Applications Circuit
50Ω TRANSMISSION LINES
N
P
T
T
H
P
U
U
T
C
L
U
O
O
E
A
A
O
U
T
T
C
E
K
A
A
L
Q
C
E
D
S
V
D
V
1
2
3
3
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
0
9
1
P
K
L
C
F
E
R
1nF
C
9
8
7
0
2
2
2
3
1
2
3
4
1
1
1
1
1
2
E
N
C
F
F
E
K
C
C
C
V
L
V
C
F
E
R
NC
0.47µF ±20%
>300MΩ INSULATION RESISTANCE
DATAOUTP
DATAOUTN
CLKOUTP
N
T
U
O
K
L
C
6
5
2
2
VCC
24
VEE
23
LOS
22
SDA
21
SCK
20
SADDR5
19
VCC
18
VEE
17
5
6
1
L
O
L
1nF
1
µC
CLKOUTN
VCC
0.1µF1nF
2
I
C CONTROLLER
2
I
C CONTROLLER
VCC
0.1µF
µC
04949-0-031
Rev. PrA | Page 21 of 28
ADN2814 Preliminary Technical Data
T
C
=
(
(
)
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also
REFCLKP, REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/N and
DATAOUTP/N output traces to be matched in length to avoid
skew between the differential traces.
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 24).
A 0.1 µF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
VCC
ADN2814
C
50Ω
IN
PIN
TIA
Figure 24. ADN2814 AC-Coupled Input Configuration
50Ω
0.1µF
C
IN
NIN
50Ω
50Ω
VREF
3kΩ
2.5V
04949-0-026
Soldering Guidelines for Chip Scale Package
The lands on the 32 LFCSP are rectangular. The printed circuit
board pad for these should be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land should be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
so that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2814 must be chosen
such that the device works properly over the full range of data
rates used in the application. When choosing the capacitors, the
time constant formed with the two 50 Ω resistors in the signal
path must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 25), causing patterndependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection may
require some trade-offs between droop and PDJ.
Example: Assuming that 2% droop can be tolerated, then the
maximum differential droop is 4%. Normalizing to V
Droop = ∆ V = 0.04 V = 0.5 V
(1 − e
pp
–t/τ
) ; therefore, τ = 12t
:
pp
where:
τ is the RC time constant (C is the ac coupling capacitor, R =
100 Ω seen by C).
t is the total discharge time, which is equal to n
Τ
.
n is the number of CIDs.
T is the bit period.
The capacitor value can then be calculated by combining the
equations for τ and t:
/12
Rn
Once the capacitor value is selected, the PDJ can be
approximated as
pspp
nT/RC
etPDJ
−=
r
6.0/15.0
)
−
where:
PDJ
is the amount of pattern-dependent jitter allowed;
pspp
< 0.01 UI p-p typical.
t
is the rise time, which is equal to 0.22/BW,
r
where BW ~ 0.7 (bit rate).
Note that this expression for t
is accurate only for the inputs.
r
The output rise time for the ADN2814 is ~100 ps regardless of
data rate.
Rev. PrA | Page 22 of 28
Preliminary Technical Data ADN2814
VCC
C
IN
V1
TIA LIMAMP
1
V1
V1b
V2
V2b
V
DIFF
V
= V2–V2b
DIFF
VTH = ADN2814 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2814. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
V1b
V2
C
IN
V2b
234
PIN
50Ω
50Ω
NIN
ADN2814
+
V
REF
–
CDR
C
OUT
C
OUT
DATAOUTP
DATAOUTN
VREF
VTH
04949-0-027
Figure 25. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2814 can also be dc-coupled. This might
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2814 are dc-coupled, care must be taken not
to violate the input range and common-mode level requirements of the ADN2814 (see Figure 26 through Figure 28). If dc
coupling is required, and the output levels of the TIA do not
adhere to the levels shown in Figure 27, then level shifting
and/or an attenuator must be between the TIA outputs and the
ADN2814 inputs.
VCC
PIN
NIN
50Ω
VREF
ADN2814
50Ω
3kΩ
2.5V
04949-0-028
50Ω
TIA
50Ω
0.1µF
Figure 26. DC-Coupled Application
PIN
INPUT (V)
NIN
VPP = PIN – NIN = 2 × VSE = 10mV AT SENSITIVITY
= 5mV MIN
V
SE
= 2.3V MIN
V
CM
(DC-COUPLED)
04949-0-029
Figure 27. Minimum Allowed DC-Coupled Input Levels
PIN
INPUT (V)
NIN
VPP = PIN – NIN = 2 × VSE = 2.0V MAX
V
= 1.0V MAX
SE
V
CM
(DC-COUPLED)
= 2.3V
04949-0-030
Figure 28. Maximum Allowed DC-Coupled Input Levels
Rev. PrA | Page 23 of 28
ADN2814 Preliminary Technical Data
COARSE DATA RATE READBACK LOOK-UP TABLE
Code is the 9-bit value read back from COARSE_RD[8:0].
Table 13. Look-Up Table
Code F
0 5.1934e+06
1 5.1930e+06
2 5.2930e+06
3 5.3989e+06
4 5.5124e+06
5 5.6325e+06
6 5.7612e+06
7 5.8995e+06
8 6.0473e+06
9 6.2097e+06
10 6.3819e+06
11 6.5675e+06
12 6.7688e+06
13 6.9874e+06
14 7.2262e+06
15 7.4863e+06
16 7.4139e+06
17 7.4135e+06
18 7.5606e+06
19 7.7173e+06
20 7.8852e+06
21 8.0633e+06
22 8.2548e+06
23 8.4586e+06
24 8.6784e+06
25 8.9180e+06
26 9.1736e+06
27 9.4481e+06
28 9.7464e+06
29 1.0068e+07
30 1.0417e+07
31 1.0791e+07
32 1.0387e+07
33 1.0386e+07
34 1.0586e+07
35 1.0798e+07
36 1.1025e+07
37 1.1265e+07
38 1.1522e+07
39 1.1799e+07
40 1.2095e+07
41 1.2419e+07
42 1.2764e+07
43 1.3135e+07
44 1.3538e+07
45 1.3975e+07
46 1.4452e+07
47 1.4973e+07
MID
Code F
48 1.4828e+07
49 1.4827e+07
50 1.5121e+07
51 1.5435e+07
52 1.5770e+07
53 1.6127e+07
54 1.6510e+07
55 1.6917e+07
56 1.7357e+07
57 1.7836e+07
58 1.8347e+07
59 1.8896e+07
60 1.9493e+07
61 2.0136e+07
62 2.0833e+07
63 2.1582e+07
64 2.0774e+07
65 2.0772e+07
66 2.1172e+07
67 2.1596e+07
68 2.2049e+07
69 2.2530e+07
70 2.3045e+07
71 2.3598e+07
72 2.4189e+07
73 2.4839e+07
74 2.5527e+07
75 2.6270e+07
76 2.7075e+07
77 2.7950e+07
78 2.8905e+07
79 2.9945e+07
80 2.9655e+07
81 2.9654e+07
82 3.0242e+07
83 3.0869e+07
84 3.1541e+07
85 3.2253e+07
86 3.3019e+07
87 3.3834e+07
88 3.4714e+07
89 3.5672e+07
90 3.6694e+07
91 3.7792e+07
92 3.8985e+07
93 4.0273e+07
94 4.1666e+07
95 4.3164e+07
MID
Code F
96 4.1547e+07
97 4.1544e+07
98 4.2344e+07
99 4.3191e+07
100 4.4099e+07
101 4.5060e+07
102 4.6090e+07
103 4.7196e+07
104 4.8378e+07
105 4.9678e+07
106 5.1055e+07
107 5.2540e+07
108 5.4150e+07
109 5.5899e+07
110 5.7810e+07
111 5.9890e+07
112 5.9311e+07
113 5.9308e+07
114 6.0485e+07
115 6.1739e+07
116 6.3081e+07
117 6.4506e+07
118 6.6038e+07
119 6.7669e+07
120 6.9427e+07
121 7.1344e+07
122 7.3388e+07
123 7.5585e+07
124 7.7971e+07
125 8.0546e+07
126 8.3333e+07
127 8.6328e+07
128 8.3095e+07
129 8.3087e+07
130 8.4689e+07
131 8.6383e+07
132 8.8198e+07
133 9.0120e+07
134 9.2179e+07
135 9.4392e+07
136 9.6757e+07
137 9.9356e+07
138 1.0211e+08
139 1.0508e+08
140 1.0830e+08
141 1.1180e+08
142 1.1562e+08
143 1.1978e+08
MID
Code F
144 1.1862e+08
145 1.1862e+08
146 1.2097e+08
147 1.2348e+08
148 1.2616e+08
149 1.2901e+08
150 1.3208e+08
151 1.3534e+08
152 1.3885e+08
153 1.4269e+08
154 1.4678e+08
155 1.5117e+08
156 1.5594e+08
157 1.6109e+08
158 1.6667e+08
159 1.7266e+08
160 1.6619e+08
161 1.6617e+08
162 1.6938e+08
163 1.7277e+08
164 1.7640e+08
165 1.8024e+08
166 1.8436e+08
167 1.8878e+08
168 1.9351e+08
169 1.9871e+08
170 2.0422e+08
171 2.1016e+08
172 2.1660e+08
173 2.2360e+08
174 2.3124e+08
175 2.3956e+08
176 2.3724e+08
177 2.3723e+08
178 2.4194e+08
179 2.4695e+08
180 2.5233e+08
181 2.5802e+08
182 2.6415e+08
183 2.7067e+08
184 2.7771e+08
185 2.8538e+08
186 2.9355e+08
187 3.0234e+08
188 3.1188e+08
189 3.2218e+08
190 3.3333e+08
191 3.4531e+08
MID
Rev. PrA | Page 24 of 28
Preliminary Technical Data ADN2814
Code F
192 3.3238e+08
193 3.3235e+08
194 3.3876e+08
195 3.4553e+08
196 3.5279e+08
197 3.6048e+08
198 3.6872e+08
199 3.7757e+08
200 3.8703e+08
MID
Code F
MID
201 3.9742e+08
202 4.0844e+08
203 4.2032e+08
204 4.3320e+08
205 4.4719e+08
206 4.6248e+08
207 4.7912e+08
208 4.7449e+08
209 4.7447e+08
Code F
MID
210 4.8388e+08
211 4.9391e+08
212 5.0465e+08
213 5.1605e+08
214 5.2831e+08
215 5.4135e+08
216 5.5542e+08
217 5.7075e+08
218 5.8711e+08
Code F
MID
219 6.0468e+08
220 6.2377e+08
221 6.4437e+08
222 6.6666e+08
223 6.9062e+08
224 6.6476e+08
225 6.6470e+08
226 6.7751e+08
227 6.9106e+08
Rev. PrA | Page 25 of 28
ADN2814 Preliminary Technical Data
OUTLINE DIMENSIONS
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
PIN 1
INDICATOR
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
0.60 MAX
0.50
4.75
BSC SQ
0.05 MAX
0.02 NOM
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
BSC
0.50
0.40
0.30
COPLANARITY
0.08
0.60 MAX
25
24
17
16
BOTTOM
VIEW
32
9
1
8
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
Figure 29. 32-Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN2814XCPZ −40°C to 85°C Pb Free 32-LFCSP CP-32
Rev. PrA | Page 26 of 28
Preliminary Technical Data ADN2814
NOTES
Rev. PrA | Page 27 of 28
ADN2814 Preliminary Technical Data
PR04949-0-8/04(PrA)
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Rev. PrA | Page 28 of 28
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