ANALOG DEVICES ADN2813 Service Manual

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Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and

Data Recovery IC with Integrated Limiting Amp

FEATURES

Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/

generation/tolerance
Quantizer sensitivity: 3.3 mV typ
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator

2

C® interface to access optional features

I
Single-supply operation: 3.3 V
Low power: 450 mW typ
5 mm × 5 mm 32-lead LFCSP, Pb free

APPLICATIONS

SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers

ADN2813

GENERAL DESCRIPTION

The ADN2813 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati­cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.

The receiver front-end, loss-of-signal (LOS) detector circuit
indicates when the input signal level has fallen below a user­adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.

The ADN2813 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.

FUNCTIONAL BLOCK DIAGRAM

REFCLKP/N
(OPTIONAL)

SLICEP/N

PIN

NIN

VREF

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

QUANTIZER

LOS

DETECT

PHASE

SHIFTER

DATA

RE-TIMING

2

DATAOUTP/NLOSTHRADJ CLKOUTP/N

LOL

FREQUENCY

DETECT

PHASE

DETECT

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

LOOP

FILTER

LOOP

FILTER

2

VCC VEECF1 CF2

ADN2813

VCO

04951-0-001

ADN2813

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 14

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Jitter Specifications....................................................................... 4

Output and Timing Specifications............................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

2

I

C Interface Timing and Internal Register Description........... 10

Te r mi n ol o g y .................................................................................... 12

Functional Description .................................................................. 16

Frequency Acquisition............................................................... 16

Limiting Amplifier..................................................................... 16

Slice Adjust.................................................................................. 16

Loss-of-Signal (LOS) Detector................................................. 16

Lock Detector Operation.......................................................... 16

Harmonic Detector .................................................................... 17

SQUELCH Mode........................................................................ 18

2

I

C Interface ................................................................................ 18

Reference Clock (Optional) ...................................................... 18

Applications Information.............................................................. 21

PCB Design Guidelines ............................................................. 21

DC-Coupled Application .......................................................... 23

Coarse Data Rate Readback Look-Up Table............................... 24

Outline Dimensions ....................................................................... 26

Jitter Specifications......................................................................... 13

REVISION HISTORY

9/05—Revision 0: Initial Version

Ordering Guide .......................................................................... 26

Rev. 0 | Page 2 of 28

ADN2813

SPECIFICATIONS

TA = T
unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

QUANTIZER—AC CHARACTERISTICS

QUANTIZER—SLICE ADJUSTMENT

LOSS-OF-SIGNAL (LOS) DETECT

LOSS-OF-LOCK (LOL) DETECT

ACQUISITION TIME

DATA RATE READBACK ACCURACY

Data rate ≤ 20 Mb/s 200 ppm
Data rate > 20 Mb/s 100 ppm

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 2.0 V
Input Common-Mode Level DC-coupled (see Figure 27, Figure 28, and Figure 29) 2.3 2.5 2.8 V
Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10

–10

6 3.3 mV p-p
Input Offset 500 μV
Input RMS Noise BER = 1 × 10

–10

290 μV rms

Data Rate 10 1250 Mb/s
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF

Gain SLICEP – SLICEN = ±0.5 V 0.10 0.11 0.13 V/V
Differential Control Voltage Input SLICEP – SLICEN −0.95 +0.95 V
Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset 1 mV

Loss-of-Signal Detect Range (see Figure 6) R
R

= 0 Ω 14 16.5 19 mV

THRESH

= 100 kΩ 2.3 3.5 4.7 mV

THRESH

Hysteresis (Electrical) GbE
R
R

= 0 Ω 6.4 7.2 8.0 dB

THRESH

= 100 kΩ 4.6 6.2 7.8 dB

THRESH

OC-1
R
R
LOS Assert Time DC-coupled
LOS Deassert Time DC-coupled

= 0 Ω 5.5 6.6 7.7 dB

THRESH

= 10 kΩ 3.1 5.4 7.7 dB

THRESH

2

2

500 ns

400 ns

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time 10 Mb/s 5 ms
OC-12 200 μs
GbE 200 μs

Lock-to-Data Mode GbE 1.5 ms
OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms
10 Mb/s 40.0 ms
Optional Lock to REFCLK Mode 20.0 ms

Coarse Readback See Tab le 13 10 %
Fine Readback In addition to REFCLK accuracy

Rev. 0 | Page 3 of 28

ADN2813

Parameter Conditions Min Typ Max Unit

POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 1.25 Gb/s 139 155 mA
OPERATING TEMPERATURE RANGE –40 +85 °C

1

PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.

2

When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the

ADN2813 input stage.

JITTER SPECIFICATIONS

TA = T
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

30 Hz
300 Hz
25 kHz 2.5 UI p-p
250 kHz
OC-3, 223 − 1 PRBS
30 Hz
300 Hz
6500 Hz 3.5 UI p-p
65 kHz

1

Jitter tolerance of the ADN2813 at these jitter frequencies is better than what the test equipment is able to measure.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Jitter Transfer BW OC-12 75 130 kHz
OC-3 26 42 kHz
Jitter Peaking OC-12 0 0.03 dB
OC-3 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms

0.011 0.026 UI p-p
OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms

0.005 0.010 UI p-p
Jitter Tolerance 1 GbE, IEEE 802.3
637 kHz 0.749 UI p-p
OC-12, 223 − 1 PRBS

1

1

1

1

1

1

100 UI p-p
44 UI p-p

1.0 UI p-p

50 UI p-p

23.5 UI p-p

1.0 UI p-p

Rev. 0 | Page 4 of 28

ADN2813

OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

LVDS OUTPUT CHARACTERISTICS

(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)

Output Voltage High VOH (see Figure 3), 655 Mb/s 1475 mV
Output Voltage Low VOL (see Figure 3), 655 Mb/s 925 mV
Differential Output Swing VOD (see Figure 3), 655 Mb/s 250 320 400 mV
Differential Output Swing VOD (see Figure 3), 1.25 Gb/s 240 300 400
Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω

LVDS Outputs Timing GbE

Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), GbE 360 400 440 ps
Hold Time TH (see Figure 2), GbE 360 400 440 ps

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input High Voltage V
Input Low Voltage V

IH

IL

Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, I

= 3.0 mA 0.4 V

OL

I2C INTERFACE TIMING See Figure 11

SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/T
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t

HIGH

LOW

HD;STA

SU;STA

SU;DAT

HD;DAT

F

SU;STO

BUF

REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN
V
V

IL

IH

Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage V
Input Low Voltage V

IH

IL

Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V

1

Cb = total capacitance of one bus line in pF. If mixed with Hs mode devices, faster fall times are allowed.

0.7 VCC V

0.3 VCC V

600 ns
1300 ns
600 ns
600 ns
100 ns
300 ns
20 + 0.1 Cb

1

300 ns
600 ns
1300 ns

0 V
VCC V

2.0 V

0.8 V

Rev. 0 | Page 5 of 28

ADN2813

ABSOLUTE MAXIMUM RATINGS

= T

MIN

to T

T

A

0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted.

Table 4.

Parameter Rating

Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF =

MAX

THERMAL CHARACTERISTICS

Thermal Resistance

32-LFCSP, 4-layer board with exposed paddle soldered to VEE,
θ

= 28°C/W.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

ADN2813

TIMING CHARACTERISTICS

CLKOUTP

T

T

S

H

DATAOUTP/N

04951-0-002

Figure 2. Output Timing

DIFFERENTIAL CLKOUTP/N, DATAOUTP/N

V

OH

V

OS

V

OL

|VOD|

04951-0-032

Figure 3. Differential Output Specifications

5mA

R

100Ω

LOAD

100Ω

V

DIFF

5mA

SIMPLIFIED LVDS

OUTPUT STAGE

Figure 4. Differential Output Stage

Rev. 0 | Page 7 of 28

04951-0-033

ADN2813

*

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 TEST2

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

TEST1 1

VCC 2

VREF 3

NIN 4

PIN 5
SLICEP 6
SLICEN 7

VEE 8

THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.

PIN 1
INDICATOR

ADN2813*

TOP VIEW

(Not to Scale)

VCC 12

THRADJ 9

REFCLKP 10

REFCLKN 11

CF2 14

VEE 13

CF1 15

LOL 16

24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE

04951-0-004

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type

1 TEST1 Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limiting Amplifier, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 LOS DO Loss-of-Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND.

1

Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

1

Description

Rev. 0 | Page 8 of 28

ADN2813

TYPICAL PERFORMANCE CHARACTERISTICS

16

14

12

10

8

TRIP POINT (mV p-p)

6

4

2

1 10 100

1k 10k 100k

R

(Ω)

TH

04951-0-005

Figure 6. LOS Comparator Trip Point Programming

Rev. 0 | Page 9 of 28