Analog Devices ADN2812 Datasheet

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and

S

FEATURES

Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds SONET requirements for jitter transfer/

generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator

2

C™ interface to access optional features

I
Single-supply operation: 3.3 V
Low power: 750 mW typical
5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers

FUNCTIONAL BLOCK DIAGRAM

Data Recovery IC with Integrated Limiting Amp

ADN2812

PRODUCT DESCRIPTION

The ADN2812 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automati­cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.

The receiver front end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user­adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.

The ADN2812 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.

REFCLKP/N
(OPTIONAL)

LOL

VCC VEECF1 CF2

LICEP/N

PIN

NIN

VREF

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

2

QUANTIZER

LOS

DETECT

PHASE

SHIFTER

DATA

RE-TIMING

DATAOUTP/NLOSTHRADJ CLKOUTP/N

FREQUENCY

DETECT

2

Figure 1.

LOOP

FILTER

PHASE

DETECT

LOOP

FILTER

2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

VCO

04228-0-001

ADN2812

TABLE OF CONTENTS

Specifications..................................................................................... 3

Jitter Specifications....................................................................... 4

Output and Timing Specifications ............................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

2

I

C Interface Timing and Internal Register Description........... 10

Terminology .................................................................................... 12

Jitter Specifications ......................................................................... 13

Jitter Generation .........................................................................13

Jitter Transfer............................................................................... 13

Jitter Tolerance............................................................................ 13

Functional Description.................................................................. 16

Frequency Acquisition............................................................... 16

Limiting Amplifier ..................................................................... 16

Slice Adjust.................................................................................. 16

Loss of Signal (LOS) Detector .................................................. 16

Lock Detector Operation .......................................................... 16

Harmonic Detector.................................................................... 17

Squelch Mode ............................................................................. 17

I2C Interface ............................................................................... 18

Reference Clock (Optional) ...................................................... 18

Applications Information.............................................................. 21

PCB Design Guidelines ............................................................. 21

DC-Coupled Application .......................................................... 23

Coarse Data Rate Readback Look-Up Table............................... 24

Outline Dimensions....................................................................... 26

Theory of Operation ...................................................................... 14

REVISION HISTORY

Revision 0: Initial Version

Ordering Guide .......................................................................... 26

Rev. 0 | Page 2 of 28

ADN2812

SPECIFICATIONS

TA = T
unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

QUANTIZER—AC CHARACTERISTICS

QUANTIZER—SLICE ADJUSTMENT

LOSS OF SIGNAL DETECT (LOS)

R

R
R
OC-1
R
R

LOSS OF LOCK DETECT (LOL)

OC-48 1.0 µs
ACQUISITION TIME

OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms

12.3 Mb/s 40.0 ms

1

PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.

2

When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the

ADN2812 input stage.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,

MAX

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN – NIN 2.0 V

Input Common Mode Level

DC-coupled (see Figure 28, Figure 29,
and Figure 30)

Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 x 10

2.3 2.5

–10

10 6 mV p-p

2.8
V

Input Overdrive (see Figure 12) 5 3 mV p-p
Input Offset 500 µV
Input RMS Noise BER = 1 x 10

–10

290 µV rms

Data Rate 12.3 2700 Mb/s
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100

Ω

Input Capacitance 0.65 pF

Gain SLICEP – SLICEN = ±0.5 V 0.08 0.1 0.12 V/V
Differential Control Voltage Input SLICEP – SLICEN –0.95 +0.95 V
Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset 1 mV

Loss of Signal Detect Range (see Figure 5) R

= 0 Ω 12 15 17 mV

Thresh

= 100 kΩ 2.0 3.0 4.0 mV

Thresh

Hysteresis (Electrical) OC-48

= 0 Ω 5.6 6 7.2 dB

Thresh

= 100 kΩ 3.7 6 8.4 dB

Thresh

= 0 Ω 5.6 6 7.2 dB

Thresh

= 10 kΩ 2.0 4 6.7 dB

Thresh

LOS Assert Time DC-coupled2 500 ns
LOS De-Assert Time DC-coupled2 400 ns

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL De-Assert With respect to nominal 250 ppm
LOL Response Time 12.3 Mb/s 4 ms
OC-12 1.0 µs

Lock to Data Mode OC-48 1.3 ms

Optional Lock to REFCLK Mode 10.0 ms

Rev. 0 | Page 3 of 28

ADN2812

Parameter Conditions Min Typ Max Unit

DATA RATE READBACK ACCURACY

Coarse Readback (See Table 13) 10 %
Fine Readback In addition to REFCLK accuracy
Data rate < 20 Mb/s 200 ppm

Data rate > 20 Mb/s 100 ppm
POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT 219 235 259 mA
OPERATING TEMPERATURE RANGE –40 +85 °C

JITTER SPECIFICATIONS

TA = T
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

600 Hz 70 92 UI p-p
6 kHz 19 45 UI p-p
100 kHz 3.8 5 UI p-p
1 MHz 0.75 1 UI p-p
20 MHz 0.4 0.6 UI p-p
OC-12, 223 − 1 PRBS
30 Hz3 100 UI p-p
300 Hz1 44 UI p-p
25 kHz 2.5 UI p-p
250 kHz1 1.0 UI p-p
OC-3, 223 − 1 PRBS
30 Hz1 50 UI p-p
300 Hz1 24 UI p-p
6500 Hz 3.5 UI p-p
65 kHz 1.0 UI p-p

3

Jitter tolerance of the ADN2812 at these jitter frequencies is better than what the test equipment is able to measure.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,

MAX

Jitter Transfer BW OC-48 490 670 kHz

OC-12 71 108 kHz

OC-3 23 35 kHz

Jitter Peaking OC-48 0 0.03 dB

OC-12 0 0.03 dB

OC-3 0 0.03 dB

Jitter Generation OC-48, 12 kHz to 20 MHz 0.001 0.002 UI rms

0.02 0.037 UI p-p

OC-12, 12 kHz to 5 MHz 0.001 0.002 UI rms

0.01 0.019 UI p-p

OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms

0.01 0.011 UI p-p

Jitter Tolerance OC-48, 223 − 1 PRBS

Rev. 0 | Page 4 of 28

ADN2812

OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

CML OUPUT CHARACTERISTICS

(CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing VSE (see Figure 3) 300 350 600 mV
Differential Output Swing V
Output High Voltage VOH VCC V
Output Low Voltage VOL VCC − 0.6 VCC − 0.35 VCC − 0.3 V

CML Ouputs Timing

Rise Time 20% to 80% 95 112 ps
Fall Time 80% to 20% 95 123 ps
Setup Time TS (see Figure 2), OC-48 150 200 250 ps
Hold Time TH (see Figure 2), OC-48 150 200 250 ps

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA
Output Low Voltage VOL, I

I2C INTERFACE TIMING (See Figure 11)

SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time between a Stop and a Start t

REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 12.3 200 MHz
Required Accuracy 100 ppm

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 µA
Input Low Current IIL, VIN = 0.4 V −5 µA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V

4

Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed (see Table 6).

(see Figure 3) 600 700 1200 mV

DIFF

= 3.0 mA 0.4 V

OL

600 ns

HIGH

1300 ns

LOW

600 ns

HD;STA

600 ns

SU;STA

100 ns

SU;DAT

300 ns

HD;DAT

600 ns

SU;STO

1300 ns

BUF

0 V

IL

VCC V

IH

4

300 ns

Rev. 0 | Page 5 of 28

ADN2812

ABSOLUTE MAXIMUM RATINGS

TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 µF,

MAX

SLICEP = SLICEN = VEE, unless otherwise noted.

Table 4.

Parameter Rating

Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering 10 s) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

32-LFCSP, 4-layer board with exposed paddle soldered to VEE

= 28°C/W.

θ

JA

Rev. 0 | Page 6 of 28

ADN2812

TIMING CHARACTERISTICS

CLKOUTP

T

T

S

H

DATAOUTP/N

04228-0-002

Figure 2. Output Timing

OUTP

OUTN

OUTP–OUTN

V

CML

V

0V

SE

V

DIFF

V

SE

04228-0-004

Figure 3. Single-Ended vs. Differential Output Specifications

Rev. 0 | Page 7 of 28

ADN2812

*

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 TEST2

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

TEST1 1

VCC 2

VREF 3

NIN 4

PIN 5
SLICEP 6
SLICEN 7

VEE 8

THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.

PIN 1
INDICATOR

ADN2812*

TOP VIEW

(Not to Scale)

VCC 12

THRADJ 9

REFCLKP 10

REFCLKN 11

CF2 14

VEE 13

CF1 15

LOL 16

24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE

04228-0-029

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 TEST1 Connect to VCC.
2 VCC P Power for Limamp, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limamp, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss of Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I
21 SDA DI I
22 LOS DO Loss of Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I
24 VCC P Output Buffer, I
25 CLKOUTN DO Differential Recovered Clock Output. CML.
26 CLKOUTP DO Differential Recovered Clock Output. CML.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL.
28 DATAOUTN DO Differential Recovered Data Output. CML.
29 DATAOUTP DO Differential Recovered Data Output. CML.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND

1

Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

2

C Clock Input.

2

C Data Input.

2

C GND.

2

C Power.

Rev. 0 | Page 8 of 28

ADN2812

TYPICAL PERFORMANCE CHARACTERISTICS

16

14

12

10

8

TRIP POINT (mV p-p)

6

4

1000

100

JITTER AMPLITUDE (UI)

ADN2812 TOLERANCE
SONET REQUIREMENT MASK
SONET OBJECTIVE MASK
EQUIPMENT LIMIT

10

1

2

1 10 100

1k 10k 100k

R

(Ω)

TH

Figure 5. LOS Comparator Trip Point Programming

04228-0-003

0.1
1 10 100 1k 10k 100k 1M 10M

JITTER FREQUENCY (Hz)

Figure 6. Typical Measured Jitter Tolerance OC-48

100M

04228-0-030

Rev. 0 | Page 9 of 28