Analog Devices ADN2811 b Datasheet

OC-48/OC-48 FEC Clock and Data Recovery

FEATURES

Meets SONET requirements for jitter transfer/generation/

tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV

1.9 GHz minimum bandwidth

Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for both native SONET and

15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz

REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs

(LVPECL/LVDS only at 155.52 MHz)

19.44 MHz on-chip oscillator to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP

APPLICATIONS

SONET OC-48, SDH STM-16, and 15/14 FEC
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N VCC VEE

IC with Integrated Limiting Amp

ADN2811

PRODUCT DESCRIPTION

The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.

The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and

2.66 Gb/s digital wrapper rates are supported by the ADN2811,
without any change of reference clock.

This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.

The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.

The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead
chip scale package.

CF1 CF2

LOL

ADN2811

2

PIN

QUANTIZER

NIN

VREF

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

THRADJ

LEVEL

DETECT

PHASE

SHIFTER

DAT A

RETIMING

PHASE

DET.

LOOP

FILTER

22

Figure 1.

LOOP

FILTER

FREQUENCY

VCO

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

LOCK

DETECTOR

FRACTIONAL

DIVIDER

RATECLKOUTP/NDATAOUTP/NSDOUT

www.analog.com

/n

XTAL

OSC

2

2

REFSEL[0..1]

REFCLKP/N

XO1

XO2

REFSEL

03019-B-001

ADN2811

TABLE OF CONTENTS

Specifications..................................................................................... 3

Limiting Amplifier ..................................................................... 12

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Functional Descriptions.......................... 6

Definition of Terms.......................................................................... 8

Maximum, Minimum, and Typical Specifications ................... 8

Input Sensitivity and Input Overdrive....................................... 8

Single-Ended vs. Differential ...................................................... 8

LOS Response Time ..................................................................... 9

Jitter Specifications....................................................................... 9

Theory of Operation ...................................................................... 10

Functional Description ..................................................................12

Clock and Data Recovery .......................................................... 12

REVISION HISTORY

5/04—Data Sheet Changed from Rev. A to Rev. B

Slice Adjust.................................................................................. 12

Loss of Signal (LOS) Detector .................................................. 12

Reference Clock.......................................................................... 12

Lock Detector Operation.......................................................... 13

Squelch Mode ............................................................................. 14

Test Modes: Bypass and Loopback........................................... 14

Applications Information .............................................................. 15

PCB Design Guidelines ............................................................. 15

Choosing AC-Coupling Capacitors......................................... 17

DC-Coupled Application .......................................................... 18

LOL Toggling during Loss of Input Data ................................ 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Updated Format.................................................................. Universal

Changes to Table 6 and Table 7......................................................13

Updated Outline Dimensions........................................................19

Changes to Ordering Guide...........................................................19

12/02—Data Sheet Changed from Rev. 0 to Rev. A.

Change to FUNCTIONAL DESCRIPTION Reference Clock ..10

Updated OUTLINE DIMENSIONS .............................................16

Rev. B | Page 2 of 20

ADN2811

SPECIFICATIONS

Table 1. TA = T

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

Input Voltage Range @ PIN or NIN, DC-Coupled 0 1.2 V

Peak-to-Peak Differential Input 2.4 V

Input Common-Mode Level DC-Coupled. (See Figure 24) 0.4 V

Differential Input Sensitivity PIN–NIN, AC-Coupled1, BER = 1 × 10

Input Overdrive Figure 6 2 5 mV p-p

Input Offset 500 µV

Input rms Noise BER = 1 × 10
QUANTIZER—AC CHARACTERISTICS

Upper –3 dB Bandwidth 1.9 GHz

Small Signal Gain Differential 54 dB

S11 @ 2.5 GHz −15 dB

Input Resistance Differential 100 Ω

Input Capacitance 0.65 pF

Pulse Width Distortion
QUANTIZER SLICE ADJUSTMENT

Gain SliceP–SliceN = ±0.5 V 0.115 0.200 0.300 V/V

Control Voltage Range SliceP–SliceN −0.8 +0.8 V

@ SliceP or SliceN 1.3 VCC V

Slice Threshold Offset ±1.0 mV
LEVEL SIGNAL DETECT (SDOUT)

Level Detect Range (See Figure 4) R

R

R

Response Time, DC-Coupled 0.1 0.3 5 µs

Hysteresis (Electrical), PRBS 2

R

R
LOSS OF LOCK DETECT (LOL)

LOL Response Time From f
POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT 150 164 215 mA
PHASE-LOCKED LOOP CHARACTERISTICS PIN–NIN = 10 mV p-p

Jitter Transfer BW OC-48 590 880 kHz

Jitter Peaking OC-48 0.025 dB

Jitter Generation OC-48, 12 kHz–20 MHz 0.003

0.05 0.09 UI p-p

Jitter Tolerance OC-48 (See Figure 11)

600 Hz 923 UI p-p

6 kHz 203 UI p-p

100 kHz 5.5 UI p-p

1 MHz 1.03 UI p-p
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing VSE (See Figure 5) 300 455 600 mV

Differential Output Swing V

Output High Voltage V

Output Low Voltage V

Rise Time 20% to 80% 84 150 ps

Fall time 80% to 20% 84 150 ps

MIN

to T

VCC = V

MAX,

2

MIN

to V

, VEE = 0 V, CF = 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted

MAX

−10

4 10 mV p-p

−10

244 µV rms

10 ps

= 2 kΩ 9.4 13.3 18.0 mV

THRESH

= 20 kΩ 2.5 5.3 7.6 mV

THRESH

= 90 kΩ 0.7 3.0 5.2 mV

THRESH

23

R

= 2 kΩ 5.6 6.6 7.8 dB

THRESH

= 20 kΩ 3.9 6.1 8.5 dB

THRESH

= 90 kΩ 3.2 6.7 9.9 dB

THRESH

error > 1000 ppm 60 µs

VCO

3

(See Figure 5) 600 910 1200 mV

DIFF

OH

OL

VCC V
VCC − 0.6 VCC − 0.3 V

UI rms

Rev. B | Page 3 of 20

ADN2811

Parameter Conditions Min Typ Max Unit

Setup Time TS (See Figure 3) OC-48 140 ps
Hold Time TH (See Figure 3) OC-48 150 ps

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range @ REFCLKP or REFCLKN 0 VCC V
Peak-to-Peak Differential Input 100 mV
Common-Mode Level DC-Coupled, Single-Ended VCC/2 V

TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N) CML Inputs

Peak-to-Peak Differential Input Voltage 0.8 V

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage V
Input Low Voltage V

IH

IL

Input Current VIN = 0.4 V or VIN = 2.4 V −5 +5 µA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = +2.0 mA 0.4 V

1

PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2

PWD measurement made on quantizer outputs in Bypass mode.

3

Measurement is equipment limited.

4

TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

2.0 V

0.8 V

Rev. B | Page 4 of 20

ADN2811

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Ratings

Supply Voltage (VCC) 5.5 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 165°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering 10 Sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

THERMAL CHARACTERISTICS

Thermal Resistance

48-lead LFCSP, 4-layer board with exposed paddle soldered
to VCC

= 25°C/W

θ

JA

Rev. B | Page 5 of 20

ADN2811

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

48 LOOPEN

47VCC

46VEE

45 SDOUT

44 BYPASS

43VEE

42VEE

41 CLKOUTP

40 CLKOUTN

39 SQUELCH

38 DATAOUTP

37 DATAOUTN

THRADJ 1

VCC 2
VEE 3

VREF 4

PIN 5

NIN 6
SLICEP 7
SLICEN 8

VEE 9
LOL 10
XO1 11
XO2 12

PIN 1
INDICATOR

ADN2811

TOPVIEW

VEE 16

REFSEL 15

REFCLKP 14

REFCLKN 13

VEE 19

TDINP 17

TDINN 18

CF1 21

VCC 20

VEE 22

REFSEL1 23

36VCC
35VCC
34VEE
33VEE
32 NC
31 NC
30 RATE
29VEE
28VCC
27VEE
26VCC
25 CF2

REFSEL0 24

03019-B-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1 THRADJ AI LOS Threshold Setting Resistor.
2, 26, 28, Pad VCC P Analog Supply.
3, 9, 16, 19, 22, 27,

VEE P Ground.
29, 33, 34, 42, 43, 46
4 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
5 PIN AI Differential Data Input. CML.
6 NIN AI Differential Data Input. CML.
7 SLICEP AI Differential Slice Level Adjust Input.
8 SLICEN AI Differential Slice Level Adjust Input.
10 LOL DO Loss of Lock Indicator. LVTTL active high.
11 XO1 AO Crystal Oscillator.
12 XO2 AO Crystal Oscillator.
13 REFCLKN DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
14 REFCLKP DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
15 REFSEL DI Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
17 TDINP AI Differential Test Data Input.
18 TDINN AI Differential Test Data Input.
20, 47 VCC P Digital Supply.
21 CF1 AO Frequency Loop Capacitor.
23 REFSEL1 DI Reference Frequency Select (See Table 5) LVTTL.
24 REFSEL0 DI Reference Frequency Select (See Table 5) LVTTL.
25 CF2 AO Frequency Loop Capacitor.
30 RATE DI Data Rate Select (See Table 4) LVTTL.
31, 32 NC DI No Connect.
35, 36 VCC P Output Driver Supply.
37 DATAOUTN DO Differential Retimed Data Output. CML.
38 DATAOUTP DO Differential Retimed Data Output. CML.
39 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
40 CLKOUTN DO Differential Recovered Clock Output. CML.
41 CLKOUTP DO Differential Recovered Clock Output. CML.
44 BYPASS DI Bypass CDR Mode. Active high. LVTTL.
45 SDOUT DO Loss of Signal Detect Output. Active high. LVTTL.
48 LOOPEN DI Enable Test Data Inputs. Active high. LVTTL.

1

Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output

Rev. B | Page 6 of 20