ANALOG DEVICES ADN2811 Service Manual

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OC-48/OC-48 FEC Clock and Data Recovery IC

a

FEATURES
Meets SONET Requirements for Jitter Transfer/

Generation/Tolerance

Quantizer Sensitivity: 4 mV Typ

Adjustable Slice Level: 100 mV

1.9 GHz Minimum Bandwidth
Patented Clock Recovery Architecture
Loss of Signal Detect Range: 3 mV to 15 mV
Single Reference Clock Frequency for Both Native

SONET and 15/14 (7%) Wrapper Rate

Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz

REFCLK LVPECL/LVDS/LVCMOS/LVTTL
Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)

19.44 MHz Oscillator On-Chip to Be Used with

External Crystal
Loss of Lock Indicator
Loopback Mode for High Speed Test Data
Output Squelch and Bypass Features
Single-Supply Operation: 3.3 V
Low Power: 540 mW Typical
7 mm  7 mm 48-Lead LFCSP

APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM Transponders
Regenerators/Repeaters
Test Equipment
Backplane Applications

with Integrated Limiting Amp

ADN2811

PRODUCT DESCRIPTION

The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for –40C to +85C ambient
temperature, unless otherwise noted.

The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s
digital wrapper rate is supported by the ADN2811, without any
change of reference clock.

This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.

The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at
the output.

The ADN2811 is available in a compact 7 mm × 7 mm 48-lead
chip scale package.

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N VCC VEE

ADN2811

2

PIN

NIN

VREF

THRADJ

QUANTIZER

LEVEL

DETECT

PHASE

SHIFTER

DATA

RETIMING

PHASE

DET.

LOOP

FILTER

22

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

CF1 CF2

LOOP

FILTER

VCO

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © 2002 Analog Devices, Inc. All rights reserved.

LOL

FREQUENCY

LOCK

DETECTOR

FRACTIONAL

DIVIDER

RATECLKOUTP/NDATAOUTP/NSDOUT

/n

XTAL

OSC

2

2

REFSEL[0..1]

REFCLKP/N

XO1

XO2

REFSEL

ADN2811–SPECIFICATIONS

(TA = T
unless otherwise noted.)

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 4.7 F, SLICEP = SLICEN = VCC,

MAX

Parameter Conditions Min Typ Max Unit

QUANTIZER–DC CHARACTERISTICS

Input Voltage Range @ PIN or NIN, DC-Coupled 0 1.2 V
Peak-to-Peak Differential Input 2.4 V
Input Common-Mode Level DC-Coupled. (See Figure 22) 0.4 V
Differential Input Sensitivity

PIN–NIN, AC-Coupled1, BER = 1  10

–10

410mV p-p
Input Overdrive Figure 4 2 5 mV p-p
Input Offset 500 µV
Input rms Noise BER = 1  10

–10

244 µV rms

QUANTIZER–AC CHARACTERISTICS

Upper –3 dB Bandwidth 1.9 GHz
Small Signal Gain Differential 54 dB
S11 @ 2.5 GHz –15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF
Pulsewidth Distortion

2

10 ps

QUANTIZER SLICE ADJUSTMENT

Gain SliceP–SliceN = 0.5 V 0.115 0.200 0.300 V/V
Control Voltage Range SliceP–SliceN –0.8 +0.8 V
Control Voltage Range @ SliceP or SliceN 1.3 VCC V
Slice Threshold Offset ± 1.0 mV

LEVEL SIGNAL DETECT (SDOUT)

Level Detect Range (See Figure 2) R

R

R
Response TimeDC-Coupled 0.1 0.3 5 µs
Hysteresis (Electrical), PRBS 2

23

R

R

R

= 2 kΩ 9.4 13.3 18.0 mV

THRESH

= 20 kΩ 2.5 5.3 7.6 mV

THRESH

= 90 kΩ 0.7 3.0 5.2 mV

THRESH

= 2 kΩ 5.6 6.6 7.8 dB

THRESH

= 20 kΩ 3.9 6.1 8.5 dB

THRESH

= 90 kΩ 3.2 6.7 9.9 dB

THRESH

LOSS OF LOCK DETECT (LOL)

LOL Response Time From f

error > 1000 ppm 60 µs

VCO

POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V

POWER SUPPLY CURRENT 150 164 215 mA

PHASE-LOCKED LOOP
CHARACTERISTICS PIN–NIN = 10 mV p-p

Jitter Transfer BW OC-48 590 880 kHz
Jitter Peaking OC-48 0.025 dB
Jitter Generation OC-48, 12 kHz–20 MHz 0.003

3

UI rms

0.05 0.09 UI p-p

Jitter Tolerance OC-48 (See Figure 9)

600 Hz 92

6 kHz 20

100 kHz 5.5 UI p-p

1 MHz 1.0

3

3

3

UI p-p
UI p-p

UI p-p

REV. A–2–

ADN2811

Parameter Conditions Min Typ Max Unit

CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing V
Differential Output Swing V
Output High Voltage V
Output Low Voltage V
Rise Time 20%–80% 84 150 ps
Fall time 80%–20% 84 150 ps
Setup Time T

Hold Time T

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range @ REFCLKP or REFCLKN 0 VCC V
Peak-to-Peak Differential Input 100 mV
Common-Mode Level DC-Coupled, Single-Ended VCC/2 V

TEST DATA DC INPUT
CHARACTERISTICS4 (TDINP/N) CML Inputs

Peak-to-Peak Differential Input Voltage 0.8 V

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage V
Input Low Voltage V
Input Current VIN = 0.4 V or V

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, I
Output Low Voltage VOL, I

NOTES

1

PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2

PWD measurement made on quantizer outputs in BYPASS mode.

3

Measurement is equipment limited.

4

TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

Specifications subject to change without notice.

(See Figure 3) 300 455 600 mV

SE

(See Figure 3) 600 910 1200 mV

DIFF

OH

OL

(See Figure 1)

S

VCC – 0.6 VCC – 0.3 V

VCC V

OC-48 140 ps

(See Figure 1)

H

OC-48 150 ps

IH

IL

= –2.0 mA 2.4 V

OH

= +2.0 mA 0.4 V

OL

= 2.4 V –5 +5

IN

2.0 V

0.8 V

REV. A

–3–

ADN2811

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Minimum Input Voltage (All Inputs) . . . . . . . . . . VEE – 0.4 V

Maximum Input Voltage (All Inputs) . . . . . . . . VCC + 0.4 V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 165C

Storage Temperature . . . . . . . . . . . . . . . . . . –65C to +150C

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LFCSP, four-layer board with exposed paddle
soldered to VCC

θJA = 25C/W

Lead Temperature (Soldering 10 Sec) . . . . . . . . . . . . . . 300C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Option

ADN2811ACP-CML –40ºC to +85ºC 48-Lead LFCSP CP-48
ADN2811ACP-CML-RL –40ºC to +85ºC 48-Lead LFCSP CP-48

Tape-Reel, 2500 pcs

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN2811 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A–4–

PIN CONFIGURATION

48 LOOPEN

47 VCC

46 VEE

45 SDOUT

44 BYPASS

43 VEE

42 VEE

41 CLKOUTP

40 CLKOUTN

39 SQUELCH

38 DATAOUTP

37 DATAOUTN

ADN2811

THRADJ 1

VCC 2
VEE 3

VREF 4

PIN 5

NIN 6
SLICEP 7
SLICEN 8

VEE 9
LOL 10
XO1 11
XO2 12

NC = NO CONNECT

PIN 1
INDICATOR

ADN2811

TOP VIEW

VEE 16

TDINP 17

REFSEL 15

REFCLKP 14

REFCLKN 13

VEE 19

VCC 20

TDINN 18

CF1 21

VEE 22

REFSEL1 23

REFSEL0 24

36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2

PIN FUNCTION DESCRIPTION

Pin No. Mnemonic Type Description

1 THRADJ AI LOS Threshold Setting Resistor
2, 26, 28, Pad VCC P Analog Supply
3, 9, 16, 19, 22, 27, 29, VEE P Ground

33, 34, 42, 43, 46
4 VREF AO Internal V

Voltage. Decouple to GND with 0.1 µF capacitor.

REF

5 PIN AI Differential Data Input. CML.
6NIN AI Differential Data Input. CML.
7 SLICEP AI Differential Slice Level Adjust Input
8 SLICEN AI Differential Slice Level Adjust Input
10 LOL DO Loss of Lock Indicator. LVTTL active high.
11 XO1 AO Crystal Oscillator
12 XO2 AO Crystal Oscillator
13 REFCLKN DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS

(LVPECL, LVDS only at 155.52 MHz).

14 REFCLKP DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS

(LVPECL, LVDS only at 155.52 MHz).

15 REFSEL DI Reference Source Select. “0” = on-chip oscillator with external crystal;

“1” = external clock source, LVTTL.
17 TDINP AI Differential Test Data Input
18 TDINN AI Differential Test Data Input
20, 47 VCC P Digital Supply
21 CF1 AO Frequency Loop Capacitor
23 REFSEL1 DI Reference Frequency Select (See Table II) LVTTL.
24 REFSEL0 DI Reference Frequency Select (See Table II) LVTTL.
25 CF2 AO Frequency Loop Capacitor
30 RATE DI Data Rate Select (See Table I) LVTTL.
31, 32 NC DI No Connect
35, 36 VCC P Output Driver Supply
37 DATAOUTN DO Differential Retimed Data Output. CML.
38 DATAOUTP DO Differential Retimed Data Output. CML.
39 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
40 CLKOUTN DO Differential Recovered Clock Output. CML.
41 CLKOUTP DO Differential Recovered Clock Output. CML.
44 BYPASS DI Bypass CDR Mode. Active high. LVTTL.
45 SDOUT DO Loss of Signal Detect Output. Active high. LVTTL.
48 LOOPEN DI Enable Test Data Inputs. Active high. LVTTL.

Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output

REV. A

–5–