ANALOG DEVICES ADN2806 Service Manual

www.BDTIC.com/ADI

622 Mbps Clock and Data Recovery IC

FEATURES

Exceeds SONET requirements for jitter transfer/

generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 359 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free

APPLICATIONS

BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers

GENERAL DESCRIPTION

The ADN2806 provides the receiver functions for clock and
data recovery, and data retiming for 622 Mbps NRZ data. The
ADN2806 automatically locks to 622 Mbps data without the
need for an external reference clock or programming. In the
absence of input data, the output clock drifts no more than
±5%. All SONET jitter requirements are met, including jitter
transfer, jitter generation, and jitter tolerance. All specifications
are quoted for −40°C to +85°C ambient temperature, unless
otherwise noted.

This device, together with a PIN diode, TIA preamplifier, and a

p can implement a highly integrated, low cost, low power

lim am
fiber optic receiver.

The ADN2806 is available in a compact 5 mm × 5 mm,
32-lead LFCS

FUNCTIONAL BLOCK DIAGRAM

REFCLKP/REF CLKN

(OPTIONAL)

LOL

ADN2806

P.

VCC VEECF1 CF2

PIN

NIN

VREF

BUFFER

PHASE

SHIFTER

DATA

RE-TIMING

2

DATAOUTP/
DATAOUTN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

FREQUENCY

DETECT

PHASE

DETECT

CLKOUTP/
CLKOUTN

Figure 1.

LOOP

FILTER

LOOP

FILTER

2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADN2806

VCO

5831-001

ADN2806

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Jitter Specifications......................................................................... 10

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Jitter Specifications....................................................................... 3

Output and Timing Specifications ............................................. 4

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Timing Characteristics..................................................................... 6

Pin Configuration and Function Descriptions............................. 7

2

I

C Interface Timing and Internal Register Description............. 8

REVISION HISTORY

Theory of Operation ...................................................................... 11

Functional Description.................................................................. 13

Frequency Acquisition............................................................... 13

Input Buffer Amplifier............................................................... 13

Lock Detector Operation .......................................................... 13

SQUELCH Modes...................................................................... 13

2

I

C Interface ................................................................................ 14

Reference Clock (Optional) ...................................................... 15

Applications Information.............................................................. 17

PCB Design Guidelines ............................................................. 17

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

2/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADN2806

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SPECIFICATIONS

TA = T
unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DATA INPUTS—DC CHARACTERISTICS

DATA INPUTS—AC CHARACTERISTICS

LOSS-OF-LOCK (LOL) DETECT

ACQUISITION TIME

DATA RATE READBACK ACCURACY

POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 622.08 Mbps 109 mA
OPERATING TEMPERATURE RANGE –40 +85 °C

to T

MIN

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V
Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V

Data Rate 622 Mbps
S11 @ 622 MHz −15 dB
Output Clock Range Absence of input data 622 ± 5% MHz
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time OC-12 200 μs

Lock to Data Mode OC-12 2.0 ms
Optional Lock to REFCLK Mode 20.0 ms

Fine Readback In addition to REFCLK accuracy
OC-12 100 ppm

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

JITTER SPECIFICATIONS

TA = T
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

30 Hz
300 Hz
25 kHz 2.5 UI p-p
250 kHz

1

Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.

to T

MIN

Jitter Transfer Bandwidth OC-12 75 130 kHz
Jitter Peaking OC-12 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms

0.011 0.026 UI p-p
Jitter Tolerance OC-12, 223 − 1 PRBS

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

1

1

1

Rev. 0 | Page 3 of 20

100 UI p-p
44 UI p-p

1.0 UI p-p

ADN2806

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OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

LVDS OUTPUT CHARACTERISTICS

(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)

Output Voltage High VOH (see Figure 3) 1475 mV
Output Voltage Low VOL (see Figure 3) 925 mV
Differential Output Swing VOD (see Figure 3) 250 320 400 mV

Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω

LVDS Outputs’ Timing

Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), OC-12 760 800 840 ps
Hold Time TH (see Figure 2), OC-12 760 800 840 ps

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input High Voltage VIH 0.7 VCC V

Input Low Voltage VIL 0.3 VCC V

Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA

Output Low Voltage VOL, IOL = 3.0 mA 0.4 V
I2C INTERFACE TIMING See Figure 10

SCK Clock Frequency 400 kHz

SCK Pulse Width High t

SCK Pulse Width Low t

Start Condition Hold Time t

Start Condition Setup Time t

Data Setup Time t

Data Hold Time t

SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb

Stop Condition Setup Time t

Bus Free Time Between a Stop and a Start t
REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN

V

V

Minimum Differential Input Drive 100 mV p-p

Reference Frequency 10 160 MHz

Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS

Input High Voltage VIH 2.0 V

Input Low Voltage VIL 0.8 V

Input High Current IIH, VIN = 2.4 V 5 μA

Input Low Current IIL, VIN = 0.4 V −5 μA
LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V

Output Low Voltage VOL, IOL = +2.0 mA 0.4 V

1

Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.

600 ns

HIGH

1300 ns

LOW

600 ns

HD;STA

600 ns

SU;STA

100 ns

SU;DAT

300 ns

HD;DAT

600 ns

SU;STO

1300 ns

BUF

0 V

IL

VCC V

IH

1

300 ns

Rev. 0 | Page 4 of 20

ADN2806

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ABSOLUTE MAXIMUM RATINGS

TA = T

0.47 μF, unless otherwise noted.

Table 4.

Parameter Rating

Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF =

MAX

Stress above those listed under Absolute Maximum Ratings may
ca

use permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θ

= 28°C/W.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 20

ADN2806

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TIMING CHARACTERISTICS

CLKOUTP

DATAOUTP/

DATAOUTN

V

OH

T

T

S

H

Figure 2. Output Timing

DIFFERENT IAL CLKOUTP/N, DATAO UTP/N

05831-002

V

OS

V

OL

|VOD|

5831-032

Figure 3. Differential Output Specifications

5mA

R

LOAD

V

100Ω

5mA

SIMPLIFIED LVDS

OUTPUT STAGE

100Ω

DIFF

05831-033

Figure 4. Differential Output Stage

Rev. 0 | Page 6 of 20

ADN2806

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 TEST2

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

TEST1 1

VCC 2

VREF 3

NIN 4
PIN 5

NC 6
NC 7

VEE 8

* THERE IS AN EXPOSED PAD ON THE BOTTOM OF

THE PACKAGE THAT MUST BE CONNECT ED TO GND.

PIN 1
INDICATO R

ADN2806*

TOP VIEW

(Not to Scale)

NC 9

NC=NO CONNECT

REFCLKP 10

REFCLKN 11

VEE 13

VCC 12

CF2 14

CF1 15

LOL 16

24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE

05831-004

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type

1 TEST1 Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 NC No Connect
7 NC No Connect
8 VEE P GND for Limiting Amplifier, LOS.
9 NC No Connect
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 NC No Connect
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND.

1

Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

1

Description

Rev. 0 | Page 7 of 20

ADN2806

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I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

SLAVE ADDRESS [6...0]

1A500000X

MSB = 1 SET BY

PIN 19

Figure 6. Slave Address Configuration

R/W
CTRL.

0 = WR
1 = RD

5831-007

S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA

Figure 7. I

2

C Write Data Transfer

5831-00

S

S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)

A(M) = LACK OF ACKNOWLEDG E BY MASTER

2

Figure 8. I

C Read Data Transfer

5831-009

SDA

SCK

START BIT

S

SLAVE ADDRESS SUB ADDRES S DATA

SLADDR[4... 0]

Figure 9. I

SUB ADDR[6...1] DATA[6...1]

2

C Data Transfer Timing

D0D7A0A7A5A6

STOP BIT

ACKACKWR ACK

P

5831-010

t

F

SDA

t

SCK

SS

LOW

t

HD;STA

t

R

t

HD;DAT

t

SU;DAT

Figure 10. I

t

F

t

HIGH

t

SU;STA

2

C Port Timing Diagram

t

t

SU;STO

HD;STA

t

BUF

t

R

PS

5831-011

Rev. 0 | Page 8 of 20

ADN2806

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Table 6. Internal Register Map

1

Reg
Name R/W Addr D7 D6 D5 D4 D3 D2 D1 D0

FREQ0 R 0x0 MSB LSB
FREQ1 R 0x1 MSB LSB
FREQ2 R 0x2 0 MSB LSB
MISC R 0x4 x x x

Static

L

LO

LOL
status

Data rate
measurement

x x

complete
CTRLA W 0x8 F
CTRLB W 0x9

range Data rate/DIV_F

REF

Config

L

LO

Reset
MISC[4]

System
reset

ratio Measure data rate Lock to reference

REF

0

Reset

0 0 0

MISC[2]

CTRLC W 0x11 0 0 0 0 0 x SQUELCH mode Output boost

1

All writeable registers default to 0x00.

Table 7. Miscellaneous Register, MISC

Static LOL LOL Status Data Rate Measurement Complete
D7 D6 D5 D4 D3 D2 D1 D0

x x x 0 = Waiting for next LOL 0 = Locked 0 = Measuring data rate x x
1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete

Table 8. Control Register, CTRLA

F

Range Data Rate/Div_F

REF

1

Ratio Measure Data Rate Lock to Reference

REF

D7 D6 D5 D4 D3 D2 D1 D0

0 0 19.44 MHz 0 1 0 1 32 Set to 1 to measure data rate 0 = Lock to input data
0 1 38.88 MHz 0 1 0 1 32 1 = Lock to reference clock
1 0 77.76 MHz 0 1 0 1 32
1 1 155.52 MHz 0 1 0 1 32

1

Where DIV_F

is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).

REF

Table 9. Control Register, CTRLB

Config LOL Reset MISC[4] System Reset Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0

0 = LOL pin normal operation
1 = LOL pin is static LOL

Write a 1 followed
by 0 to reset MISC[4]

Write a 1 followed by
0 to reset ADN2806

Set to 0

Write a 1 followed
by

0 to reset MISC[2]

Set to 0 Set to 0 Set to 0

Table 10. Control Register, CTRLC

SQUELCH Mode Output Boost

D7 D6 D5 D4 D3 D2 D1 D0

Set to 0

0 = Squelch data outputs and

0 = Default output swing Set to 0 Set to 0 Set to 0 Set to 0 Set to 0

clock outputs
1 = Squelch data outputs or

1 = Boost output swing

clock outputs

Rev. 0 | Page 9 of 20

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JITTER SPECIFICATIONS

The ADN2806 CDR is designed to achieve the best bit­error-rate (BER) performance and to exceed the jitter
transfer, generation, and tolerance specifications proposed
for SONET/SDH equipment defined in the Telcordia
Technologies specification.

Jitter is the dynamic displacement of digital signal edges from

heir long-term average positions, measured in unit intervals

t
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.

The following sections briefly summarize the specifications of
j

itter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2806 performance with respect to those specifications.

Jitter Generation

The jitter generation specification limits the amount of jitter

hat can be generated by the device with no jitter and wander

t
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms and less than 0.1 UI p-p.

Jitter Transfer

The jitter transfer function is the ratio of the jitter on the output

nal to the jitter applied on the input signal vs. the frequency.

sig
This parameter measures the amount of jitter on an input signal
that can be transferred to the output signal (see

nt is limited.

amou

Figure 11). This

0.1

SLOPE = –20dB/ DECADE

JITTER G AIN (dB)

ACCEPTABLE

RANGE

JITTER FREQUENCY (kHz)

Figure 11. Jitter Transfer Curve

f

C

Jitter Tolerance

The jitter tolerance is defined as the peak-to-peak amplitude of
t

he sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see

15.00

1.50

AMPLITUDE (UI p-p)

0.15

INPUT JITTE

Figure 12).

SLOPE = –20dB/DECADE

f

0

Figure 12. SONET Jitter Tolerance Mask

f

1

JITTER FREQUENCY (kHz)

f2f

3

f

4

5831-015

5831-016

Rev. 0 | Page 10 of 20

ADN2806

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THEORY OF OPERATION

The ADN2806 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, composed of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop that compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.

The delay and phase loops together track the phase of the input
da

ta signal. For example, when the clock lags the input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
the data. The faster clock picks up phase, whereas the delayed
data loses phase. Because the loop filter is an integrator, the
static phase error is driven to 0°.

X(s)

INPUT

DATA

RECOVERED

CLOCK

d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHI FTER GAI N
n = DIVIDE

ATI O

psh

e(s)

d/sc

Z(s)

JITTER TRANSFER FUNCTION

Z(s)

=

X(s)

2

s

TRACKING ERROR T RANSFER FUNCTION

e(s)

=

X(s)

2

s

Figure 13. PLL/DLL Architecture

o/s

1/n

1

n psh

cn

s+ 1

+

o

do

2

s

d psh

s++

c

JITTER PEAKIN
IN ORDINARY PLL

do
cn

5831-017

Another view of the circuit is that the phase shifter implements
t

he zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path;
therefore, it does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase­locked loop is caused by the presence of this zero in the closed­loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.

The delay and phase loops together simultaneously provide
wi

deband jitter accommodation and narrow-band jitter

filtering. The linearized block diagram in Figure 13 shows that

he jitter transfer function, Z(s)/X(s), provides excellent second-

t
order low-pass filtering. Note that the jitter transfer has no zero,
unlike an ordinary second-order phase-locked loop. This means
that the main PLL loop has virtually no jitter peaking (see
Figure 14), making this circuit ideal for signal regenerator

pplications, where jitter peaking in a cascade of regenerators

a
can contribute to hazardous jitter accumulation.

The error transfer, e(s)/X(s), has the same high-pass form as an
ord

inary phase-locked loop. This transfer function can be
optimized to accommodate a significant amount of wideband
jitter, because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.

ADN2806

JITTER GAIN (dB)

o

n psh

Figure 14. Jitter Response vs. Conventional PLL

d psh

c

FREQUENCY (kHz)

Z(s)
X(s)

5831-018

The delay and phase loops contribute to overall jitter accom­modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated, and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.

Rev. 0 | Page 11 of 20

ADN2806

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At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range. The size of
the VCO tuning range, therefore, has only a small effect on the
jitter accommodation. The delay-locked loop control voltage is
now larger; therefore, the phase shifter takes on the burden of
tracking the input jitter. The phase shifter range, in UI, can be
seen as a broad plateau on the jitter tolerance curve. The phase
shifter has a minimum range of 2 UI at all data rates.

The gain of the loop integrator is small for high jitter
f

requencies; therefore, larger phase differences are needed to
increase the loop control voltage enough to tune the range of
the phase shifter. However, large phase errors at high jitter
frequencies cannot be tolerated. In this region, the gain of the
integrator determines the jitter accommodation. Because the
gain of the loop integrator declines linearly with frequency,
jitter accommodation is lower with higher jitter frequency. At
the highest frequencies, the loop gain is very small, and little
tuning of the phase shifter can be expected. In this case, jitter
accommodation is determined by the eye opening of the input
data, the static phase error, and the residual loop jitter
generation. The jitter accommodation is roughly 0.5 UI in this
region. The corner frequency between the declining slope and
the flat region is the closed-loop bandwidth of the delay-locked
loop, which is roughly 1.0 MHz at 622 Mbps.

Rev. 0 | Page 12 of 20

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FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2806 acquires frequency from the data. The lock
detector circuit compares the frequency of the VCO and the
frequency of the incoming data. When these frequencies differ
by more than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. When the VCO frequency is within 250 ppm
of the data frequency, LOL is deasserted.

Once LOL is deasserted, the frequency-locked loop is turned
o

ff. The PLL/DLL pulls the VCO frequency in the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between
CF1 a

nd CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.

INPUT BUFFER AMPLIFIER

The input buffer has differential inputs (PIN/NIN), which are
internally terminated with 50 Ω to an on-chip voltage reference
(VREF = 2.5 V typically). The minimum differential input level
required to achieve a BER of 10

−10

is 200 mV p-p.

LOCK DETECTOR OPERATION

The lock detector on the ADN2806 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2806 is a CDR that locks onto a
622 Mbps data rate without the use of a reference clock as an
acquisition aid. In this mode, the lock detector monitors the
frequency difference between the VCO and the input data
frequency and deasserts the loss of lock signal, which appears
on Pin 16, LOL, when the VCO is within 250 ppm of the data
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount and acquires phase lock.
Once locked, if the input frequency error exceeds 1000 ppm
(0.1%), the loss-of-lock signal is reasserted and control returns
to the frequency loop, which begins a new frequency
acquisition. The LOL pin remains asserted until the VCO locks
onto a valid input data stream to within 250 ppm frequency
error. This hysteresis is shown in

–1000

Figure 15. Transfer Function of LOL

Figure 15.

LOL

1

0–250 250 1000 f

VCO

(ppm)

ERROR

5831-020

LOL Detector Operation Using a Reference Clock

In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2806 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7, 6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
det

ector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16, LOL, is deasserted
when the VCO is within 250 ppm of the desired frequency. This
enables the D/PLL, which pulls the VCO frequency in the
remaining amount with respect to the input data and acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss-of-lock signal is reasserted and
control returns to the frequency loop, which reacquires with
respect to the reference clock. The LOL pin remains asserted
until the VCO frequency is within 250 ppm of the desired
frequency. This hysteresis is shown in

Figure 15.

Static LOL Mode

The ADN2806 implements a static LOL feature that indicates if
a loss-of-lock condition has ever occurred. This feature remains
asserted, even if the ADN2806 regains lock, until the static LOL
bit is manually reset. The I

2

C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock condition,
this bit is internally asserted to logic high. The MISC[4] bit remains
high even after the ADN2806 has reacquired lock to a new data
rate. This bit can be reset by writing a 1 followed by 0 to I

2

C
Register Bit CTRLB[6]. Once reset, the MISC[4] bit remains
deasserted until another loss-of-lock condition occurs.

2

Writ i ng a 1 to I

C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The CTRLB[7]
bit defaults to 0. In this mode, the LOL pin operates in the
normal operating mode, that is, it is asserted only when the
ADN2806 is in acquisition mode and deasserts when the
ADN2806 has reacquired lock.

SQUELCH MODES

Two modes for the SQUELCH pin are available with the
ADN2806: squelch data outputs and clock outputs mode and
squelch data outputs or clock outputs mode. Squelch data outputs
and clock outputs mode is selected when CTRLC[1] is 0 (default
mode). In this mode, when the SQUELCH input, Pin 27, is driven
to a TTL high state, both the data outputs (DATAOUTN and
DATAOUTP) and the clock outputs (CLKOUTN and CLKOUTP)
are set to the zero state to suppress downstream processing. If
the squelch function is not required, Pin 27 should be tied to VEE.

Rev. 0 | Page 13 of 20

ADN2806

www.BDTIC.com/ADI

Squelch data outputs or clock outputs mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN and DATAOUTP pins
are squelched. When the SQUELCH input is driven to a low
state, the CLKOUTN and CLKOUTP pins are squelched. This is
especially useful in repeater applications, where the recovered
clock may not be needed.

I2C INTERFACE

The ADN2806 supports a 2-wire, I2C-compatible serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information to and from any device
connected to the bus. Each slave device is recognized by a
unique address. The ADN2806 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are
defaulted to all 0s. The slave address consists of the seven MSBs
of an 8-bit word. The LSB of the word either sets a read or write
operation (see

hile Logic 0 corresponds to a write operation.

w

To control the device on the bus, the following protocol must be

lowed. First, the master initiates a data transfer by establish-

fol
ing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines, waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.

Figure 6). Logic 1 corresponds to a read operation,

The ADN2806 acts as a standard slave device on the bus. The data
o

n the SDA pin is eight bits long, supporting the 7-bit addresses
plus the R/W bit. The ADN2806 has eight subaddresses to enable
the user-accessible internal registers (see Tab l e 6 through Tab l e

10). It, therefore, interprets the first byte as the device address
a

nd the second byte as the starting subaddress. Auto-increment
mode is supported, allowing data to be read from or written to
the starting subaddress and each subsequent address without
manually addressing the subsequent subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without updating all registers.

Stop and start conditions can be detected at any stage of the
da

ta transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2806 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while reading back in auto­increment mode, then the highest subaddress register contents
continue to be output until the master device issues a no acknow­ledge. This indicates the end of a read. In a no-acknowledge
condition, the SDATA line is not pulled low on the ninth pulse.
See

Figure 7 and Figure 8 for sample write and read data transfers

a

nd Figure 9 for a more detailed timing diagram.

Additional Features Available via the I2C Interface

System Reset

A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2806 in its
previously programmed operating mode, as set in Registers
CTRL[A], CTRL[B], and CTRL[C].

2

C Register Bit CTRLB[5]. This initiates a new

Rev. 0 | Page 14 of 20

ADN2806

V

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REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data
recovery with the ADN2806; however, support for an optional
reference clock is provided. The reference clock can be driven
differentially or in a single-ended fashion. If the reference
clock is not being used, REFCLKP should be tied to VCC, and
REFCLKN can be left floating or tied to VEE (the inputs are
internally terminated to VCC/2). See
18 for sample configurations.

The REFCLK input buffer accepts any differential signal with a

eak-to-peak differential amplitude of greater than 100 mV (for

p
example, LVPECL or LVDS) or a standard single-ended, low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not
critical, and 100 ppm accuracy is sufficient.

ADN2806

REFCLKP

10

11

REFCLKN

Figure 16. Differential REFCLK Configuration

CC

REFCLKP
CLK
OSC

OUT

REFCLKN

Figure 17. Single-Ended REFCLK

VCC

REFCLKP

NC

REFCLKN

Figure 18. No REFCLK Configur

ADN2806

ADN2806

10

11

100kΩ

Figure 16 through Figure

BUFFER

100kΩ

100kΩ

BUFFER

100kΩ

100kΩ

Configuration

BUFFER

100kΩ

ation

VCC/2

VCC/2

VCC/2

5831-021

5831-022

5831-023

There are two mutually exclusive uses, or modes, of the
reference clock. The reference clock can be used either to help
the ADN2806 lock onto data or to measure the frequency of the
incoming data to within 0.01%. The modes are mutually
exclusive because in the first use the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate, and in the second use the user does not know what
the data rate is and wants to measure it.

Lock-to-reference mode is enabled by writing a 1 to I

2

C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I

2

C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2806 locks onto a frequency derived
from the reference clock according to

Data Rate/2

CTRLA[5:2]

= REFCLK/2

CTRLA[7, 6]

The user must provide a reference clock that is a function of the

ta rate. By default, the ADN2806 expects a reference clock of

da

19.44 MHz. Other options are 38.88 MHz, 77.76 MHz, and

155.52 MHz, which are selected by programming CTRLA[7, 6].
CTRLA[5:2] should be programmed to [0101] for all cases.

Table 11. CTRLA Settings

CTRLA[7, 6] Range (MHz) CTRLA[5:2] Ratio

00 19.44 0101 25
01 38.88 0101 25
10 77.76 0101 25
11 155.52 0101 25

For example, if the reference clock frequency is 38.88 MHz and the
input data rate is 622.08 Mbps, CTRLA[7, 6] is set to [01] to
produce a divided-down reference clock of 19.44 MHz, and
CTRLA[5:2] is set to [0101], that is, 5, because

622.08 Mbps/19.44 MHz = 2

5

In this mode, if the ADN2806 loses lock for any reason, it relocks
o

nto the reference clock and continues to output a stable clock.

While the ADN2806 is operating in lock-to-reference mode,
a

0 to 1 transition should be written into the CTRLA[0] bit to

initiate a lock-to-reference clock command.

Rev. 0 | Page 15 of 20

ADN2806

(

www.BDTIC.com/ADI

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2806 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to within 0.01% (100 ppm) accuracy.
The accuracy error of the reference clock is added to the accuracy
of the ADN2806 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the measure­ment is within 200 ppm.

The reference clock can range from 10 MHz to 160 MHz.

y default, the ADN2806 expects a reference clock between

B
10 MHz and 20 MHz. If the reference clock is between 20 MHz
and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz,
the user must configure the ADN2806 for the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7, 6]. Using the reference clock to determine the frequency
of the incoming data does not affect the manner in which the
part locks onto data. In this mode, the reference clock is used
only to determine the frequency of the data.

Prior to reading back the data rate using the reference clock, the
CTRL

A[7, 6] bits must be set to the appropriate frequency
range with respect to the reference clock being used. A fine data
rate readback is then executed as follows:

3. Read back MIS

complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.

4. Read back t

FREQ0[7:0].

The data rate can be determined by

DATARATE

where:
FREQ[22:0] is th
FREQ1[7:0], and FREQ0[7:0] (LSB byte).

f

is the data rate (Mbps).

DATARATE

is the REFCLK frequency (MHz).

f

REFCLK

SEL_RATE is the setting from CTRLA[7, 6].

For example, if the reference clock frequency is 32 MHz,

EL_RATE = 1, because the reference frequency falls into the

S
20 MHz to 40 MHz range, setting CTRLA[7, 6] to [01],.
Assume for this example that the input data rate is 622.08 Mb/s
(OC12). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 10
Plugging this value into the equation yields

637e3 × 32e6/2

C[2]. If it is 0, the measurement is not

he data rate from FREQ2[6:0], FREQ1[7:0], and

)_14(

RATESEL

+

[]

×=

e reading from FREQ2[6:0] (MSB byte,

(14 + 1)

= 622.08 Mbps

fFREQf

REFCLK

)

2/0.22

3

.

1. W

rite a 1 to CTRLA[1]. This enables the fine data rate

measurement capability of the ADN2806. This bit is level
sensitive and can perform subsequent frequency measurements
without being reset.

2. Res

et MISC[2] by writing a 1 followed by a 0 to CTRLB[3].

This initiates a new data rate measurement.

Table 12.

D22 D21 ... D17 D16 D15 D14 ... D9 D8 D7 D6 ... D1 D0

FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]

If subsequent frequency measurements are required, CTRLA[1]

hould remain set to 1. It does not need to be reset. The

s
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.

Note that a data rate readback is valid only if LOL is low. If LOL

h, the data rate readback is invalid.

is hig

Rev. 0 | Page 16 of 20

ADN2806

(

=

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal
performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.

Use of a 22 μF electrolytic capacitor between VCC and VEE is

ecommended at the location where the 3.3 V supply enters the

r
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between ADN2806 supply pins VCC and VEE,
as close as possible to the ADN2806 VCC pins.

If connections to the supply and ground are made through

ias, the use of multiple vias in parallel helps to reduce series

v
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buf fers. Refer to
r

ecommended connections.

Figure 19 for the

By placing the power supply and GND planes adjacent to each

ther and using close spacing between the planes, excellent high

o
frequency decoupling can be realized. The capacitance is given
by

)

pF/0.88εrdAC

PLANE

where:

ε

is the dielectric constant of the PCB material.

r

A is the area of the overlap of power and GND planes (cm

2

).
d is the separation between planes (mm).
For FR-4, ε

C

PLANE

= 4.4 and d = 0.25 mm; therefore,

r

~ 15 pF/cm2.

VCC

0.1µF

+

LIM

1nF

0.1µF

50Ω

50Ω

0.1µF22µF 1nF

TEST2

TEST1

1

VCC

2

VREF

3

NIN

4

PIN

5

NC

6

NC

7

VEE

1.6µF

1.6µF

8

NC

VCC

0.1µF

Figure 19. Typical ADN2806 Applications Circuit

50Ω TRANSMISSIO N LINES

TP

AOUTN

SQUELCH

DAT

CLKOU

DATAOUTP

VEE

VCC

27

28

29

30

31

32

EXPOSED PAD

TIED OFF TO

VEE PLANE

WITH VIAS

9

11

14

13

12

10

CF1

CF2

VEE

VCC

REFCLKP

REFCLKN

NC

0.47µF ±20%
>300MΩ INSULAT ION RESISTANCE

1nF

DATAOUTP

DATAOUTN

CLKOUTP

CLKOUTN

CLKOUTN

25

26

VCC

24

VEE

23

NC

22

SDA

21

SCK

20

SADDR5

19

VCC

18

VEE

17

15

LOL

1nF

16

µC

VCC

0.1µF1nF

2

I

C CONTROLL ER

2

C CONTROLL ER

I

VCC

0.1µF

µC

5831-031

Rev. 0 | Page 17 of 20

ADN2806

www.BDTIC.com/ADI

Transmission Lines

Minimizing reflections in the ADN2806 requires use of 50 Ω
transmission lines for all pins with high frequency input and
output signals, including PIN, NIN, CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN,
if a high frequency reference clock is used, such as 155 MHz). It
is also necessary for the PIN/NIN input traces to be matched in
length and for the CLKOUTP/CLKOUTN and
DATAOUTP/DATAOUTN output traces to be matched in
length to avoid skew between the differential traces.

The high speed inputs, PIN and NIN, are internally terminated

ith 50 Ω to an internal reference voltage (see Figure 20).

w
A 0.1 μF
provide an ac ground for the inputs.

is recommended between VREF, Pin 3, and GND to

Choosing AC Coupling Capacitors

AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2806 can be optimized
for the application. When choosing the capacitors, the time
constant formed with the two 50 Ω resistors in the signal path
must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see
dep

endent jitter (PDJ).

Figure 21), causing pattern-

The user must determine how much droop is tolerable and

hoose an ac coupling capacitor based on that amount of droop.

c
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection can
require some trade-offs between droop and PDJ.

As with any high speed, mixed-signal design, take care to keep
all h

igh speed digital traces away from sensitive analog nodes.

ADN2806

C

LIM

Figure 20. ADN2806 AC-Coupled Input Configuration

50Ω

50Ω

0.1µF

IN

PIN

C

IN

NIN

50Ω50Ω

VREF

3kΩ

2.5V

5831-026

Soldering Guidelines for Lead Frame Chip Scale Package

The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.

For example, assuming that 2% droop can be tolerated, the

um differential droop is 4%. Normalizing to V p-p:

maxim

−t/τ

Droop = ΔV = 0

.04 V = 0.5 V p-p (1 − e

); therefore, τ = 12t

where:

he RC time constant (C is the ac coupling capacitor, R =

τ is t
100 Ω seen by C).
t is the total discharge time, which is equal to nT, where n is the
number of CIDs, and T is the bit period.

The capacitor value can then be calculated by combining the

quations for τ and t:

e

C = 12

nT/R

Once the capacitor value is selected, the PDJ can be
a

pproximated as

PDJ

pspp

= 0.5 tr(1 − e

(−nT/RC)

)/0.6

where:

PDJ

is the amount of pattern-dependent jitter allowed

pspp

(<0.01 UI p-p typical).

t

is the rise time, which is equal to 0.22/BW,

r

where BW ~ 0.7 (bit rate).

Rev. 0 | Page 18 of 20

Note that this expression for t

is accurate only for the inputs.

r

The output rise time for the ADN2806 is ~100 ps regardless of
the data rate.

ADN2806

V

www.BDTIC.com/ADI

LIM

V1

V1b

C

IN

V2

C

IN

V2b

PIN

50Ω

50Ω

NIN

ADN2806

+

BUFFER

V

REF

–

CDR

C

OUT

C

OUT

DATAOUTP

DATAOUTN

1

V1

V1b

V2

V2b

DIFF

V

= V2–V2b

DIFF

VTH = ADN2806 THRESHOLD

NOTES:

1. DURING DATA PATTERNS WITH HIG H TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS Z ERO.

2. WHEN THE OUT PUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DI FFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL , WHICH EFFECTIVELY INTRODUCES A DIFFERENT IAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.

3. WHEN THE BURST OF DATA STARTS AGAI N, THE DIF FERENTI AL DC OFFSET ACROSS THE AC COUPLI NG CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIG H OR LOW DE PENDING ON T HE LEVELS OF V1 AND V1b WHEN T HE TIA WENT TO CID, IS CANCELED OUT. THE QUANTI ZER
DOES NOT RECO GNIZE THIS AS A VALID STATE.

4. THE DC OFF SET SLOWLY DI SCHARGES UNTI L THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS T HE SENSIT IVITY OF T HE ADN2806.

THE QUANTIZER CAN RECOGNIZE BOTH HI GH AND LOW STATES AT THIS POINT.

234

VREF

VTH

5831-027

Figure 21. Example of Baseline Wander

Rev. 0 | Page 19 of 20

ADN2806

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1
INDICATOR

3.45

3.30 SQ

3.15

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 22. 32-Lead Frame Chip Scale Package [LFCSP_VQ]

mm × 5 mm Body, Very Thin Quad

5

(CP-32-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADN2806ACPZ
ADN2806ACPZ-500RL7
ADN2806ACPZ-RL7
EVAL-ADN2806EB Evaluation Board

1

Z = Pb-free part.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05831–0–2/06(0)

1

1

1

−40°C to +85°C 32-Lead LFCSP_VQ CP-32-3

−40°C to +85°C 32-Lead LFCSP_VQ, Tape-Reel, 500 pieces CP-32-3

−40°C to +85°C 32-Lead LFCSP_VQ, Tape-Reel, 1500 pieces CP-32-3

Rev. 0 | Page 20 of 20