ANALOG DEVICES ADN2806 Service Manual
www.BDTIC.com/ADI
622 Mbps Clock and Data Recovery IC
FEATURES
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 359 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
GENERAL DESCRIPTION
The ADN2806 provides the receiver functions for clock and
data recovery, and data retiming for 622 Mbps NRZ data. The
ADN2806 automatically locks to 622 Mbps data without the
need for an external reference clock or programming. In the
absence of input data, the output clock drifts no more than
±5%. All SONET jitter requirements are met, including jitter
transfer, jitter generation, and jitter tolerance. All specifications
are quoted for −40°C to +85°C ambient temperature, unless
otherwise noted.
This device, together with a PIN diode, TIA preamplifier, and a
p can implement a highly integrated, low cost, low power
lim am
fiber optic receiver.
The ADN2806 is available in a compact 5 mm × 5 mm,
32-lead LFCS
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REF CLKN
(OPTIONAL)
LOL
ADN2806
P.
VCC VEECF1 CF2
PIN
NIN
VREF
BUFFER
PHASE
SHIFTER
DATA
RE-TIMING
2
DATAOUTP/
DATAOUTN
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
FREQUENCY
DETECT
PHASE
DETECT
CLKOUTP/
CLKOUTN
Figure 1.
LOOP
FILTER
LOOP
FILTER
2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
ADN2806
VCO
5831-001
ADN2806
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Jitter Specifications......................................................................... 10
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 3
Output and Timing Specifications ............................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Timing Characteristics..................................................................... 6
Pin Configuration and Function Descriptions............................. 7
2
I
C Interface Timing and Internal Register Description............. 8
REVISION HISTORY
Theory of Operation ...................................................................... 11
Functional Description.................................................................. 13
Frequency Acquisition............................................................... 13
Input Buffer Amplifier............................................................... 13
Lock Detector Operation .......................................................... 13
SQUELCH Modes...................................................................... 13
2
I
C Interface ................................................................................ 14
Reference Clock (Optional) ...................................................... 15
Applications Information.............................................................. 17
PCB Design Guidelines ............................................................. 17
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
2/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADN2806
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SPECIFICATIONS
TA = T
unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DATA INPUTS—DC CHARACTERISTICS
DATA INPUTS—AC CHARACTERISTICS
LOSS-OF-LOCK (LOL) DETECT
ACQUISITION TIME
DATA RATE READBACK ACCURACY
POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 622.08 Mbps 109 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
to T
MIN
Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V
Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V
Data Rate 622 Mbps
S11 @ 622 MHz −15 dB
Output Clock Range Absence of input data 622 ± 5% MHz
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF
VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time OC-12 200 μs
Lock to Data Mode OC-12 2.0 ms
Optional Lock to REFCLK Mode 20.0 ms
Fine Readback In addition to REFCLK accuracy
OC-12 100 ppm
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
JITTER SPECIFICATIONS
TA = T
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
30 Hz
300 Hz
25 kHz 2.5 UI p-p
250 kHz
1
Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.
to T
MIN
Jitter Transfer Bandwidth OC-12 75 130 kHz
Jitter Peaking OC-12 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms
0.011 0.026 UI p-p
Jitter Tolerance OC-12, 223 − 1 PRBS
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
1
1
1
Rev. 0 | Page 3 of 20
100 UI p-p
44 UI p-p
1.0 UI p-p
ADN2806
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OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High VOH (see Figure 3) 1475 mV
Output Voltage Low VOL (see Figure 3) 925 mV
Differential Output Swing VOD (see Figure 3) 250 320 400 mV
Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω
LVDS Outputs’ Timing
Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), OC-12 760 800 840 ps
Hold Time TH (see Figure 2), OC-12 760 800 840 ps
I2C INTERFACE DC CHARACTERISTICS LVCMOS
Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, IOL = 3.0 mA 0.4 V
I2C INTERFACE TIMING See Figure 10
SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = +2.0 mA 0.4 V
1
Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.
600 ns
HIGH
1300 ns
LOW
600 ns
HD;STA
600 ns
SU;STA
100 ns
SU;DAT
300 ns
HD;DAT
600 ns
SU;STO
1300 ns
BUF
0 V
IL
VCC V
IH
1
300 ns
Rev. 0 | Page 4 of 20
ADN2806
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ABSOLUTE MAXIMUM RATINGS
TA = T
0.47 μF, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
MIN
to T
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF =
MAX
Stress above those listed under Absolute Maximum Ratings may
ca
use permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θ
= 28°C/W.
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADN2806
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TIMING CHARACTERISTICS
CLKOUTP
DATAOUTP/
DATAOUTN
V
OH
T
T
S
H
Figure 2. Output Timing
DIFFERENT IAL CLKOUTP/N, DATAO UTP/N
05831-002
V
OS
V
OL
|VOD|
5831-032
Figure 3. Differential Output Specifications
5mA
R
LOAD
V
100Ω
5mA
SIMPLIFIED LVDS
OUTPUT STAGE
100Ω
DIFF
05831-033
Figure 4. Differential Output Stage
Rev. 0 | Page 6 of 20
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