ANALOG DEVICES ADN2805 Service Manual
www.BDTIC.com/ADI
1.25 Gbps Clock and Data Recovery IC
FEATURES
Locks to 1.25 Gbps NRZ serial data input
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
2
I
C interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
GbE line card
GENERAL DESCRIPTION
The ADN2805 provides the receiver functions of quantization
and clock and data recovery for 1.25 Gbps. The ADN2805
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance.
All specifications are specified for −40°C to +85°C ambient
temperature, unless otherwise noted. The ADN2805 is available
in a compact 5 mm × 5 mm 32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REF CLKN
(OPTIO NAL)
LOL
FREQUENCY
DETECT
LOOP
FILTER
ADN2805
VCC VEECF1 CF2
PIN
NIN
VREF
BUFFER
PHASE
SHIFTER
DATA
RE-TIMING
2
DATAOUTP/
DATAOUTN
PHASE
DETECT
CLKOUTP/
CLKOUT N
Figure 1.
LOOP
FILTER
2
VCO
ADN2805
07121-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADN2805
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Jitter Specifications ....................................................................... 3
Output and Timing Specifications ............................................. 4
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
I2C Interface Timing and Internal Register Description ............. 8
Theory of Operation ...................................................................... 10
Functional Description .................................................................. 12
Frequency Acquisition ............................................................... 12
Input Buffer ................................................................................. 12
Lock Detector Operation .......................................................... 12
SQUELCH Mode ........................................................................ 13
System Reset ................................................................................ 13
I2C Interface ................................................................................ 13
Applications Information .............................................................. 14
PCB Design Guidelines ............................................................. 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN2805
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SPECIFICATIONS
TA = T
unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS
QUANTIZER—AC CHARACTERISTICS
LOSS-OF-LOCK (LOL) DETECT
ACQUISITION TIME
DATA RATE READBACK ACCURACY
POWER SUPPLY
OPERATING TEMPERATURE RANGE −40 +85 °C
to T
MIN
Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V
Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V
Data Rate 1250 Mbps
S11 @ 2.5 GHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF
VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time 200 μs
Lock-to-Data Mode GbE 1.5 ms
Optional Lock to REFCLK Mode 20.0 ms
Fine Readback In addition to REFCLK accuracy 100 ppm
Power Supply Voltage 3.0 3.3 3.6 V
Power Supply Current Locked to 1.25 Gbps 118 131 mA
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
JITTER SPECIFICATIONS
TA = T
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
to T
MIN
Jitter Peaking 0 0.03 dB
Jitter Generation 0.001 0.003 UI rms
0.02 0.04 UI p-p
Jitter Tolerance GbE, IEEE 802.3, 637 kHz 0.749 UI p-p
, VCC = V
MAX
MIN
to V
, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
MAX
Rev. 0 | Page 3 of 16
ADN2805
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OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS
CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN
Differential Output Swing VOD (see Figure 3) 240 300 400 mV
Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω
LVDS Outputs Timing
Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), GbE 360 400 440 ps
Hold Time TH (see Figure 2), GbE 360 400 440 ps
I2C® INTERFACE DC CHARACTERISTICS LVCMOS
Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, I
I2C INTERFACE TIMING See Figure 10
SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time tR/tF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t
REFCLK CHARACTERISTICS Optional lock-to-REFCLK mode
Input Voltage Range @ REFCLKP or REFCLKN
Input Low Voltage VIL 0 V
Input High Voltage VIH VCC V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = 2.0 mA 0.4 V
1
Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed.
= 3.0 mA 0.4 V
OL
600 ns
HIGH
1300 ns
LOW
600 ns
HD;STA
600 ns
SU;STA
100 ns
SU;DAT
300 ns
HD;DAT
600 ns
SU;STO
1300 ns
BUF
1
300 ns
Rev. 0 | Page 4 of 16
ADN2805
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Timing Characteristics
CLKOUT P
T
T
S
DATAOUTP/
DATAOUTN
V
OH
H
Figure 2. Output Timing
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
07121-002
V
OS
V
OL
|VOD|
7121-003
Figure 3. Differential Output Specifications
5mA
R
LOAD
V
100Ω
5mA
SIMPLIFIED LVDS
OUTPUT STAGE
100Ω
DIFF
07121-004
Figure 4. Differential Output Stage
Rev. 0 | Page 5 of 16
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