ANALOG DEVICES ADN2804 Service Manual

622 Mbps Clock and Data Recovery IC

www.BDTIC.com/ADI

FEATURES

Exceeds SONET requirements for jitter transfer/

generation/tolerance
Quantizer sensitivity: 3.3 mV typical
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 423 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free

APPLICATIONS

BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers

with Integrated Limiting Amplifier

ADN2804

GENERAL DESCRIPTION

The ADN2804 provides the receiver functions of quantization,
signal level detect, clock and data recovery, and data retiming
for 622 Mbps NRZ data. The ADN2804 automatically locks to
622 Mbps data without the need for an external reference clock
or programming. In the absence of input data, the output clock
drifts no more than ±5%. All SONET jitter requirements are
met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,

n implement a highly integrated, low cost, low power fiber

ca
optic receiver.

The receiver’s front-end loss-of-signal (LOS) detector circuit

dicates when the input signal level falls below a user-adjustable

in
threshold. The LOS detect circuit has hysteresis to prevent chatter
at the output.

The ADN2804 is available in a compact 5 mm × 5 mm,
32-lead LFCS

P.

FUNCTIONAL BLOCK DIAGRAM

REFCLKP/REFCLKN

(OPTIO NAL)

SLICEP/SLICEN

PIN

NIN

VREF

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

QUANTIZER

LOS

DETECT

LOSTHRADJ CLKOUTP/

PHASE

SHIFTER

RE-TIMING

DATAOUTP/
DATAOUTN

DATA

2

Figure 1.

LOL

FREQUENCY

DETECT

PHASE

DETECT

CLKOUTN

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

LOOP

FILTER

LOOP

FILTER

2

VCC VEECF1 CF2

ADN2804

VCO

5801-001

ADN2804

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Jitter Specifications......................................................................... 13

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Jitter Specifications....................................................................... 4

Output and Timing Specifications ............................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

2

I

C Interface Timing and Internal Register Description........... 10

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 14

Functional Description.................................................................. 16

Frequency Acquisition............................................................... 16

Limiting Amplifier ..................................................................... 16

Slice Adjust.................................................................................. 16

Loss-of-Signal (LOS) Detector ................................................. 16

Lock Detector Operation .......................................................... 17

SQUELCH Modes...................................................................... 17

2

I

C Interface ................................................................................ 17

Reference Clock (Optional) ...................................................... 19

Applications Information.............................................................. 21

PCB Design Guidelines ............................................................. 21

DC-Coupled Application.......................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

2/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADN2804

www.BDTIC.com/ADI

SPECIFICATIONS

TA = T
unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

QUANTIZER—DC CHARACTERISTICS

QUANTIZER—AC CHARACTERISTICS

QUANTIZER—SLICE ADJUSTMENT

LOSS-OF-SIGNAL (LOS) DETECT

R

R
R

LOSS-OF-LOCK (LOL) DETECT

ACQUISITION TIME

DATA RATE READBACK ACCURACY

POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V
POWER SUPPLY CURRENT Locked to 622.08 Mbps 128 mA
OPERATING TEMPERATURE RANGE –40 +85 °C

1

PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.

2

When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the

ADN2804 input stage.

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 2.0 V
Input Common-Mode Level DC-coupled (see Figure 27, Figure 28, and Figure 29) 2.3 2.5 2.8 V
Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10

–10

6 3.3 mV p-p
Input Offset 500 μV
Input RMS Noise BER = 1 × 10

–10

290 μV rms

Data Rate 622 Mbps
Output Clock Range Absence of input data 622 ± 5% MHz
S11 @ 622 MHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF

Gain SLICEP − SLICEN = ±0.5 V 0.10 0.11 0.13 V/V
Differential Control Voltage Input SLICEP − SLICEN −0.95 +0.95 V
Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset 1 mV

Loss-of-Signal Detect Range (see Figure 6) R

= 0 Ω 14.9 16.7 18.4 mV

THRESH

= 100 kΩ 2.6 3.5 4.4 mV

THRESH

Hysteresis (Electrical) OC-12

= 0 Ω 6.2 6.9 7.7 dB

THRESH

= 100 kΩ 4.1 6.1 8.1 dB

THRESH

LOS Assert Time DC-coupled
LOS Deassert Time DC-coupled

2

2

500 ns
400 ns

VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time OC-12 200 μs

Lock to Data Mode OC-12 2.0 ms
Optional Lock to REFCLK Mode 20.0 ms

Fine Readback In addition to REFCLK accuracy
OC-12 100 ppm

Rev. 0 | Page 3 of 24

ADN2804

www.BDTIC.com/ADI

JITTER SPECIFICATIONS

TA = T
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

PHASE-LOCKED LOOP CHARACTERISTICS

30 Hz
300 Hz
25 kHz 2.5 UI p-p
250 kHz

1

Jitter tolerance of the ADN2804 at these jitter frequencies is better than what the test equipment is able to measure.

to T

MIN

Jitter Transfer Bandwidth OC-12 75 130 kHz
Jitter Peaking OC-12 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms

0.011 0.026 UI p-p
Jitter Tolerance OC-12, 223 − 1 PRBS

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,

MAX

1

1

1

100 UI p-p
44 UI p-p

1.0 UI p-p

Rev. 0 | Page 4 of 24

ADN2804

www.BDTIC.com/ADI

OUTPUT AND TIMING SPECIFICATIONS

Table 3.

Parameter Conditions Min Typ Max Unit

LVDS OUTPUT CHARACTERISTICS

(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)

Output Voltage High VOH (see Figure 3) 1475 mV
Output Voltage Low VOL (see Figure 3) 925 mV
Differential Output Swing VOD (see Figure 3) 250 320 400 mV

Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100 Ω

LVDS Outputs’ Timing

Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time TS (see Figure 2), OC-12 760 800 840 ps
Hold Time TH (see Figure 2), OC-12 760 800 840 ps

I2C INTERFACE DC CHARACTERISTICS LVCMOS

Input High Voltage VIH 0.7 VCC V
Input Low Voltage VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA
Output Low Voltage VOL, IOL = 3.0 mA 0.4 V

I2C INTERFACE TIMING See Figure 11

SCK Clock Frequency 400 kHz
SCK Pulse Width High t
SCK Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb
Stop Condition Setup Time t
Bus Free Time Between a Stop and a Start t

REFCLK CHARACTERISTICS Optional lock to REFCLK mode

Input Voltage Range @ REFCLKP or REFCLKN
V
V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH, VIN = 2.4 V 5 μA
Input Low Current IIL, VIN = 0.4 V −5 μA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage VOH, IOH = −2.0 mA 2.4 V
Output Low Voltage VOL, IOL = +2.0 mA 0.4 V

1

Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.

600 ns

HIGH

1300 ns

LOW

600 ns

HD;STA

600 ns

SU;STA

100 ns

SU;DAT

300 ns

HD;DAT

600 ns

SU;STO

1300 ns

BUF

0 V

IL

VCC V

IH

1

300 ns

Rev. 0 | Page 5 of 24

ADN2804

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = T

0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted.

Table 4.

Parameter Rating

Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

MIN

to T

, VCC = V

MAX

MIN

to V

, VEE = 0 V, CF =

MAX

Stress above those listed under Absolute Maximum Ratings may
ca

use permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θ

= 28°C/W.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

ADN2804

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

CLKOUTP

T

T

S

DATAOUTP/

DATAOUTN

V

OH

H

Figure 2. Output Timing

DIFFERENTIAL CLKOUTP/ N, DATAOUTP/N

05801-002

V

OS

V

OL

|VOD|

5801-032

Figure 3. Differential Output Specifications

5mA

R

LOAD

V

100Ω

5mA

SIMPLIFIED LVDS

OUTPUT STAGE

100Ω

DIFF

05801-033

Figure 4. Differential Output Stage

Rev. 0 | Page 7 of 24

ADN2804

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 TEST2

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

TEST1 1

VCC 2

VREF 3

NIN 4

PIN 5
SLICEP 6
SLICEN 7

VEE 8

* THERE IS AN EXPOSED PAD ON THE BOTTOM OF

THE PACKAGE THAT MUST BE CONNECT ED TO GND.

PIN 1
INDICATOR

ADN2804*

TOP VIEW

(Not to Scale)

VCC 12

THRADJ 9

REFCLKP 10

REFCLKN 11

CF2 14

VEE 13

CF1 15

LOL 16

24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE

05801-004

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type

1 TEST1 Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limiting Amplifier, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 LOS DO Loss-of-Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND.

1

Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

1

Description

Rev. 0 | Page 8 of 24