ANALOG DEVICES ADN2531 Service Manual

11.3 Gbps, Active Back-Termination,

VCCA

FEATURES

3.3 V operation
Up to 11.3 Gbps operation
Typical 26 ps rise/fall times
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p differential
Automatic laser shutdown (ALS)
Crosspoint adjustment (CPA)
VCSEL, FP, DFB laser support
SFF/SFP/XFP/SFP+ MSA compliant
Optical evaluation board available
Compact, 3 mm × 3 mm LFCSP

APPLICATIONS

Optical transmitters, up to 11.3 Gbps, for SONET/SDH,

Ethernet, and Fibre Channel applications
SFF/SFP/SFP+/XFP/X2/XENPAK/XPAK MSA compliant
300-pin optical modules, up to 11.3 Gbps

Differential Laser Diode Driver

ADN2531

GENERAL DESCRIPTION

The ADN2531 laser diode driver can work with directly
modulated laser diodes, including vertical-cavity surface-emitting
laser (VCSEL), Fabry-Perot (FP) lasers, and distributed feedback
(DFB) lasers, with a differential loading resistance ranging from
5 Ω to 140 Ω. The active back-termination in the ADN2531
absorbs signal reflections from the laser diode side of the output
transmission lines, enabling excellent optical eye quality even when
the TOSA end of the output transmission lines is significantly
mismatched. The ADN2531 is a SFP+ MSA-compliant device,
and its small package and enhanced ESD protection provides
the optimum solution for compact modules in which laser
diodes are packaged in low pin-count optical subassemblies.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various average
optical power and extinction ratio control schemes, including a
closed-loop or a look-up table control. The automatic laser shut­down (ALS) feature allows turning the bias on and off while
simultaneously modulating currents by driving the ALS pin with
a low voltage transistor-to-transistor logic (LVTTL) source.

The product is available in a space-saving, 3 mm × 3 mm LFCSP
package and operates from −40°C to +100°C.

FUNCTIONAL BLOCK DIAGRAM

CPA

VCC

50Ω 50Ω

GND

DATAP

DATAN

400Ω

MSET GND BSET

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

200Ω

CROSSPOINT

ADJUST

LS

200Ω

ADN2531

100Ω

200Ω 10Ω

I

MOD

VCC

IMODP

IMODN

IBMON
IBIAS

07881-001

VCC

800Ω

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADN2531

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Package Thermal Specifications ................................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Test Circuit ...................................................................................... 10

Theory of Operation ...................................................................... 11

REVISION HISTORY

9/09—Revision 0: Initial Version

Input Stage ................................................................................... 11

Bias Current ................................................................................ 11

Automatic Laser Shutdown (ALS) ........................................... 12

Modulation Current ................................................................... 12

Load Mistermination ................................................................. 14

Crosspoint Adjust ....................................................................... 14

Power Consumption .................................................................. 14

Applications Information .............................................................. 15

Typical Application Circuit ....................................................... 15

Layout Guidelines....................................................................... 16

Design Example .......................................................................... 16

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

Rev. 0 | Page 2 of 20

ADN2531

SPECIFICATIONS

VCC = VCC
Typical values are specified at 25°C and I

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT (I

Bias Current Range 10 100 mA

Bias Current While ALS Asserted 300 μA ALS = high

Compliance Voltage

0.55 VCC V I

MODULATION CURRENT (IMODP, IMODN)

Modulation Current I

70 mA diff R

I

While ALS Asserted 500 μA diff ALS = high

MOD

Crosspoint Adjust (CPA) Range

Rise Time (20% to 80%)

Fall Time (20% to 80%)

Random Jitter

Deterministic Jitter

5.8 8.2 ps p-p 10.7 Gbps, CPA 35% to 65%

Deterministic Jitter

5.8 8.2 ps p-p 11.3 Gbps, CPA 35% to 65%

Differential |S22| −5 dB 5 GHz < f < 10 GHz, Z0 = 100 Ω differential

−10.5 dB f < 5 GHz, Z0 = 100 Ω differential

Compliance Voltage

DATA INPUTS (DATAP, DATAN)

Input Data Rate 11.3 Gbps NRZ

Differential Input Swing 0.15 1.6 V p-p diff Differential ac-coupled

Differential |S11| −15 dB f < 10 GHz, Z0 = 100 Ω differential

Input Termination Resistance 85 100 115 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to I

BSET Input Resistance 800 1000 1200 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to I

MSET Input Resistance 600 Ω

BIAS MONITOR (IBMON)

I

BMON

Accuracy of I

−4.0 +4.0 % 20 mA ≤ I

−2.5 +2.5 % 40 mA ≤ I

−2 +2 % 70 mA ≤ I
AUTOMATIC LASER SHUTDOWN (ALS)

VIH 2.0 V

VIL 0.8 V

IIL −20 +20 μA

IIH 0 200 μA

ALS Assert Time 2 μs

ALS Negate Time 10 μs

to VCC

MIN

BIAS

2, 3, 4

to I

Ratio 10 μA/mA

BIAS

to I

BIAS

, TA = −40°C to +100°C, 12 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.

MAX

= I

BIAS

= 40 mA with crosspoint adjust disabled, unless otherwise noted.

MOD

)

1

0.6 V

Range 10 80 mA diff R

MOD

2

2, 3 , 4

2, 3, 4

<0.5 ps rms

2, 4, 5

2, 4, 6

5.4 8.2 ps

1

V

Gain 100 mA/V

BIAS

Gain 120 mA/V

MOD

Ratio −5.0 +5.0 % 10 mA ≤ I

BMON

35 65 %

26 32.5 ps

26 32.5 ps

5.4 8.2 ps p-p 10.7 Gbps, CPA disabled

− 1.1 VCC + 1.1 V

CC

V I

CC

= 80 mA

BIAS

= 10 mA

BIAS

= 5 Ω to 50 Ω differential

LOAD

= 100 Ω differential

LOAD

p-p 11.3 Gbps, CPA disabled

< 20 mA, R

BIAS

< 40 mA, R

BIAS

< 70 mA, R

BIAS

< 80 mA, R

BIAS

Rising edge of ALS to falling edge of I

below 10% of nominal; see Figure 2

I

MOD

Falling edge of ALS to rising edge of I
I

above 90% of nominal; see Figure 2

MOD

IBMON

IBMON

IBMON

IBMON

7

= 750 Ω
= 750 Ω
= 750 Ω
= 750 Ω

BIAS

BIAS

7

and

and

Rev. 0 | Page 3 of 20

ADN2531

A

A

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

VCC 3.0 3.3 3.6 V

8

I

36 mA V

CC

9

I

55 62 mA V

SUPPLY

1

The voltage between the pin with the specified compliance voltage and GND.

2

Specified for TA = −40°C to +85°C due to test equipment limitation. See the section for data on performance for TA = −40°C to +100°C. Typical Performance Characteristics

3

The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.

4

Measured using the high speed characterization circuit shown in Figure 22.

5

The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.

6

The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.

7

Measured at balanced IMODP and IMODN.

8

Only includes current in the ADN2531 VCC pins.

9

Includes current in ADN2531 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the section for total supply current calculation. Power Consumption

PACKAGE THERMAL SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

θ

65 72.2 79.4 °C/W Thermal resistance from junction to top of package.

J-TOP

θ

2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.

J-PAD

IC Junction Temperature 125 °C

ALS

LS

NEGATE TIME

BSET

BSET

= V
= V

MSET

MSET

= 0 V
= 0 V

ND I

I

BIAS
MOD

90%

10%

ALS

ASSERT TIME

Figure 2. ALS Timing Diagram

t

t

07881-002

Rev. 0 | Page 4 of 20

ADN2531

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage: VCC to GND −0.3 V to +4.2 V
IMODP, IMODN to GND VCC − 1.5 V to 4.5 V
DATAP, DATAN to GND VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
ESD on IMODP/IMODN1 200 V HBM
ESD on All Other Pins1 1.5 kV HBM
Junction Temperature 150°C
Storage Temperature Range −65°C to +125°C

1

HBM = human body model.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 20

ADN2531

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

DATAN

DATAP

VCC

161514

13

12

VCC

BSET

11

IBMON

10

IBIAS

9GND

07881-003

1MSET

PIN 1
INDICATOR

2

CPA
ALS

NOTES

1. THERE ISAN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST BE
CONNECTED TO THE VCC OR GND PLANE.

3
4GND

ADN2531

TOP VIEW

(Not to S cale)

5VCC

678

IMODP

IMODN

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 MSET Input Modulation Current Control Input
2 CPA Input Crosspoint Adjust Control Input
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad EP Power Connect to the VCC or GND plane

Rev. 0 | Page 6 of 20

ADN2531

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.

35

10

30

25

20

15

RISE TIME (ps)

10

5

0

10 30 50 70

Figure 4. Rise Time vs. I

35

30

25

20

15

FALL TIME (ps)

10

5

0

10 20 30 40 50 60 70 80

Figure 5. Fall Time vs. I

I

I

MOD

MOD

(mA)

(mA)

MOD

MOD

8

6

4

2

DETERMINISTIC JITTER (ps p-p)

0

10 20 30 40 50 60 70 80

07881-004

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

RANDOM JITT E R (ps rms)

0.2

0.1

0

10 20 30 40 50 60 70 80

07881-005

10.7GBPS

11.3GBPS

I

(mA)

MOD

Figure 7. Deterministic Jitter vs. I

I

(mA)

MOD

Figure 8. Random Jitter vs. I

MOD

MOD

07881-007

07881-008

0

–5

–10

–15

–20

–25

–30

DIFFERENT IAL |S11| (dB)

–35

–40

FREQUENCY (G Hz )

1501234567891011121314

07881-006

Figure 6. Differential |S11|

0

–5

–10

–15

–20

–25

DIFFERENTIAL |S 22| (dB)

–30

–35

0 2.5 5.0 7.5 10.0 12.5 15.0

FREQUENCY (G Hz )

Figure 9. Differential |S22|

07881-009

Rev. 0 | Page 7 of 20

ADN2531

30

25

20

15

RISE TIM E (ps)

10

5

0

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 10. Rise Time vs. Temperature

(Worse-Case Conditions, CPA Disabled)

07881-010

10

9

8

7

6

5

4

3

DETERMINISTIC JITTER (ps p-p)

2

1
–40 –20 0 20 40 60 80 100

10.7GBPS

11.3GBPS

TEMPERATURE (°C)

Figure 13. Deterministic Jitter vs. Temperature

(Worse-Case Conditions, CPA Disabled)

07881-013

30

25

20

15

FALL TIME (ps)

10

5

0

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 11. Fall Time vs. Temperature

(Worst-Case Conditions, CPA Disabled)

1.0

0.8

0.6

0.4

RANDOM JITTER (ps rms)

0.2

75

65

55

45

35

CROSSPOI NT PERCENTAGE ( %)

25

15

7881-011

1.0 1.2 1.4 1.6 1.8 2.0 2.2

Figure 14. I

Eye Diagram Crosspoint vs. CPA Input Peripheral Voltage and VCC

MOD

75

65

55

45

35

CROSSPOINT PERCENTAGE ( %)

25

VCC = 3.0V
VCC = 3.3V
VCC = 3.6V

CPA INPUT PERI P HE RAL VOLTAGE (V)

= 40 mA)

(I

MOD

TA = –40°C
TA = +85°C
TA = +25°C
TA = +100°C

2.4

07881-014

0
–40 –20 0 20 40 60 80 100

TEMPERATURE ( °C)

Figure 12. Random Jitter vs. Temperature

(Worst-Case Conditions, CPA Disabled [Worst-Case I

MOD

= 40 mA])

07881-012

Rev. 0 | Page 8 of 20

15

Figure 15. I

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

MOD

CPA INPUT PERI P HE RAL VOLTAG E (V)

Eye Diagram Crosspoint vs. CPA Input Peripheral Voltage and

Ambient Temperature (I

= 40 mA)

MOD

07881-015

ADN2531

m

m

m

280
260
240
220
200
180

A)

160

(

140
120

TOTAL

I

100

80
60
40
20

0

0 2040608

12

10

8

6

100mA I

BIAS

50mA I

BIAS

10mA I

BIAS

CURRENT (mA)

I

MOD

Figure 16. Total Supply Current vs. I

40mA 20mA

MOD

and I

BIAS

0

07881-016

135
130
125
120
115
110
105
100

95
90
85
80

A)

75

(

70
65
60

MOD

I

55
50
45
40
35
30
25
20
15
10

5
0

0 0.2 0.4 0.6 0.8 1.0 1.2

Figure 19. I

MOD

CROSSING

vs.V

R

LOAD

V

MSET

at Various R

MSET

= 5Ω

(V)

1 LEVEL1 LEVEL

R

LOAD

= 50Ω

LOAD

R

LOAD

Resistors

= 12Ω

07881-119

NUMBER OF HITS

4

2

0

26.0 27.026.5 27.5
AVERAGE RISE/FALL TIME (ps)

28.0 28.5 29.0 29.5

Figure 17. Average Rise/Fall Time Distribution vs. I

120
110
100

90
80
70

A)
(

60

BIAS

50

I

40
30
20
10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Figure 18. I

TA = –40°C
TA = +25°C
TA = +85°C

vs. V

BIAS

V

(V)

BSET

at Various Temperatures

BEST

MOD

07881-017

CH1 17.4mV /DIV

0V

07881-018

Figure 20. Electrical Eye Diagram

= 40 mA, PRBS31 Pattern at 10.3125 Gbps)

(I

MOD

CH2 16.4mV/DIV
–6.0mV

Figure 21. Filtered 10 Gb Ethernet Optical Eye Using NX8346TS DFB (PRBS31

0 LEVEL0 LEVEL

07881-019

07881-121

Pattern at 10.3125 Gbps)

Rev. 0 | Page 9 of 20

ADN2531

VEEV

V

TEST CIRCUIT

= 50Ω

Z

0

J2

GND GND GND

J3

GND GND

DC BLOCK

DC BLOCK

EE

TP1

VCC

DATAP

DATAN

VCC

V

EE

V

CPA

750Ω

TP2

ADN2531

J8 J5

V

EE

V

BSET

BSET IBMON IBIAS GND

GND

Z0 = 50Ω Z0 = 50Ω

Z0 = 50ΩZ0 = 50Ω

GND

MSET CPA ALS GND

V

MSET

Figure 22. High Speed Characterization Circuit

EE

GND

10Ω

10nF

VCC

IMODP

IMODN

VCC

GND GND GND

GND

200Ω

GNDGND

10nF

V

EE

10µF

50Ω

50Ω

GND

GND

V

Z

GND

EE

GND

BIAS TEE

ADAPTER

GND

= 50Ω

0

BIAS TEE

GND

BIAS TEE: PICOSECO ND P ULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE9436 2.92mm

ATTENUATOR: PASTERNACK PE7046-10 2.92mm

ADAPTER

FEMALE-TO-FEMALEADAPTER

10dB ATTENUATOR

ATTENUATOR

ATTENUATOR

GND

50Ω

OSCILLOSCOPE

50Ω

GND

07881-021

Rev. 0 | Page 10 of 20

ADN2531

V

THEORY OF OPERATION

As shown in Figure 1, the ADN2531 consists of an input stage and
two voltage-controlled current sources for bias and modulation.
The bias current is available at the IBIAS pin. It is controlled by the
voltage at the BSET pin and can be monitored at the IBMON pin.
The differential modulation current is available at the IMODP
and IMODN pins. It is controlled by the voltage at the MSET pin.

The output stage implements the active back-termination
circuitry for proper transmission line matching and power
consumption reduction. The ADN2531 can drive a load with
differential resistance ranging from 5 Ω to 140 Ω. The excellent
back-termination in the ADN2531 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated.

INPUT STAGE

The input stage of the ADN2531 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 23.

CC

DATAP

DATAN

Figure 23. Equivalent Circuit of the Input Stage

The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2531 with single-ended data signal sources.

The ADN2531 input stage must be ac-coupled to the signal source
to eliminate the need for matching between the common-mode
voltages of the data signal source and the input stage of the driver
(see Figure 24). The ac coupling capacitors should have an
impedance less than 50 Ω over the required frequency range.
Generally, this is achieved using 10 nF to 100 nF capacitors, for
more than 1 Gbps operation.

50Ω

50Ω

V

CC

07881-022

50Ω 50Ω

DATA SIGNAL SOURCE

Figure 24. AC Coupling the Data Source to the ADN2531 Data Inputs

C

C

BIAS CURRENT

The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 25.

V

CC

ADN2531

800Ω

200Ω

Figure 25. Voltage-to-Current Converter Used to Generate I

The BSET to I

voltage-to-current conversion factor is set

BIAS

at 100 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/100. By connecting a 750 Ω resistor between IBMON
and GND, the bias current can be monitored as a voltage across
the resistor. A low temperature coefficient precision resistor must
be used for the IBMON resistor (R
of R

due to tolerances or drift in its value over temperature

IBMON

contributes to the overall error budget for the I

If the IBMON voltage is being connected to an ADC for analog­to-digital conversion, R

IBMON

minimize errors due to voltage drops on the ground plane. See the
Design Example section for example calculations of the accuracy of
the I

monitor as a percentage of the nominal I

BIAS

200Ω

GND

should be placed close to the ADC to

ADN2531

DATAP

DATAN

I

BMON

IBMONBSET
IBIAS

I

BIAS

2Ω

). Any error in the value

IBMON

monitor voltage.

BIAS

value.

BIAS

07881-023

07881-024

BIAS

Rev. 0 | Page 11 of 20

ADN2531

V

V

V

V

V

A

VCCV

The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 26 to Figure 28.

CC

BSET

800Ω

200Ω

Figure 26. Equivalent Circuit of the BSET Pin

IBIAS

CC

100Ω

10Ω

Figure 27. Equivalent Circuit of the IBIAS Pin

CC

V

CC

Figure 28. Equivalent Circuit of the IBMON Pin

CC

IBMON

V

CC

2kΩ

500Ω

100Ω

CC

07881-025

07881-026

07881-027

The recommended configuration for the BSET, IBIAS, and
IBMON pins is shown in Figure 29.

TO LASE R C

THODE

AUTOMATIC LASER SHUTDOWN (ALS)

The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Tab l e 5.

Table 5. ALS Logic States

ALS Logic State I

BIAS

and I

MOD

High Disabled
Low Enabled
Floating Enabled

The ALS pin is compatible with 3.3 V CMOS and LVTTL logic
levels. Its equivalent circuit is shown in Figure 30.

CC

ALS

Figure 30. Equivalent Circuit of the ALS Pin

42kΩ

100Ω

2kΩ

07881-029

MODULATION CURRENT

The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current via a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 31.

V

CC

IMODP

I

100Ω

MOD

IMODN

I

L

BIAS

IBIAS

ADN2531

V

BSET

BSET

GND

IBMON

R

IBMON

750Ω

07881-028

Figure 29. Recommended Configuration for BSET, IBIAS, and IBMON Pins

The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Tab l e 1). The
maximum compliance voltage is specified for only two bias
current levels (10 mA and 100 mA), but it can be calculated for
any bias current by

V

COMPLIANCE

(V) = VCC (V) − 0.75 − 4.4 × I

BIAS

(A)

See the Headroom Calculations section for examples.

The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see Tabl e 6.

Rev. 0 | Page 12 of 20

FROM CPA STAGE

MSET

400Ω

200Ω

GND

ADN2531

Figure 31. Generation of Modulation Current on the ADN2531

The dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.
This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive back­termination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current (I

), the range of which is specified in Ta b le 1 , flows

MOD

into the external load.

07881-030

ADN2531

V

V

VCCV

V

V

V

V

The equivalent circuits for the MSET, IMODP, and IMODN pins
are shown in Figure 32 and Figure 33. The two 50 Ω resistors in
Figure 33 represent the active back-termination resistance.

CC

MSET

400Ω

200Ω

Figure 32. Equivalent Circuit of the MSET Pin

50Ω

7.7Ω 7.7Ω

Figure 33. Equivalent Circuit of the IMODP and IMODN Pins

CC

07881-031

50Ω

CC

07881-032

IMODPIMODN

The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 34. See Ta b le 6 for recom­mended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
connected as shown in Figure 34.

MSET

IBIAS

ADN2531

IMODP

IMODN

MSET

GND

Figure 34. Recommended Configuration for the

MSET, IMODP, and IMODN Pins

V

CC

L L

= 25Ω Z0 = 25Ω

Z

0

Z

L

Z

0

= 100Ω

= 25Ω

C

C

L

V

CC

Z

0

= 25Ω

L

V

CC

FP/DFB
TOSA

07881-033

The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 35.

200
190
180
170
160
150
140
130
120
110

GAIN (mA/V)

100

90
80
70
60
50

0 102030405060

MAXIMUM

TYPICAL

MINIMUM

DIFFERENTIAL R

LOAD

(Ω)

07881-034

Figure 35. MSET Voltage to Modulation Current Ratio vs.

Differential Load Resistance

Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the Applications Information section).

The circuit used to drive the MSET voltage must be able to
drive the 600 Ω resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2531 (IMODP and IMODN pins) must
be ac-coupled to the load. The voltages at these pins have a dc
component equal to V
peak-to-peak amplitude of I
load impedance (R

and an ac component with single-ended

CC

× 50 Ω. This is the case when the

MOD

) is less than 100 Ω differential because

TOSA

the transmission line characteristic impedance sets the peak-to­peak amplitude. For the case where R
the single-ended, peak-to-peak amplitude is I

is greater than 100 Ω,

TOSA

× R

MOD

TOSA

÷ 2.

For proper operation of the output stage, the voltages at the
IMODP and IMODN pins must be between the compliance
voltage specifications for this pin over supply, temperature, and
modulation current range, as shown in Figure 36. See the
Headroom Calculations section for examples of headroom
calculations.

IMODP,VIMODN

+ 1.1V

CC

NORMAL OPERATION RE GION

V

CC

– 1.1V

CC

7881-035

Figure 36. Allowable Range for the Voltage at IMODP and IMODN

Rev. 0 | Page 13 of 20

ADN2531

A

(

)

θ×+

θ×θ

×

LOAD MISTERMINATION

Due to its excellent S22 performance, the ADN2531 can drive
differential loads that range from 5 Ω to 140 Ω. In practice, many
TOSAs have differential resistance not equal to 100 Ω. In this
case, with 100 Ω differential transmission lines connecting the
ADN2531 to the load, the load end of the transmission lines are
misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the ADN2531
absorbs these reflections, preventing their reflection back to the
load. This enables excellent optical eye quality to be achieved even
when the load end of the transmission lines is significantly mis­terminated. The connection between the load and the ADN2531
must be made with 100 Ω differential (50 Ω single-ended)
transmission lines so that the driver end of the transmission
lines is properly terminated.

CROSSPOINT ADJUST

The crossing level in the output electrical eye diagram can be
adjusted between 35% and 65% using the crosspoint adjust (CPA)
control input. This can be used to compensate for asymmetry in
the laser response and to optimize the optical eye mask margin.
The CPA input is a voltage-control input, and a plot of eye cross­point vs. CPA control voltage is shown in Figure 14 and Figure 15
in the Typical Performance Characteristics section. The equivalent
circuit for the CPA pin is shown in Figure 37. To disable the
crosspoint adjust function and set the eye crossing to 50%, the
CPA pin should be tied to V

7kΩ

V

CC

Figure 37. Equivalent Circuit for CPA Pin

CPA

7kΩ

.

CC

7kΩ

07881-036

POWER CONSUMPTION

The power dissipated by the ADN2531 is given by

V

⎛

VP ×+

CC

MSET

⎜
⎝

+×=

8.5

where:

V

is the power supply voltage.

CC

I

is the bias current generated by the ADN2531.

BIAS

is the voltage applied to the MSET pin.

V

MSET

I

is the sum of the current that flows into the VCC, IMODP,

SUPPLY

and IMODN pins when V

V

is the average voltage on the IBIAS pin.

IBIAS

BSET

= V

⎞
⎟

⎠

MSET

IVI

= 0 (see Tabl e 1).

BIASIBIASSUPPLY

Rev. 0 | Page 14 of 20

Considering V
V

to IBIAS, the dissipated power becomes

BSET

VP

CC

To ensure long-term reliable operation, the ADN2531 junction
temperature must not exceed 150°C, as specified in Tabl e 3. For
improved heat dissipation, the module case can be used as a
heat sink, as shown in Figure 38.

THERM

LCOMPOUND

DIE

PACKAGE

PCB

COPPER PLANE

Figure 38. Typical Optical Module Structure

A compact optical module is a complex thermal environment, and
calculations of device junction temperature using the junction-to­ambient thermal resistance (θ
accurate results. The following equation, derived from the
model in Figure 39, can be used to estimate the IC junction
temperature:

T

=

J

wher

e:

he temperature at the top of the package in °C.

T

is t

TOP

T

is the temperature at the package exposed paddle in °C

PAD

T

is the IC junction temperature in °C.

J

P is the ADN2531 power dissipation in wa

θ

is the thermal resistance from the IC junc

J-TOP

the package.
θ

J-PAD

is the th

ermal resistance from the IC junction to the

exposed paddle of the package.

Figure 39. Electrical Model for Thermal Calc ations

T

and T perature

TOP

can be determined by measuring the tem

PAD

at points inside the module, as shown in Figure 38. The thermo­couples should be positioned to obtain an accurate measurement of
the temperatures of the package top and paddle. θ
are given in Ta ble 2 .

= 10 V/A as the conversion factor from

BSET/IBIAS

V

⎛

MSET

⎜
⎝

+×=

T

VIAS

PADJ

−

⎞
⎟

⎠

MODULE CASE

TOP

T

J

T

PAD

) of the package do not yield

JA

−

TOPTOPJ

PADJ

−

⎛

×+

VI

⎜

IBIASSUPPLY

⎝

θ×+

−

θ+θ

TOPJ

−

tts.

T

TOP

θ

J-TOP

T

J

P

θ

T

T

J-PAD

PAD

PAD

T

TOP

V

⎞

BSET

⎟

/108.5

AV

⎠

THERMOCOUPLES

TTP

PADPADJ

TOPJ

−

.

tion to the top of

07881-038

ul

and θ

J-TOP

J-PAD

07881-037

ADN2531

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

Figure 40 shows a typical application circuit for the ADN2531.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 750 Ω resistor connected between
the IBMON pin and GND. The dc voltage applied to the CPA
pin controls the crosspoint in the output eye diagram. By tying
the CPA pin to V
allows the user to turn the bias and modulation currents on and
off, depending on the logic level applied to the pin. The data
signal source must be connected to the DATAP and DATAN
pins of the ADN2531 using 50 Ω transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 Ω differential (50 Ω
single-ended) transmission lines.

Tabl e 6 provides a list of recommended components for the ac
coupling interface between the ADN2531 and the TOSA. The
reference circuit can support up to 11.3 Gbps applications, and

, the CPA function is disabled. The ALS pin

CC

BSET

DATAP

DATAN

MSET

+3.3V

Z0 = 50Ω

= 50Ω

Z

0

GND

V

CC

V

CC

BSET IBMON IBIAS GND

VCC

DATAP

C1

DATAN

C2

VCC

MSET ALS GND

V

CC

C7
20µF

GND

R5
750Ω

TP1

ADN2531

CPA

CPA

Figure 40. Typical ADN2531 Application Circuit

ALS

IMODP

IMODN

the low frequency cutoff performance is dependent on the dc
blocking capacitance and the transmission line impedance. For
additional applications information and optical eye diagram
performance data, consult the relevant application notes on the
ADN2531 product page at www.analog.com.

Table 6. Recommended Components

Component Value Description

R1, R2 110 Ω 0603 size resistor
R3, R4 300 Ω 0603 size resistor
R13, R14 Varies

The resistor value and size are TOSA
load impedance dependent

C3, C4 100 nF

0402 size capacitor,
Phycomp 223878719849

L6, L7 160 nH

0603 size inductor,
Murata LQW18ANR16

L2, L3

0603 size chip ferrite bead, Murata
BLM18HG601

L1, L4, L5, L8 10 μH

0805 size inductor,
Murata LQM21FN100M70L

C8

V

CC

GND

GND

CC

CC

L1

L2

L3

L4 R2

V

CC

GND

C5

10nF

V

CC

V

VCC

Z

= 50Ω Z0 = 50Ω

0

Z0 = 50Ω Z0 = 50Ω

V

VCC

V

CC

C6

10nF
GND

L8

R1

R14

C4

C3

R13

L5 R3

V

CC

100nF

V

CC

R4

L7

TOSA

L6

07881-039

Rev. 0 | Page 15 of 20

ADN2531

K

LAYOUT GUIDELINES

Due to the high frequencies at which the ADN2531 o
care should be taken when designing the P

CB layout to obtain
optimum performance. For example, use controlled impedance
transmission lines for high speed signal paths, and keep the
length of transmission lines as short as possible to reduce losses
and pattern-dependent jitter. In addition, the PCB layout must
be symmetrical, both on the DATAP and DATAN inputs and o
the IMODP and IMODN outputs, to ensure a balance between
the differential signals.

Furthermore, all VCC and GND pins must be connected to
solid copper planes by using low inductance connections. Wh
these connections are made through vias, multiple vias can be
connected in parallel to reduce the parasitic inductance. Each
GND pin must be locally decoupled to VCC with high quality
capacitors (see Figure 40). If proper decoupling cannot be
achieved using a single capacitor, u

se multiple capacitors in
parallel for each GND pin. A 20 μF tantalum capacitor must be
used as the general decoupling capacitor for the entire module.

For recommended PCB layouts, including those suitable for the

FP+ and XFP modules, contact sales. For guidelines on the

S

rface-mount assembly of the ADN2531, see the AN-772

su
Application Note,

Lead Frame Chip Scale Package (LFCSP)

A Design and Manufacturing Guide for the

, on www.analog.com.

perates,

en

DESIGN EXAMPLE

Assuming that the impedance of the TOSA is 12 Ω, the forward
voltage of the laser at low current is V

= 40 mA, and VCC = 3.3 V, this design example calculates

I

MOD

• The headroom for the IBIAS, IMODP, and IMODN pins.

• The typical voltage required at the BSET and MSET pins to

produce the desired bias and modulation currents.

• The I

monitor accuracy over the I

BIAS

Headroom Calculations

To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Tab l e 1 .

Considering the typical application circuit shown in Figure 40,
the voltage at the IBIAS pin can be written as

V

= VCC − VF − (I

IBIAS

e:

wher

is the supply voltage.

V

CC

V

is the forward voltage across the laser at low current.

F

R

is the resistance of the TOSA.

TOSA

V

is the dc voltage drop across L5, L6, L7, and L8.

LA

BIAS

× R

For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Ta b le 1 .

Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that V

V

= 3.3 − 1.5 − (0.04 × 12) = 1.32 V

IBIAS

= 0 V, VF = 1.5 V, and I

LA

TOSA

= 1.5 V, I

F

BIAS

) − VLA

= 40 mA,

BIAS

current range.

= 40 mA,

BIAS

Rev. 0 | Page 16 of 20

Therefore, V

The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by

V

COMPLIANCE_MAX

n

For this example,

V = V − 0.75 − 4.4 × 0.04 = 2.374 V

COMPLIANCE_MAX CC

Therefore, V
requirement.

ulate the h a urrent pins

To calc eadroom t the modulation c
(IMODP and
to V du

CC

I

× 5 se R

MOD

operation of the ADN2531, t

pin should in region shown

output be with the normal operation
in Figure 36.

ing the dc ltage dro

Assum vo p across L1, L2, L3, and L4 is 0 V
and I

MOD

output pins is e

V

CC

Therefore, V
requirement.

The maximum voltage at the modulation output pins is equal to

V

CC

Therefore, V
requirement.

Headroom calculations must be repeated for the minimum and
maximum values of the required I
proper device operation over all operating conditions.

BSET and MSET Pin Voltage Calculations

To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2531 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required I
I

gain specified in Tabl e 1 . Assuming that I

BIAS

I

BIAS/VBSET

BSET voltage is given by

V

BSET

The BSET voltage range can be calculated using the required
I

range and the minimum and maximum BSET voltage to

BIAS

gain values specified in Ta b le 1 .

I

BIAS

The voltage required at the MSET pin to produce the desired
modulation current can be calculated using

V

MSET

K is the MSET voltage to I

where

= 1.32 V > 0.6 V, which satisfies the requirement

IBIAS

= VCC − 0.75 − 4.4 × I

= 1.32 V < 2.374 V, which s

IBIAS

IMO he

DN), tupvoltage has a dc component equal

e to the ac-co led

0 Ω becau is roper

configuration and a swing equal to

less than 100 Ω. For p

TOSA

(A)

BIAS

atisfies the

he voltage at each modulation

mA, nim odulation

is 40

− (I

+ (I

= 100 mA/V (which is the typical I

the mi

qual

to

× 12)/2 = VCC − 0.24 V

MOD

− 0.24 > VCC − 1.1 V, which satisfies the

CC

× 12)/2 = VCC + 0.24 V

MOD

+ 0.24 < VCC + 1.1 V, which satisfies the

CC

range can be calculated using the BSET voltage to

BIAS

I

(mA)

BIAS

mA/V100

I

MOD

=

um voltage at the m

and I

BIAS

40

100

===

V4.0

ratio.

MOD

ranges to ensure

MOD

= 40 mA and that

BIAS

BIAS/VBSET

ratio), the

ADN2531

e actual resistance of the TOSA The value of K depends on th This example assumes that the nominal value of I
and can be obtained from Figure 35. For a TOSA resistance of
12 Ω, the typical value of K is 110 mA/V. Assuming that I

MOD

40 mA and using the preceding equation, the MSET voltage is
given by

(mA)

I

V

MSET

MOD

mA/V110

40

110

V36.0

===

The MSET voltage range can be calculated using the required
I

range and the minim

MOD

um and maximum K values. These
values can be obtained from the minimum and maximum
curves in Figure 35.

IBIAS Monitor Accuracy Calculations

6

5

RATIO (%)

4

BMON

TO I

3

BIAS

2

=

and that the I
80 mA. The accuracy of the I
and is plotted in Fig 1

±4.3% for the mini

imum I

max

range for all operating conditions is 10 mA to

BIAS

BIAS

to I

ratio is given in Tabl

BMON

ure 4 .

41, t e IBMON outpu urrenReferring to Figur

e h t c t accuracy is

mum I

value of 80 mA.

BIAS

of 10 mA and ±3.0% for the

BIAS

The accuracy of the IBMON output current as a perc
the nominal I

for the minimum I

for the maximum I

is given by

BIAS

AccuracyIBMON

BIAS

AccuracyIBMON

BIAS

3.4

MIN

mA10_ ±=×=

100

value, and by

0.3

MAX

mA80_ ±=×=

100

value. This gives a worse-case accuracy
for the IBMON output current of ±6.0% of the nominal I
value over all operating conditions. The IBMON output curr
accuracy numbers can b
for t nd any other error

he 750 Ω IBMON resistor (R

sources to cal ulate an overall accuracy for the IBMON

c voltage.

e combined with the accuracy numbers

) a

IBMON

100

100

BIAS

mA40

mA40

is 40 mA

entage of

%0.6

BIAS

e 1

%075.1

ent

1

ACCURACY O F I

0

0

20

I

BIAS

Figure 41. Accuracy of I

(mA)

BIAS

to I

BMON

Ratio

100806040

07881-040

Rev. 0 | Page 17 of 20

ADN2531

OUTLINE DIMENSIONS

0.50

EXPOSED

PAD

R

E

0.40

0.30

16

1

4

5

P

N

I

N

I

D

*

1.65

1.50 SQ

1.35

0.25 MIN

IO

1

A

R

O

T

C

I

071708-A

0.6

0 MAX

BOTTOM VIEW

13

12

0.50

BSC

9
8

1.50 REF

FO PROPER CONNECTION OF
TH EXPOSED PAD, REFER TO
THE PIN CONF IGURAT N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA SHEET.

cale Package [LFCSP_VQ]

ry Thin Quad

PIN 1

INDICATOR

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

0.45

VIEW

0.30

0.23

0.18

TOP

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

*

COMPLIANT

EXCEPT FOR EXPOSED PAD DI MENSION.

TO

JEDEC STANDARDS MO - 220-VEED-2

Figure 42. 16-Lead Lead Frame Chip S

3 mm × 3 mm Body, Ve

(CP-16-3)

Dimensions shown in

millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADN2531ACPZ-WP
ADN2531ACPZ-R2
ADN2531ACPZ- 16-Lead LFCSP_VQ, 1,500-Piece Reel CP-16-3 F0K R7
EVAL-ADN2531-NTZ
EVAL-ADN2531-NPZ

1

Z = RoHS Compliant Part.

1

−40°C to +100°C 16-Lead LFCSP_VQ, 50-Piece Waffle Pack CP-16-3 F0K

1

−40°C to +100°C 16-Lead LFCSP_VQ, 250-Piece Reel CP-16-3 F0K

1

−40°C to +100°C

1

Optical Evaluation Board Without Laser Populated

1

Optical Evaluation Board with Laser Populated

Rev. 0 | Page 18 of 20

ADN2531

NOTES

Rev. 0 | Page 19 of 20

ADN2531

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07881-0-9/09(0)

Rev. 0 | Page 20 of 20