ANALOG DEVICES ADN2531 Service Manual
11.3 Gbps, Active Back-Termination,
VCCA
FEATURES
3.3 V operation
Up to 11.3 Gbps operation
Typical 26 ps rise/fall times
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p differential
Automatic laser shutdown (ALS)
Crosspoint adjustment (CPA)
VCSEL, FP, DFB laser support
SFF/SFP/XFP/SFP+ MSA compliant
Optical evaluation board available
Compact, 3 mm × 3 mm LFCSP
APPLICATIONS
Optical transmitters, up to 11.3 Gbps, for SONET/SDH,
Ethernet, and Fibre Channel applications
SFF/SFP/SFP+/XFP/X2/XENPAK/XPAK MSA compliant
300-pin optical modules, up to 11.3 Gbps
Differential Laser Diode Driver
ADN2531
GENERAL DESCRIPTION
The ADN2531 laser diode driver can work with directly
modulated laser diodes, including vertical-cavity surface-emitting
laser (VCSEL), Fabry-Perot (FP) lasers, and distributed feedback
(DFB) lasers, with a differential loading resistance ranging from
5 Ω to 140 Ω. The active back-termination in the ADN2531
absorbs signal reflections from the laser diode side of the output
transmission lines, enabling excellent optical eye quality even when
the TOSA end of the output transmission lines is significantly
mismatched. The ADN2531 is a SFP+ MSA-compliant device,
and its small package and enhanced ESD protection provides
the optimum solution for compact modules in which laser
diodes are packaged in low pin-count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various average
optical power and extinction ratio control schemes, including a
closed-loop or a look-up table control. The automatic laser shutdown (ALS) feature allows turning the bias on and off while
simultaneously modulating currents by driving the ALS pin with
a low voltage transistor-to-transistor logic (LVTTL) source.
The product is available in a space-saving, 3 mm × 3 mm LFCSP
package and operates from −40°C to +100°C.
FUNCTIONAL BLOCK DIAGRAM
CPA
VCC
50Ω 50Ω
GND
DATAP
DATAN
400Ω
MSET GND BSET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
200Ω
CROSSPOINT
ADJUST
LS
200Ω
ADN2531
100Ω
200Ω 10Ω
I
MOD
VCC
IMODP
IMODN
IBMON
IBIAS
07881-001
VCC
800Ω
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADN2531
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Package Thermal Specifications ................................................. 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuit ...................................................................................... 10
Theory of Operation ...................................................................... 11
REVISION HISTORY
9/09—Revision 0: Initial Version
Input Stage ................................................................................... 11
Bias Current ................................................................................ 11
Automatic Laser Shutdown (ALS) ........................................... 12
Modulation Current ................................................................... 12
Load Mistermination ................................................................. 14
Crosspoint Adjust ....................................................................... 14
Power Consumption .................................................................. 14
Applications Information .............................................................. 15
Typical Application Circuit ....................................................... 15
Layout Guidelines....................................................................... 16
Design Example .......................................................................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Rev. 0 | Page 2 of 20
ADN2531
SPECIFICATIONS
VCC = VCC
Typical values are specified at 25°C and I
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
BIAS CURRENT (I
Bias Current Range 10 100 mA
Bias Current While ALS Asserted 300 μA ALS = high
Compliance Voltage
0.55 VCC V I
MODULATION CURRENT (IMODP, IMODN)
Modulation Current I
70 mA diff R
I
While ALS Asserted 500 μA diff ALS = high
MOD
Crosspoint Adjust (CPA) Range
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Random Jitter
Deterministic Jitter
5.8 8.2 ps p-p 10.7 Gbps, CPA 35% to 65%
Deterministic Jitter
5.8 8.2 ps p-p 11.3 Gbps, CPA 35% to 65%
Differential |S22| −5 dB 5 GHz < f < 10 GHz, Z0 = 100 Ω differential
−10.5 dB f < 5 GHz, Z0 = 100 Ω differential
Compliance Voltage
DATA INPUTS (DATAP, DATAN)
Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.15 1.6 V p-p diff Differential ac-coupled
Differential |S11| −15 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to I
BSET Input Resistance 800 1000 1200 Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to I
MSET Input Resistance 600 Ω
BIAS MONITOR (IBMON)
I
BMON
Accuracy of I
−4.0 +4.0 % 20 mA ≤ I
−2.5 +2.5 % 40 mA ≤ I
−2 +2 % 70 mA ≤ I
AUTOMATIC LASER SHUTDOWN (ALS)
VIH 2.0 V
VIL 0.8 V
IIL −20 +20 μA
IIH 0 200 μA
ALS Assert Time 2 μs
ALS Negate Time 10 μs
to VCC
MIN
BIAS
2, 3, 4
to I
Ratio 10 μA/mA
BIAS
to I
BIAS
, TA = −40°C to +100°C, 12 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.
MAX
= I
BIAS
= 40 mA with crosspoint adjust disabled, unless otherwise noted.
MOD
)
1
0.6 V
Range 10 80 mA diff R
MOD
2
2, 3 , 4
2, 3, 4
<0.5 ps rms
2, 4, 5
2, 4, 6
5.4 8.2 ps
1
V
Gain 100 mA/V
BIAS
Gain 120 mA/V
MOD
Ratio −5.0 +5.0 % 10 mA ≤ I
BMON
35 65 %
26 32.5 ps
26 32.5 ps
5.4 8.2 ps p-p 10.7 Gbps, CPA disabled
− 1.1 VCC + 1.1 V
CC
V I
CC
= 80 mA
BIAS
= 10 mA
BIAS
= 5 Ω to 50 Ω differential
LOAD
= 100 Ω differential
LOAD
p-p 11.3 Gbps, CPA disabled
< 20 mA, R
BIAS
< 40 mA, R
BIAS
< 70 mA, R
BIAS
< 80 mA, R
BIAS
Rising edge of ALS to falling edge of I
below 10% of nominal; see Figure 2
I
MOD
Falling edge of ALS to rising edge of I
I
above 90% of nominal; see Figure 2
MOD
IBMON
IBMON
IBMON
IBMON
7
= 750 Ω
= 750 Ω
= 750 Ω
= 750 Ω
BIAS
BIAS
7
and
and
Rev. 0 | Page 3 of 20
ADN2531
A
A
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
VCC 3.0 3.3 3.6 V
8
I
36 mA V
CC
9
I
55 62 mA V
SUPPLY
1
The voltage between the pin with the specified compliance voltage and GND.
2
Specified for TA = −40°C to +85°C due to test equipment limitation. See the section for data on performance for TA = −40°C to +100°C. Typical Performance Characteristics
3
The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
4
Measured using the high speed characterization circuit shown in Figure 22.
5
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
6
The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.
7
Measured at balanced IMODP and IMODN.
8
Only includes current in the ADN2531 VCC pins.
9
Includes current in ADN2531 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the section for total supply current calculation. Power Consumption
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
θ
65 72.2 79.4 °C/W Thermal resistance from junction to top of package.
J-TOP
θ
2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.
J-PAD
IC Junction Temperature 125 °C
ALS
LS
NEGATE TIME
BSET
BSET
= V
= V
MSET
MSET
= 0 V
= 0 V
ND I
I
BIAS
MOD
90%
10%
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
t
t
07881-002
Rev. 0 | Page 4 of 20
ADN2531
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage: VCC to GND −0.3 V to +4.2 V
IMODP, IMODN to GND VCC − 1.5 V to 4.5 V
DATAP, DATAN to GND VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
ESD on IMODP/IMODN1 200 V HBM
ESD on All Other Pins1 1.5 kV HBM
Junction Temperature 150°C
Storage Temperature Range −65°C to +125°C
1
HBM = human body model.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 20
ADN2531
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
DATAN
DATAP
VCC
161514
13
12
VCC
BSET
11
IBMON
10
IBIAS
9GND
07881-003
1MSET
PIN 1
INDICATOR
2
CPA
ALS
NOTES
1. THERE ISAN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST BE
CONNECTED TO THE VCC OR GND PLANE.
3
4GND
ADN2531
TOP VIEW
(Not to S cale)
5VCC
678
IMODP
IMODN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic I/O Description
1 MSET Input Modulation Current Control Input
2 CPA Input Crosspoint Adjust Control Input
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad EP Power Connect to the VCC or GND plane
Rev. 0 | Page 6 of 20
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