Analog Devices ADN2530 prb Datasheet

10.7 Gbps Active Back-Termination,

A

Preliminary Technical Data

FEATURES

Up to 10.7 Gbps operation
Very low power: I
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Cross Point Adjust Function
PECL/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2 mA to 23 mA
Automatic laser shutdown (ALS)

3.3 V operation
Compact 3 mm × 3 mm LFCSP package
Voltage–input control for bias and modulation currents
XFP-compliant bias current monitor

APPLICATIONS

SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules

= 65 mA

CC

Differential VCSEL Driver

ADN2530

GENERAL DESCRIPTION

The ADN2530 VCSEL driver is designed for direct modulation
of packaged VCSELs. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
small package provides the optimum solution for compact
modules where VCSELs are packaged in low pin-count optical
subassemblies.

The differential data inputs are PECL/CML-compatible and
terminated with an internal 100 Ω differential resistor. This
minimizes signal reflections to the data signal source.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye cross
point in the output eye diagram is adjustable via the cross point
adjust (CPA) control voltage input.

The automatic laser shutdown feature allows the user to turn
on/off the bias and modulation currents by driving the ALS pin
with the proper logic levels.

FUNCTIONAL BLOCK DIAGRAM

800Ω

Adjust

200Ω

CP

Cross

Point

VCC ALS

VCC

50Ω 50Ω

GND

DATAP

DATAN

MSET GND BSET

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

VCC

Figure 1.

The product is available in a space saving 3 mm × 3 mm LFCSP
package specified from −40°C to +85°C.

ADN2530

100ΩIMOD

VCC

800Ω

200Ω

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

200Ω 10Ω

IMODP

IMODN

IBMON
IBIAS

02461-001

ADN2530 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Package Thermal Specifications................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

General........................................................................................... 9

Input Stage..................................................................................... 9

Bias Current .................................................................................. 9

Automatic Laser Shutdown (ALS) ........................................... 10

Modulation Current................................................................... 10

REVISION HISTORY

x/04—Revision PrB: Second Version

Cross Point Adjust...................................................................... 12

Power Consumption .................................................................. 12

Applications Information.............................................................. 14

Typical Application Circuit....................................................... 14

Layout Guidelines....................................................................... 15

Design Example.......................................................................... 15

Headroom Calculations ............................................................ 15

BSET and MSET Pin Voltage Calculation .............................. 15

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. PrB | Page 2 of 17

Preliminary Technical Data ADN2530

SPECIFICATIONS

VCC = VCC
noted. Typical values are specified at 25°C, IMOD = 10 mA, Cross Point Adjust disabled.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT(IBIAS)

Bias Current Range 2 25 mA
Bias current while ALS Asserted 50 µA ALS = high
Compliance Voltage1 0.5 VCC – 1.3 V IBIAS = 25 mA

0.5 VCC – 0.8 V IBIAS = 2 mA
MODULATION CURRENT (IMODP, IMODN)

Modulation Current Range 2 23 mA diff. R
Modulation Current while ALS Asserted 200 µA diff ALS = high
Rise time (20% to 80%)
Fall time (20% to 80%)
Random Jitter
Deterministic Jitter
Cross Point Adjust Range3 35 65 %
Differential |S22| −10 dB 5 Ghz < F < 10 GHz, Z0 = 100 Ω differential

−15 dB F < 5 GHz, Z0 = 100 Ω differential
Compliance Voltage1 VCC − 0.7 VCC + 0.7 V

DATA INPUTS (DATAP, DATAN)

Input Data Rate 10.7 Gbps NRZ
Differential Input Swing 0.4 1.6 V pk-pk diff. Differential ac-coupled
Differential |S11| −15 dB F < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to IBIAS Gain 15 20 24 mA/V
BSET Input Resistance 800 1000 1200 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to IMOD Gain 15 20 24 mA/V
MSET Input Resistance 800 1000 1200 Ω

BIAS MONITOR (IBMON)

IBMON to IBIAS Ratio 50 µA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 %

−4.0 +4.0 %

−2.5 +2.5 %

−2 +2 %

AUTOMATIC LASER SHUTDOWN (ALS)

VIH 2.4 V
VIL 0.8 V
IIL −20 +20 µA
IIH 0 200 µA
ALS Assert Time 10 µs

ALS Negate Time 10 µs

POWER SUPPLY

VCC 3.07 3.3 3.53 V
I

27 31 mA V

CC5

I

65 73 mA V

SUPPLY6

1

Refers to the voltage between the pin for which the compliance voltage is specified and GND.

2

The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.

3

Measured using the high speed characterization circuit shown in Figure 3.

4

The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.

5

Only includes current in the ADN2525 VCC pins.

6

Includes current in ADN2525 VCC pins and DC current in IMODP and IMODN pull-up inductors. See section on “Power Consumption” for total supply current

calculation.

to VCC

MIN

2, 3

0.4 0.9 ps rms

3,4

, TA = −40°C to +85°C, 100 Ω differential load impedance, Cross Point Adjust disabled, unless otherwise

MAX

LOAD

2, 3

24 32 ps

2, 3

24 32 ps

7.0 10 ps pk-pk

2 mA ≤ IBIAS < 4 mA, R
4 mA ≤ IBIAS < 8 mA, R
8 mA ≤ IBIAS < 14 mA, R
14 mA ≤ IBIAS < 25 mA, R

Rising edge of ALS to fall of IBIAS and IMOD below 10% of
nominal. See Figure 2

Falling edge of ALS to rise of IBIAS and IMOD above 90% of
nominal. See Figure 2

BSET

BSET

= 35 Ω to 100 Ω differential

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= V

= 0 V

MSET

= V

= 0 V

MSET

Rev. PrB | Page 3 of 17

ADN2530 Preliminary Technical Data

VEEV

V

Z

= 50Ω

0

J2

GND GND GND

J3

GND GND

ALS

IBIAS

AND IMOD

90%

10%

ALS

ASSERT TIME

Figure 2. ALS Timing Diagram

EE

TP1

VCC

DATAP

DATAN

VCC

750Ω

TP2

ADN2530

VBSET

BSET IBMON IBIAS GND

GND

Z

= 50Ω Z0 = 50Ω Z0 = 50Ω

0

10nF

10nF

GND

MSET CPA ALS GND

GND

10Ω

IMODP

IMODN

VCC

VCC

EE

10nF

GND

GND

GND

= 50Ω Z0 = 50ΩZ0 = 50ΩZ0 = 50Ω

Z

0

GND

ALS

NEGATE TIME

t

t

02461-002

GND

BIAS TEE

ADAPTOR

GND

ADAPTOR

GND

GNDGND

BIAS TEE
GND

ATTENUATOR

ATTENUATOR

GND

50Ω

OSCILLOSCOPE

50Ω

GND

VMSET

VEE

VCPA

J8 J5

VEE

GND GND GND

VEE

10nF

22µF

GND

VEE

BIAS TEE: Picosecond Pulse Labs Model 5542-219
Adaptor: Pasternack PE-9436 2.92mm female-to-female adaptor
Attenuator: Pasternack PE-7046 2.92mm 20dB attenuator

Figure 3. High Speed Characterization Circuit

02461-003

Rev. PrB | Page 4 of 17

Preliminary Technical Data ADN2530

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Min Max Unit

Supply Voltage—VCC to GND −0.3 +4.2 V
IMODP, IMODN to GND VCC − 1 .5 4.5 V
DATAP, DATAN to GND VCC − 1.8 VCC − 0.4 V
All Other Pins −0.3 VCC + 0.3 V
Junction Temperature 150 °C
Storage Temperature −65 +150 °C
Soldering Temperature

(Less than 10 s)

240 °C

PACKAGE THERMAL SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit Conditions/Comments

θ

θ

J-TOP

J-PAD

2.6 5.8 10.7 °C/W Thermal resistance from junction to top of package.

65 72.2 79.4 °C/W Thermal resistance from junction to bottom of exposed pad.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrB | Page 5 of 17

ADN2530 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

DATAN

DATAP

VCC

161514

13

BSET

VCC

IMODP

12
11
10

9

IBMON
IBIAS
GND

02461-016

1

MSET

CPA

ALS

GND

2
3
4

PIN 1
INDICATOR

ADN2530

TOP VIEW

5

678

VCC

IMODN

Figure 4. Pin Configuration

Note: There is an exposed pad on the bottom of the package that must be connected to the VCC or GND plane with filled vias.

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 MSET Input Modulation current control input
2 CPA Input Cross Point Adjust control input
3 ALS Input Automatic laser shutdown
4 GND Power Negative power supply
5 VCC Power Positive power supply
6 IMODN Output Modulation current negative output
7 IMODP Output Modulation current positive output
8 VCC Power Positive power supply
9 GND Power Negative power supply
10 IBIAS Output Bias current output
11 IBMON Output Bias current monitoring output
12 BSET Input Bias current control input
13 VCC Power Positive power supply
14 DATAP Input Data signal positive input
15 DATAN Input Data signal negative input
16 VCC Power Positive power supply
Exposed Pad Pad Power Connect to GND or VCC

Rev. PrB | Page 6 of 17