ANALOG DEVICES ADN2530 Service Manual

11.3 Gbps, Active Back-Termination,

VCCA

A

FEATURES

Up to 11.3 Gbps operation

−40°C to +100°C operation
Very low power: I
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)

3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor

APPLICATIONS

10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers

SUPPLY

= 65 mA

Differential VCSEL Driver

ADN2530

GENERAL DESCRIPTION

The ADN2530 laser diode driver is designed for direct modula­tion of packaged VCSELs with a differential resistance ranging
from 35 Ω to 140 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from −40°C to +100°C.

FUNCTIONAL BLOCK DIAGRAM

CP

VCC

50Ω 50Ω

GND

DATAP

DATAN

800Ω

200Ω

MSET GND BSET

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CROSS

POINT

ADJUST

LS

200Ω

ADN2530

100Ω

200Ω 10Ω

IMOD

VCC

IMODP

IMODN

IBMON

IBIAS

05457-001

VCC

800Ω

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADN2530

TABLE OF CONTENTS

Features.............................................................................................. 1

Automatic Laser Shutdown (ALS) ........................................... 11

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Package Thermal Specifications................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Input Stage................................................................................... 10

Bias Current ................................................................................10

REVISION HISTORY

Modulation Current................................................................... 11

Load Mistermination................................................................. 13

Crosspoint Adjust....................................................................... 13

Power Consumption .................................................................. 13

Applications Information.............................................................. 15

Typical Application Circuit....................................................... 15

Layout Guidelines....................................................................... 15

Design Example.......................................................................... 16

Headroom Calculations ........................................................ 16

BSET and MSET Pin Voltage Calculation .......................... 16

IBIAS Monitor Accuracy Calculations................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

8/06—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 3............................................................................ 5

Changes to Figure 24...................................................................... 10

Changes to Figure 30...................................................................... 11

Changes to Modulation Current Section .................................... 12

Changes to Typical Application Circuit Section......................... 15

10/05—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADN2530

SPECIFICATIONS

VCC = VCC
Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT (IBIAS)

Bias Current Range 2 25 mA
Bias Current While ALS Asserted 50 μA ALS = high
Compliance Voltage

0.55 VCC – 0.8 V IBIAS = 2 mA

MODULATION CURRENT (IMODP, IMODN)

Modulation Current Range 2.2 23 mA diff R

2.2 19 mA diff R
Modulation Current While ALS Asserted 250 μA diff ALS = high
Crosspoint Adjust (CPA) Range
Rise Time (20% to 80%)

26.4 34.7 ps CPA 35% to 65%
Fall Time (20% to 80%)

26.5 33.7 ps CPA 35% to 65%
Random Jitter
<0.5 ps rms CPA 35% to 65%
Deterministic Jitter

5.8 8.2 ps p-p 10.7 Gbps, CPA 35% to 65%
Deterministic Jitter

5.8 8.2 ps p-p 11.3 Gbps, CPA 35% to 65%
Differential |S22| −5 dB 5 GHz < f < 10 GHz, Z0 = 100 Ω differential

−13.6 dB f < 5 GHz, Z0 = 100 Ω differential
Compliance Voltage

DATA INPUTS (DATAP, DATAN)

Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled
Differential |S11| −15 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to IBIAS Gain 15 20 24 mA/V
BSET Input Resistance 800 1000 1200 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to IMOD Gain 14 19 23 mA/V
MSET Input Resistance 800 1000 1200 Ω

BIAS MONITOR (IBMON)

IBMON to IBIAS Ratio 50 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % IBIAS = 2 mA, R

−4.3 +4.3 % IBIAS = 4 mA, R

−3.5 +3.5 % IBIAS = 8 mA, R

−3.0 +3.0 % IBIAS = 14 mA, R

−2.5 +2.5 % IBIAS = 25 mA, R

AUTOMATIC LASER SHUTDOWN (ALS)

VIH 2.4 V
VIL 0.8 V
IIL −20 +20 μA
IIH 0 200 μA

to VCC

MIN

2, 3, 4

, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.

MAX

1

2

2, 3 , 4

2, 3, 4

0.55 VCC – 1.3 V IBIAS = 25 mA

= 35 Ω to 100 Ω differential

LOAD

= 140 Ω differential

LOAD

35 65 %
26 32.5 ps CPA disabled

26 32.5 ps CPA disabled

<0.5 ps rms CPA disabled

2, 4, 5

2, 4, 6

1

5.4 8.2 ps p-p 10.7 Gbps, CPA disabled

5.4 8.2 ps p-p 11.3 Gbps, CPA disabled

VCC − 0.7 VCC + 0.7 V

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

Rev. A | Page 3 of 20

ADN2530

Parameter Min Typ Max Unit Test Conditions/Comments

ALS Assert Time 2 μs

ALS Negate Time 10 μs

POWER SUPPLY

VCC 3.07 3.3 3.53 V

7

I

CC

8

I

SUPPLY

1

The voltage between the pin with the specified compliance voltage and GND.

2

Specified for TA = −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = −40°C to +100°C.

3

The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.

4

Measured using the high speed characterization circuit shown in Figure 3.

5

The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.

6

The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.

7

Only includes current in the ADN2530 VCC pins.

8

Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.

27 32 mA V
65 76 mA V

PACKAGE THERMAL SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

θ

65 72.2 79.4 °C/W Thermal resistance from junction to top of package.

J-TOP

θ

2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.

J-PAD

IC Junction Temperature 125 °C

ALS

ALS

NEGATE TIME

Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see

Figure 2

Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see

= V
= V

MSET

MSET

= 0 V
= 0 V

BSET

BSET

Figure 2

Z

= 50Ω

0

J2

GND GND GND

J3

GND GND

DC-BLOCK

DC-BLOCK

IBIAS

AND IMOD

90%

10%

ALS

ASSERT TIME

Figure 2. ALS Timing Diagram

VEEVEE

VBSET

GND

Z

= 50Ω Z0 = 50Ω

0

GND

VMSET

750Ω

TP1

BSET IBMON IBIAS GND

VCC

ADN2530

DATAP

DATAN

VCC

MSET CPA ALS GND

VEE

VCPA

VEE

VEE

GND
10Ω

TP2

VCC

IMODP

IMODN

VCC

VEE

J8 J5

GND GND GND

10nF

10nF

10μF

Figure 3. High Speed Characterization Circuit

GND

GNDGND

t

t

05457-002

GND

GND

BIAS TEE

GND

= 50ΩZ0 = 50ΩZ0 = 50Ω

Z

0

GND

GND

BIAS TEE

GND

BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR

VEE

DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A

ADAPTER

ADAPTER

ATTENUATOR

ATTENUATOR

50Ω

OSCILLOSCOPE

50Ω

GND

GND

05457-003

Rev. A | Page 4 of 20

ADN2530

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage—VCC to GND −0.3 V to +4.2 V
IMODP, IMODN to GND VCC − 1.5 V to +4.5 V
DATAP, DATAN to GND VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Soldering Temperature

(Less than 10 sec)

300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 5 of 20

ADN2530

E

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

DATAN

DATAP

VCC

161514

13

12

1

MSET

CPA

ALS

GND

NOTES:
THERE IS AN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST B
CONNECTED TO THE VCC OR GND PLANE.

2

3

4

PIN 1
INDICATOR

ADN2530

TOP VIEW

(Not to Scale)

5

678

VCC

IMODP

IMODN

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 MSET Input Modulation Current Control Input
2 CPA Input Crosspoint Adjust Control Input
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad Pad Power Connect to GND or VCC

BSET

11

IBMON

10

IBIAS

9

GND

VCC

05457-004

Rev. A | Page 6 of 20