Datasheet ADN2530 Datasheet (ANALOG DEVICES)

11.3 Gbps, Active Back-Termination,

VCCA

A

FEATURES

Up to 11.3 Gbps operation

−40°C to +100°C operation
Very low power: I
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)

3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor

APPLICATIONS

10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers

SUPPLY

= 65 mA

Differential VCSEL Driver

ADN2530

GENERAL DESCRIPTION

The ADN2530 laser diode driver is designed for direct modula­tion of packaged VCSELs with a differential resistance ranging
from 35 Ω to 140 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from −40°C to +100°C.

FUNCTIONAL BLOCK DIAGRAM

CP

VCC

50Ω 50Ω

GND

DATAP

DATAN

800Ω

200Ω

MSET GND BSET

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CROSS

POINT

ADJUST

LS

200Ω

ADN2530

100Ω

200Ω 10Ω

IMOD

VCC

IMODP

IMODN

IBMON

IBIAS

05457-001

VCC

800Ω

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADN2530

TABLE OF CONTENTS

Features.............................................................................................. 1

Automatic Laser Shutdown (ALS) ........................................... 11

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Package Thermal Specifications................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Input Stage................................................................................... 10

Bias Current ................................................................................10

REVISION HISTORY

Modulation Current................................................................... 11

Load Mistermination................................................................. 13

Crosspoint Adjust....................................................................... 13

Power Consumption .................................................................. 13

Applications Information.............................................................. 15

Typical Application Circuit....................................................... 15

Layout Guidelines....................................................................... 15

Design Example.......................................................................... 16

Headroom Calculations ........................................................ 16

BSET and MSET Pin Voltage Calculation .......................... 16

IBIAS Monitor Accuracy Calculations................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

8/06—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 3............................................................................ 5

Changes to Figure 24...................................................................... 10

Changes to Figure 30...................................................................... 11

Changes to Modulation Current Section .................................... 12

Changes to Typical Application Circuit Section......................... 15

10/05—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADN2530

SPECIFICATIONS

VCC = VCC
Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT (IBIAS)

Bias Current Range 2 25 mA
Bias Current While ALS Asserted 50 μA ALS = high
Compliance Voltage

0.55 VCC – 0.8 V IBIAS = 2 mA

MODULATION CURRENT (IMODP, IMODN)

Modulation Current Range 2.2 23 mA diff R

2.2 19 mA diff R
Modulation Current While ALS Asserted 250 μA diff ALS = high
Crosspoint Adjust (CPA) Range
Rise Time (20% to 80%)

26.4 34.7 ps CPA 35% to 65%
Fall Time (20% to 80%)

26.5 33.7 ps CPA 35% to 65%
Random Jitter
<0.5 ps rms CPA 35% to 65%
Deterministic Jitter

5.8 8.2 ps p-p 10.7 Gbps, CPA 35% to 65%
Deterministic Jitter

5.8 8.2 ps p-p 11.3 Gbps, CPA 35% to 65%
Differential |S22| −5 dB 5 GHz < f < 10 GHz, Z0 = 100 Ω differential

−13.6 dB f < 5 GHz, Z0 = 100 Ω differential
Compliance Voltage

DATA INPUTS (DATAP, DATAN)

Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled
Differential |S11| −15 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to IBIAS Gain 15 20 24 mA/V
BSET Input Resistance 800 1000 1200 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to IMOD Gain 14 19 23 mA/V
MSET Input Resistance 800 1000 1200 Ω

BIAS MONITOR (IBMON)

IBMON to IBIAS Ratio 50 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % IBIAS = 2 mA, R

−4.3 +4.3 % IBIAS = 4 mA, R

−3.5 +3.5 % IBIAS = 8 mA, R

−3.0 +3.0 % IBIAS = 14 mA, R

−2.5 +2.5 % IBIAS = 25 mA, R

AUTOMATIC LASER SHUTDOWN (ALS)

VIH 2.4 V
VIL 0.8 V
IIL −20 +20 μA
IIH 0 200 μA

to VCC

MIN

2, 3, 4

, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.

MAX

1

2

2, 3 , 4

2, 3, 4

0.55 VCC – 1.3 V IBIAS = 25 mA

= 35 Ω to 100 Ω differential

LOAD

= 140 Ω differential

LOAD

35 65 %
26 32.5 ps CPA disabled

26 32.5 ps CPA disabled

<0.5 ps rms CPA disabled

2, 4, 5

2, 4, 6

1

5.4 8.2 ps p-p 10.7 Gbps, CPA disabled

5.4 8.2 ps p-p 11.3 Gbps, CPA disabled

VCC − 0.7 VCC + 0.7 V

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

= 750 Ω

IBMON

Rev. A | Page 3 of 20

ADN2530

Parameter Min Typ Max Unit Test Conditions/Comments

ALS Assert Time 2 μs

ALS Negate Time 10 μs

POWER SUPPLY

VCC 3.07 3.3 3.53 V

7

I

CC

8

I

SUPPLY

1

The voltage between the pin with the specified compliance voltage and GND.

2

Specified for TA = −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = −40°C to +100°C.

3

The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.

4

Measured using the high speed characterization circuit shown in Figure 3.

5

The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.

6

The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.

7

Only includes current in the ADN2530 VCC pins.

8

Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.

27 32 mA V
65 76 mA V

PACKAGE THERMAL SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

θ

65 72.2 79.4 °C/W Thermal resistance from junction to top of package.

J-TOP

θ

2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.

J-PAD

IC Junction Temperature 125 °C

ALS

ALS

NEGATE TIME

Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see

Figure 2

Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see

= V
= V

MSET

MSET

= 0 V
= 0 V

BSET

BSET

Figure 2

Z

= 50Ω

0

J2

GND GND GND

J3

GND GND

DC-BLOCK

DC-BLOCK

IBIAS

AND IMOD

90%

10%

ALS

ASSERT TIME

Figure 2. ALS Timing Diagram

VEEVEE

VBSET

GND

Z

= 50Ω Z0 = 50Ω

0

GND

VMSET

750Ω

TP1

BSET IBMON IBIAS GND

VCC

ADN2530

DATAP

DATAN

VCC

MSET CPA ALS GND

VEE

VCPA

VEE

VEE

GND
10Ω

TP2

VCC

IMODP

IMODN

VCC

VEE

J8 J5

GND GND GND

10nF

10nF

10μF

Figure 3. High Speed Characterization Circuit

GND

GNDGND

t

t

05457-002

GND

GND

BIAS TEE

GND

= 50ΩZ0 = 50ΩZ0 = 50Ω

Z

0

GND

GND

BIAS TEE

GND

BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR

VEE

DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A

ADAPTER

ADAPTER

ATTENUATOR

ATTENUATOR

50Ω

OSCILLOSCOPE

50Ω

GND

GND

05457-003

Rev. A | Page 4 of 20

ADN2530

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage—VCC to GND −0.3 V to +4.2 V
IMODP, IMODN to GND VCC − 1.5 V to +4.5 V
DATAP, DATAN to GND VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Soldering Temperature

(Less than 10 sec)

300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 5 of 20

ADN2530

E

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

DATAN

DATAP

VCC

161514

13

12

1

MSET

CPA

ALS

GND

NOTES:
THERE IS AN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST B
CONNECTED TO THE VCC OR GND PLANE.

2

3

4

PIN 1
INDICATOR

ADN2530

TOP VIEW

(Not to Scale)

5

678

VCC

IMODP

IMODN

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 MSET Input Modulation Current Control Input
2 CPA Input Crosspoint Adjust Control Input
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad Pad Power Connect to GND or VCC

BSET

11

IBMON

10

IBIAS

9

GND

VCC

05457-004

Rev. A | Page 6 of 20

ADN2530

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.

30

25

20

15

RISE TIME (ps)

10

5

0

0

30

25

20

15

FALL TIME (ps)

10

5

0

0

DIFFERENTIAL MODULATION CURRENT (mA)

Figure 5. Rise Time vs. IMOD

DIFFERENTIAL MODULATION CURRENT (mA)

Figure 6. Fall Time vs. IMOD

10

9

8

7

6

5

4

3

DETERMINISTIC JITTER (ps)

2

1

05457-035

252015105

0

0

10.7Gbps

11.3Gbps

2015105

DIFFERENTIAL MODULATION CURRENT (mA)

05457-037

25

Figure 8. Deterministic Jitter vs. IMOD

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

RANDOM JITTER (ps rms)

0.2

0.1

05457-036

252015105

0

0

DIFFERENTIAL MODULATION CURRENT (mA)

JITTER BELOW EQUIPMENT

MEASUREMENT CAPABILITY

05457-048

252015105

Figure 9. Random Jitter vs. IMOD

–10

–15

–20

–25

DIFFERENTIAL |S11| (dB)

–30

–35

–40

0

–5

0

FREQUENCY (GHz)

05457-049

151413121110987654321

Figure 7. Differential |S11|

–10

–15

–20

–25

DIFFERENTIAL |S22| (dB)

–30

–35

–40

0

–5

0

FREQUENCY (GHz)

05457-050

151413121110987654321

Figure 10. Differential |S22|

Rev. A | Page 7 of 20

ADN2530

35

30

25

20

15

RISE TIME (ps)

10

5

0

–40

TEMPERATURE (°C)

05457-044

100806040200–20

Figure 11. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled)

35

30

25

20

15

FALL TIME (ps)

10

5

10

9

8

7

6

5

4

3

DETERMINISTIC JITTER (ps)

2

1

0

–40

10.7Gbps

11.3Gbps

TEMPERATURE (°C)

Figure 14. Deterministic Jitter vs. Temperature

(Worse-Case Conditions, CPA Disabled)

80

70

60

50

40

IMOD EYE CROSSPOINT (%)

30

VCC = [3.07, 3.3, 3.53]

05457-047

100806040200–20

0

–40

TEMPERATURE (°C)

05457-045

100806040200–20

Figure 12. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled)

1.0

0.8

0.6

0.4

RANDOM JITTER (ps rms)

0.2

0

–40

TEMPERATURE (°C)

05457-046

100806040200–20

Figure 13. Random Jitter vs. Temperature

(Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 2.2 mA])

20

1.00

CPA VOLTAGE (V)

05457-042

2.502.252.001.751.501.25

Figure 15. IMOD Eye Diagram Crosspoint vs. CPA Voltage and VCC

(IMOD = 10 mA)

80

70

60

50

40

IMOD EYE CROSSPOINT (%)

30

20

0.75

+85°C

+100°C

–40°C

+25°C

CPA VOLTAGE (V)

05457-043

2.502.252.001.751.501.251.00

Figure 16. IMOD Eye Diagram Crosspoint vs. CPA Voltage and Temperature

(IMOD = 10 mA)

Rev. A | Page 8 of 20

ADN2530

140

IBIAS = 25mA

120

100

IBIAS = 10mA

1 LEVEL 1 LEVEL

80

60

40

TOTAL SUPPLY CURRENT (mA)

20

0

25

20

15

10

OCCURANCE (%)

5

0

25

IBIAS = 2mA

0

DIFFERENTIAL MODULATION CURRENT (mA)

Figure 17. Total Supply Current vs. IMOD

26

RISE TIME (ps)

Figure 18. Worst-Case Rise Time Distribution

CROSSING

0 LEVEL 0 LEVEL

05457-038

252015105

05457-014

Figure 20. Electrical Eye Diagram

(IMOD = 10 mA, PRBS31 Pattern at 10.3125 Gbps)

05457-039

3130292827

05457-016

Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL

(PRBS31 Pattern at 10.3125 Gbps, 3 dB Optical Attenuator)

20

15

10

OCCURANCE (%)

5

0

26

FALL TIME (ps)

05457-040

3130292827

Figure 19. Worst-Case Fall Time Distribution

Rev. A | Page 9 of 20

ADN2530

P

THEORY OF OPERATION

As shown in Figure 1, the ADN2530 consists of an input
stage and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-termination circuitry for proper transmission line
matching and power consumption reduction. The ADN2530
can drive a load with differential resistance ranging from 35 Ω
to 140 Ω. The excellent back-termination in the ADN2530
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.

INPUT STAGE

The input stage of the ADN2530 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in

Figure 22.

VCC

50Ω 50Ω

DATA SIGNAL SOURCE

Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs

C

C

BIAS CURRENT

The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in

Figure 24.

VCC

ADN2530

800Ω

ADN2530

DATAP

DATAN

IBMON

IBIAS

IBMONBSET

IBIAS

05457-018

DATA

VCC

DATAN

Figure 22. Equivalent Circuit of the Input Stage

50Ω

50Ω

VCC

05457-017

The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2530 with single-ended data signal sources.

The ADN2530 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common­mode voltages of the data signal source and the input stage of
the driver (see

Figure 23). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF
capacitors.

200Ω

Figure 24. Voltage-to-Current Converter Used to Generate IBIAS

200Ω

GND

10Ω

5457-019

The BSET to IBIAS voltage-to-current conversion factor is
set at 20 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/20. By connecting a 750 Ω resistor between IBMON
and GND, the bias current can be monitored as a voltage across
the resistor. A low temperature coefficient precision resistor
must be used for the IBMON resistor (R
the value of R

due to tolerances or drift in its value over

IBMON

). Any error in

IBMON

temperature contributes to the overall error budget for the IBIAS
monitor voltage. If the IBMON voltage is being connected to an
ADC for A/D conversion, R

should be placed close to the

IBMON

ADC to minimize errors due to voltage drops on the ground
plane. See the

Design Example section for example calculations
of the accuracy of the IBIAS monitor as a percentage of the
nominal IBIAS value.

Rev. A | Page 10 of 20

ADN2530

V

V

The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in

Figure 25 to Figure 27.

VCC

BSET

800Ω

200Ω

Figure 25. Equivalent Circuit of the BSET Pin

IBIAS

VCC

100Ω

10Ω

Figure 26. Equivalent Circuit of the IBIAS Pin

VCC

VCC

VCC

2kΩ

05457-021

VCC

500Ω

05457-020

See the Headroom Calculations section for examples.

The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see

Tabl e 6 .

AUTOMATIC LASER SHUTDOWN (ALS)

The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in

Table 5.

ALS Logic State IBIAS and IMOD

High Disabled
Low Enabled
Floating Enabled

The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in

Tabl e 5 .

Figure 29.

CC

ALS

35kΩ

Figure 29. Equivalent Circuit of the ALS Pin

CC

100Ω

2kΩ

05457-024

100Ω

VCC

IBMON

05457-022

Figure 27. Equivalent Circuit of the IBMON Pin

The recommended configuration for BSET, IBIAS, and IBMON
is shown in

Figure 28. Recommended Configuration for BSET, IBIAS, and IBMON Pins

Figure 28.

VBSET

ADN2530

BSET

GND

TO LASER CATHODE

L

IBIAS

IBMON

R

IBMON

750Ω

IBIAS

05457-023

The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see

Tabl e 1 ). The
maximum compliance voltage is specified for only two bias
current levels (2 mA and 25 mA), but it can be calculated for
any bias current by

V

COMPLIANCE

(V) = VCC (V) − 0.75 − 22 × IBIAS (A)

MODULATION CURRENT

The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 30.

VCC

IMOD

IMODP

IMODN

5457-025

100Ω

FROM CPA STAG E

MSET

800Ω

200Ω

GND

ADN2530

Figure 30. Generation of Modulation Current on the ADN2530

This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.

Rev. A | Page 11 of 20

ADN2530

V

V

V

This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive back­termination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current IMOD, the range specified in

Tabl e 1 , flows in the
external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in
resistors in

Figure 32 are not real resistors. They represent the

Figure 31 and Figure 32. The two 50 Ω

active back-termination resistance.

CC

MSET

800Ω

200Ω

Figure 31. Equivalent Circuit of the MSET Pin

VCC VCC

50Ω

15Ω 15Ω

Figure 32. Equivalent Circuit of the IMODP and IMODN Pins

CC

05457-026

IMODPIMODN

50Ω

05457-027

The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in

Figure 33. See Tab l e 6 for recom­mended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
connected as shown in

Figure 33.

IBIAS

ADN2530

IMODP

VCC

L

L

= 50Ω Z0 = 50Ω

Z

0

C

45

40

35

MAX

TYP

DIFFERENTIAL LOAD RESISTANCE

05457-029

1401301201101009080706050403020

MSET VOLTAGE TO MODULATION

30

25

MIN

20

CURRENT RATIO (mA/V)

15

10

10

Figure 34. MSET Voltage to Modulation Current Ratio vs.

Differential Load Resistance

Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the

Applications Information section).

The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
23 mA modulation currents through the differential load, the
output stage of the ADN2530 (IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins
have a dc component equal to VCC and an ac component with
single-ended peak-to-peak amplitude of IMOD × 50 Ω. This
is the case when the load impedance (R

) is less than

TOSA

100 Ω differential because the transmission line characteristic
impedance sets the peak-to-peak amplitude. For the case where
R

is greater than 100 Ω, the single-ended, peak-to-peak

TOSA

amplitude is IMOD × R

÷ 2. For proper operation of the

TOSA

output stage, the voltages at the IMODP and IMODN pins must
be between the compliance voltage specifications for this pin
over supply, temperature, and modulation current range, as
shown in

Figure 35. See the Headroom Calculations section for

examples of headroom calculations.

IMODP,VIMODN

TOSA

05457-028

VCC + 0.7V

NORMAL OPERATION REGION

VCC

VMSET

MSET

GND

IMODN

= 50Ω Z0 = 50Ω

Z

0

C

L

VCCLVCC

Figure 33. Recommended Configuration for the

MSET, IMODP, and IMODN Pins

VCC – 0.7V

The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in

Figure 34.

Rev. A | Page 12 of 20

Figure 35. Allowable Range for the Voltage at IMODP and IMODN

05457-030

ADN2530

LOAD MISTERMINATION

Due to its excellent S22 performance, the ADN2530 can drive
differential loads that range from 35 Ω to 140 Ω. In practice,
many TOSAs have differential resistance not equal to 100 Ω. In
this case, with 100 Ω differential transmission lines connecting
the ADN2530 to the load, the load end of the transmission lines
are misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2530 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to
be achieved even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2530 must be made with 100 Ω differential (50 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.

POWER CONSUMPTION

The power dissipated by the ADN2530 is given by

V

⎛

VCCP

MSET

50

+×=

⎜
⎝

where:

VCC is the power supply voltage.

IBIAS is the bias current generated by the ADN2530.

is the voltage applied to the MSET pin.

V

MSET

I

is the sum of the current that flows into the VCC,

SUPPLY

IMODP, and IMODN pins of the ADN2530 when IBIAS =
IMOD = 0 expressed in amps (see

is the average voltage on the IBIAS pin.

V

IBIAS

⎞
⎟

IBIASSUPPLY

⎠

Table 1 ).

××+

IBIASVI

)2.1(

CROSSPOINT ADJUST

The crossing level in the output electrical eye diagram can be
adjusted between 35% and 65% using the crosspoint adjust (CPA)
control input. This can be used to compensate for asymmetry in
the VCSEL response and optimizes the optical eye mask margin.
The CPA input is a voltage control input, and a plot of eye cross­point vs. CPA control voltage is shown in
in the

Typical Performance Characteristics section. The equivalent
circuit for the CPA pin is shown in
crosspoint adjust function and set the eye crossing to 50%, the
CPA pin should be tied to VCC.

VCC

CPA

Figure 36. Equivalent Circuit for CPA Pin

Figure 15 and Figure 16

Figure 36. To disable the

100Ω

05457-031

Considering VBSET/IBIAS = 50 as the conversion factor from
V

to IBIAS, the dissipated power becomes

BSET

V

⎛

MSET

VCCP

⎜
⎝

+×= 2.1

⎞

VI

⎟
⎠

V

⎛

BSET

⎜

IBIASSUPPLY

5050

⎝

⎞

××+

⎟
⎠

To ensure long-term reliable operation, the junction tempera­ture of the ADN2530 must not exceed 125°C, as specified in
Tabl e 2 . For improved heat dissipation, the module’s case can be
used as a heat sink, as shown in

THERMAL COMPOUND

DIE

PACKAGE

PCB

COPPER PLANE

VIAS

Figure 37. Typical Optical Module Structure

MODULE CASE

T

TOP

T

J

T

PAD

Figure 37.

THERMO-COUPLE

05457-032

Rev. A | Page 13 of 20

ADN2530

(

)

T

A compact optical module is a complex thermal environment,
and calculations of device junction temperature using the
package θ

(junction-to-ambient thermal resistance) do not

JA

yield accurate results. The following equation, derived from the
model in

Figure 38, can be used to estimate the IC junction

temperature:

θ×+θ×+θ×θ×

TTP

PADJ

=

T

J

−

−

TOPTOPJ

PADJ

−

−

θ+θ

TOPJ

−

PADPADJ

TOPJ

−

P

Figure 38. Electrical Model for Thermal Calculations

TOP

θ

T

J

θ

J-PAD

T

PAD

T

J-TOP

PAD

T

TOP

05757-033

where:

T

is the temperature at top of package in degrees Celsius.

TOP

T

is the temperature at package exposed paddle in degrees

PAD

Celsius.

T

is the IC junction temperature in degrees Celsius.

J

P is the ADN2530 power dissipation in watts.

θ

is the thermal resistance from IC junction to package top.

J-TOP

θ

is the thermal resistance from IC junction to package

J-PAD

exposed pad.

T

and T

TOP

at points inside the module, as shown in

can be determined by measuring the temperature

PAD

Figure 37. The thermo­couples should be positioned to obtain an accurate measurement of
the package top and paddle temperatures. θ
given in

Tabl e 2 .

J-TOP

and θ

J-PAD

are

Rev. A | Page 14 of 20

ADN2530

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

Figure 39 shows the typical application circuit for the
ADN2530. The dc voltages applied to the BSET and MSET pins
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 Ω resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 Ω transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 Ω differential (50 Ω
single-ended) transmission lines.
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at

Table 6.

Component Value Description

R1, R2 110 Ω 0603 size resistor
R3, R4 300 Ω 0603 size resistor
C3, C4 100 nF

L6, L7 160 nH

L2, L3

L1, L4, L5, L8 10 μH

Tabl e 6 shows recommended

www.analog.com.

0402 size capacitor,
Phycomp 223878719849

0603 size inductor,
Murata LQW18ANR16

0603 size chip ferrite bead,
Murata BLM18HG601

0805 size inductor,
Murata LQM21FN100M70L

GND

BSET

DATAP

DATAN

MSET

+3.3V

VCC VCC

Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω

C1

= 50Ω

Z

0

C2

VCC

TP1

BSET IBMON IBIAS GND

VCC

DATAP

ADN2530

DATAN

VCC

MSET ALS GND

VCC

C7
20μF

GND

Figure 39. Typical ADN2530 Application Circuit

CPA

CPA

R5
750Ω

ALS

LAYOUT GUIDELINES

Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 μF tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530, consult the
Amkor Technology® “Application Notes for Surface Mount
Assembly of Amkor’s

VCC

L1

R1

L2

GND

Z0 = 50Ω Z0 = 50Ω

GND

VCC

C4

C3

L3

L4 R2

VCC

10nF

VCC

IMODP

IMODN

VCC

10nF

GND

GND

C5

VCC

VCC

C6

Figure 39. If proper decoupling cannot be

MicroLeadFrame® (MLF®) Packages.”

C8

100nF

V

CC

L8

R4

L7

TOSA

L6

L5 R3

VCC

05757-034

Rev. A | Page 15 of 20

ADN2530

DESIGN EXAMPLE

This design example covers:

• Headroom calculations for IBIAS, IMODP, and IMODN pins.

• Calculation of the typical voltage required at the BSET

and MSET pins to produce the desired bias and
modulation currents.

• Calculations of the IBIAS monitor accuracy over the IBIAS

current range.

This design example assumes that the impedance of the
TOSA is 60 Ω, the forward voltage of the VCSEL at low current

= 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.

is V

F

Headroom Calculations

To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in

Considering the typical application circuit shown in
the voltage at the IBIAS pin can be written as

V

IBIAS

where:

VCC is the supply voltage.

V

is the forward voltage across the laser at low current.

F

R

is the resistance of the TOSA.

TOSA

V

is the dc voltage drop across L5, L6, L7, and L8.

LA

For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.55 V, as specified by the minimum
IBIAS compliance specification in

Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that V

V

IBIAS

V

IBIAS

The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by

V

COMPLIANCE_MAX

For this example,

V

COMPLIANCE_MAX

V

IBIAS

To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD
ADN2530, the voltage at each modulation output pin should be
within the normal operation region shown in

Tabl e 1 .

Figure 39,

= VCC − VF − (IBIAS × R

TOSA

) − VLA

Tabl e 1 .

= 0 V, VF = 1.2 V, and IBIAS = 10 mA,

LA

= 3.3 − 1.2 − (0.01 × 60) = 1.5 V

= 1.5 V > 0.55 V, which satisfies the requirement

= VCC − 0.75 − 22 × IBIAS (A)

= VCC – 0.75 − 22 × 0.01 = 2.33 V

= 1.5 V < 2.33 V, which satisfies the requirement

× 50 Ω, as R

< 100 Ω. For proper operation of the

TOSA

Figure 35.

Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V
and IMOD = 10 mA, the minimum voltage at the modulation
output pins is equal to

VCC − (IMOD × 50)/2 = VCC − 0.25

VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement

The maximum voltage at the modulation output pins is equal to

VCC + (IMOD × 50)/2 = VCC + 0.25

VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement

Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.

BSET and MSET Pin Voltage Calculation

To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2530 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in
and the typical IBIAS/V

Table 1 . Assuming that IBIAS = 10 mA

ratio of 20 mA/V, the BSET voltage

BSET

is given by

BSET

IBIAS

mA/V20

V

10
20

V5.0

===

(mA)

The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in

Table 1 .

The voltage required at the MSET pin to produce the desired
modulation current can be calculated using

IMOD

=

V

MSET

K is the MSET voltage to IMOD ratio.

where

K

The value of K depends on the actual resistance of the TOSA
and can be obtained from

Figure 34. For a TOSA resistance of
60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD =
10 mA and using the preceding equation, the MSET voltage is
given by

V

MSET

IMOD

mA/V24

10
24

V42.0

===

(mA)

The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These can
be obtained from the minimum and maximum curves in

Figure 34.

Rev. A | Page 16 of 20

ADN2530

IBIAS Monitor Accuracy Calculations

6

5

4

3

Referring to
±4.3% for the minimum IBIAS of 4 mA and ±3.0% for the
maximum IBIAS value of 14 mA.

The accuracy of the IBMON output current as a percentage of
the nominal IBIAS is given by

Figure 40, the IBMON output current accuracy is

100

AccuracyIBMON

MIN

mA4_ ±=×=

100

mA8

3.4
%15.2

2

1

ACCURACY OF IBIAS TO IBMON RATIO (%)

0

0

Figure 40. Accuracy of IBIAS to IBMON Ratio

IBIAS (mA)

05457-041

252015105

This example assumes that the nominal value of IBIAS is 8 mA
and that the IBIAS range for all operating conditions is 4 mA to
14 mA. The accuracy of the IBIAS to IBMON ratio is given in
the

Table 1 and is plotted in Figure 40.

for the minimum IBIAS value, and by

100

0.3

AccuracyIBMON

MAX

mA14_ ±=×=

100

mA8

%25.5

for the maximum IBIAS value. This gives a worse-case accuracy
for the IBMON output current of ±5.25% of the nominal IBIAS
value over all operating conditions. The IBMON output current
accuracy numbers can be combined with the accuracy numbers
for the 750 Ω IBMON resistor (R

) and any other error

IBMON

sources to calculate an overall accuracy for the IBMON voltage.

Rev. A | Page 17 of 20

ADN2530

R

R

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

*

COMPLIANT
EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

13

12

(BOTTOM VIEW)

9

8

Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions shown in millimeters

EXPOSED

PAD

0.30

16

1

4

5

N

P

I

D

N

I

*

1.65

1.50 SQ

1.35

0.25 MIN

1

O

C

I

A

T

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADN2530YCPZ-WP
ADN2530YCPZ-R2
ADN2530YCPZ-REEL7

1

Z = Pb-free part.

1

1

−40°C to +100°C 16-Lead LFCSP_VQ, 50-Piece Waffle Pack CP-16-3 F08

−40°C to +100°C 16-Lead LFCSP_VQ, 250-Piece Reel CP-16-3 F08

1

−40°C to +100°C 16-Lead LFCSP_VQ, 1500-Piece Reel CP-16-3 F08

Rev. A | Page 18 of 20

ADN2530

NOTES

Rev. A | Page 19 of 20

ADN2530

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05457–0–8/06(A)

Rev. A | Page 20 of 20