ANALOG DEVICES ADN2526 Service Manual

11.3 Gbps Active Back-Termination,

VCCA

FEATURES

3.3 V operation
Up to 11.3 Gbps operation
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p diff
Automatic laser shutdown (ALS)
Cross point adjustment (CPA)
XFP-compliant bias current monitor
SFP+ MSA compliant
Optical evaluation board available
Compact 3 mm × 3 mm LFCSP

APPLICATIONS

SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules

FUNCTIONAL BLOCK DIAGRAM

CPA

VCC

Differential Laser Diode Driver

ADN2526

GENERAL DESCRIPTION

The ADN2526 laser diode driver is designed for direct modula­tion of packaged laser diodes that have a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination in the
ADN2526 absorbs signal reflections from the TOSA end of the
output transmission lines, enabling excellent optical eye quality to
be achieved even when the TOSA end of the output transmission
lines is significantly misterminated. ADN2526 is an SFP+ MSA­compliant device, and its small package and enhanced ESD
protection provide the optimum solution for compact modules
where laser diodes are packaged in low pin-count optical
subassemblies.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various
average optical power and extinction ratio control schemes,
including closed-loop or look-up table control. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with a
LVT T L log i c s ource.

The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.

LS

VCC

ADN2526

50Ω

50Ω

GND

DATAP

DATAN

800Ω

MSET VEE BSET

200Ω

CROSS

POINT

ADJUST

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

50Ω

800Ω

200Ω

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

IMOD

VCC

200Ω 2Ω

IMODP

IMODN

IBMON

IBIAS

07511-001

ADN2526

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Thermal Specifications ................................................................ 4

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 10

Input Stage ................................................................................... 10

Bias Current ................................................................................ 10

Automatic Laser Shutdown (ALS) ........................................... 11

Modulation Current ................................................................... 11

Load Mistermination ................................................................. 12

Crosspoint Adjustment .............................................................. 13

Power Sequence .......................................................................... 13

Power Consumption .................................................................. 13

Applications Information .............................................................. 14

Typical Application Circuit ....................................................... 14

Layout Guidelines....................................................................... 14

Design Example .......................................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

8/09—Rev. 0 to Rev. A

Changes to θ

Changes to Figure 5 and Figure 6 ................................................... 8

1/09—Revision 0: Initial Version

Maximum Value (Table 2) ................................. 4

J-PAD

Rev. A | Page 2 of 16

ADN2526

SPECIFICATIONS

VCC = VCC
T

= 25°C, IMODD1 = 40 mA, unless otherwise noted.

A

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT (IBIAS)

Bias Current Range 10 100 mA
Bias Current While ALS Asserted 300 μA ALS = high
Compliance Voltage2 0.6 VCC V IBIAS = 100 mA

0.6 VCC V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)

Modulation Current Range 10 80 mA diff R
Modulation Current While ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Random Jitter
Deterministic Jitter
Pulse Width Distortion
Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential

−14 dB f < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage2 VCC − 1.1 VCC + 1.1 V

DATA INPUTS (DATAP, DATAN)

Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.15 1.6 V p-p diff Differential, ac-coupled
Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 100 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to IBIAS Gain 90 mA/V
BSET Input Resistance 1000 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to IMOD Gain 50 78 100 mA/V See Figure 29
MSET Input Resistance 1000 Ω

BIAS MONITOR (IBMON)

IBMON to IBIAS Ratio 10 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, R

−4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, R

−2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, R

−2 +2 % 70 mA ≤ IBIAS < 100 mA, R
AUTOMATIC LASER SHUTDOWN (ALS)

VIH 2.0 V
VIL 0.8 V
IIL −30 +30 μA
IIH 0 200 μA
ALS Assert Time 2 μs

ALS Negate Time 10 μs

to VCC

MIN

3, 4

0.4 0.9 ps rms

, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at

MAX

= 5 Ω to 50 Ω differential

LOAD

3, 4

24 32.5 ps

3, 4

24 32.5 ps

3, 5

7.2 12 ps p-p Includes pulse width distortion

3, 4

2 5 ps PWD = (|T

HIGH

Rising edge of ALS to falling edge of IBIAS and
IMOD below 10% of nominal, see Figure 2

Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal, see Figure 2

– T

LOW

|)/2

IBMON

IBMON

IBMON

IBMON

= 1 kΩ
= 1 kΩ
= 1 kΩ

= 1 kΩ

Rev. A | Page 3 of 16

ADN2526

A

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

VCC 3.0 3.3 3.6 V

6

I

46 55 mA V

CC

7

I

74 95 mA V

SUPPLY

CPA 1.88 V In NC mode (refer to Table 4)
Cross Point 50 % From an optical eye in NC mode

1

IMOD is the total modulation current sink capability for a differential driver. IMOD = I

2

Refers to the voltage between the pin for which the compliance voltage is specified and VEE.

3

The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps.

4

Measured using the high speed characterization circuit shown in Figure 3.

5

The pattern used is K28.5 (00111110101100000101) at a 11.3 Gbps rate.

6

Only includes current in the VCC pins.

7

Without laser diode loaded.

MODP

+ I

, the dynamic current sank by the IMODP and IMODN pins.

MODN

THERMAL SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

θ

2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad

J-PAD

θ

65 72.2 79.4 °C/W Thermal resistance from junction to top of package

J-TOP

IC Junction Temperature 125 °C

ALS

LS

NEGATE TI ME

BSET

BSET

= V
= V

MSET

MSET

= 0 V
= 0 V; I

= ICC + IMODP + IMODN

SUPPLY

t

IBIAS

AND IMO D

90%

10%

ALS

ASSERT TIME

t

7511-002

Figure 2. ALS Timing Diagram

Rev. A | Page 4 of 16

ADN2526

VEEV

V

GND

GND

GND

10nF

10nF

Z

GND

Z

GND

0

0

= 50Ω

Z

0

J2

GND

Z

= 50Ω

0

J3

GND

EE

VBSET

BSET IBMON IBIAS VEE

= 50Ω Z0 = 25Ω Z0 = 50Ω

= 50Ω

MSET CPA ALS

VMSET

TP1

VCC

DATAP

DATAN

VCC

VEE

VCPA

1kΩ

TP2

ADN2526

J8 J5

VEE

EE

GND

10Ω

10nF

VCC

IMODP

Z

= 25Ω Z0 = 50Ω

VCC

VEE

VEE

0

10nF

22µF

IMODN

GND GND GND

GND

GND

GND

GND

GNDGND

GND

35Ω

70Ω

35Ω

VEE

GND

GND

BIAS TEE: PICOSECOND P ULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FE MALE-TO -FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE- 7046 2.92mm 20dB ATT ENUATOR

BIAS
TEE

BIAS
TEE

GND

GND

ADAPTER

ADAPTER

ATTENUATOR

ATTENUATOR

GND

50Ω

OSCILLOSCOPE

50Ω

GND

7511-003

Figure 3. High Speed Characterization Circuit

Rev. A | Page 5 of 16