11.3 Gbps Active Back-Termination,
VCCA
FEATURES
3.3 V operation
Up to 11.3 Gbps operation
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p diff
Automatic laser shutdown (ALS)
Cross point adjustment (CPA)
XFP-compliant bias current monitor
SFP+ MSA compliant
Optical evaluation board available
Compact 3 mm × 3 mm LFCSP
APPLICATIONS
SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules
FUNCTIONAL BLOCK DIAGRAM
CPA
VCC
Differential Laser Diode Driver
ADN2526
GENERAL DESCRIPTION
The ADN2526 laser diode driver is designed for direct modulation of packaged laser diodes that have a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination in the
ADN2526 absorbs signal reflections from the TOSA end of the
output transmission lines, enabling excellent optical eye quality to
be achieved even when the TOSA end of the output transmission
lines is significantly misterminated. ADN2526 is an SFP+ MSAcompliant device, and its small package and enhanced ESD
protection provide the optimum solution for compact modules
where laser diodes are packaged in low pin-count optical
subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various
average optical power and extinction ratio control schemes,
including closed-loop or look-up table control. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with a
LVT T L log i c s ource.
The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.
LS
VCC
ADN2526
50Ω
50Ω
GND
DATAP
DATAN
800Ω
MSET VEE BSET
200Ω
CROSS
POINT
ADJUST
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
50Ω
800Ω
200Ω
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
IMOD
VCC
200Ω 2Ω
IMODP
IMODN
IBMON
IBIAS
07511-001
ADN2526
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Input Stage ................................................................................... 10
Bias Current ................................................................................ 10
Automatic Laser Shutdown (ALS) ........................................... 11
Modulation Current ................................................................... 11
Load Mistermination ................................................................. 12
Crosspoint Adjustment .............................................................. 13
Power Sequence .......................................................................... 13
Power Consumption .................................................................. 13
Applications Information .............................................................. 14
Typical Application Circuit ....................................................... 14
Layout Guidelines....................................................................... 14
Design Example .......................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Changes to θ
Changes to Figure 5 and Figure 6 ................................................... 8
1/09—Revision 0: Initial Version
Maximum Value (Table 2) ................................. 4
J-PAD
Rev. A | Page 2 of 16
ADN2526
SPECIFICATIONS
VCC = VCC
T
= 25°C, IMODD1 = 40 mA, unless otherwise noted.
A
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range 10 100 mA
Bias Current While ALS Asserted 300 μA ALS = high
Compliance Voltage2 0.6 VCC V IBIAS = 100 mA
0.6 VCC V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range 10 80 mA diff R
Modulation Current While ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Random Jitter
Deterministic Jitter
Pulse Width Distortion
Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential
−14 dB f < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage2 VCC − 1.1 VCC + 1.1 V
DATA INPUTS (DATAP, DATAN)
Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.15 1.6 V p-p diff Differential, ac-coupled
Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 100 Ω Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain 90 mA/V
BSET Input Resistance 1000 Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain 50 78 100 mA/V See Figure 29
MSET Input Resistance 1000 Ω
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio 10 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, R
−4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, R
−2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, R
−2 +2 % 70 mA ≤ IBIAS < 100 mA, R
AUTOMATIC LASER SHUTDOWN (ALS)
VIH 2.0 V
VIL 0.8 V
IIL −30 +30 μA
IIH 0 200 μA
ALS Assert Time 2 μs
ALS Negate Time 10 μs
to VCC
MIN
3, 4
0.4 0.9 ps rms
, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at
MAX
= 5 Ω to 50 Ω differential
LOAD
3, 4
24 32.5 ps
3, 4
24 32.5 ps
3, 5
7.2 12 ps p-p Includes pulse width distortion
3, 4
2 5 ps PWD = (|T
HIGH
Rising edge of ALS to falling edge of IBIAS and
IMOD below 10% of nominal, see Figure 2
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal, see Figure 2
– T
LOW
|)/2
IBMON
IBMON
IBMON
IBMON
= 1 kΩ
= 1 kΩ
= 1 kΩ
= 1 kΩ
Rev. A | Page 3 of 16
ADN2526
A
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
VCC 3.0 3.3 3.6 V
6
I
46 55 mA V
CC
7
I
74 95 mA V
SUPPLY
CPA 1.88 V In NC mode (refer to Table 4)
Cross Point 50 % From an optical eye in NC mode
1
IMOD is the total modulation current sink capability for a differential driver. IMOD = I
2
Refers to the voltage between the pin for which the compliance voltage is specified and VEE.
3
The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps.
4
Measured using the high speed characterization circuit shown in Figure 3.
5
The pattern used is K28.5 (00111110101100000101) at a 11.3 Gbps rate.
6
Only includes current in the VCC pins.
7
Without laser diode loaded.
MODP
+ I
, the dynamic current sank by the IMODP and IMODN pins.
MODN
THERMAL SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Conditions/Comments
θ
2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad
J-PAD
θ
65 72.2 79.4 °C/W Thermal resistance from junction to top of package
J-TOP
IC Junction Temperature 125 °C
ALS
LS
NEGATE TI ME
BSET
BSET
= V
= V
MSET
MSET
= 0 V
= 0 V; I
= ICC + IMODP + IMODN
SUPPLY
t
IBIAS
AND IMO D
90%
10%
ALS
ASSERT TIME
t
7511-002
Figure 2. ALS Timing Diagram
Rev. A | Page 4 of 16
ADN2526
VEEV
V
GND
GND
GND
10nF
10nF
Z
GND
Z
GND
0
0
= 50Ω
Z
0
J2
GND
Z
= 50Ω
0
J3
GND
EE
VBSET
BSET IBMON IBIAS VEE
= 50Ω Z0 = 25Ω Z0 = 50Ω
= 50Ω
MSET CPA ALS
VMSET
TP1
VCC
DATAP
DATAN
VCC
VEE
VCPA
1kΩ
TP2
ADN2526
J8 J5
VEE
EE
GND
10Ω
10nF
VCC
IMODP
Z
= 25Ω Z0 = 50Ω
VCC
VEE
VEE
0
10nF
22µF
IMODN
GND GND GND
GND
GND
GND
GND
GNDGND
GND
35Ω
70Ω
35Ω
VEE
GND
GND
BIAS TEE: PICOSECOND P ULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FE MALE-TO -FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE- 7046 2.92mm 20dB ATT ENUATOR
BIAS
TEE
BIAS
TEE
GND
GND
ADAPTER
ADAPTER
ATTENUATOR
ATTENUATOR
GND
50Ω
OSCILLOSCOPE
50Ω
GND
7511-003
Figure 3. High Speed Characterization Circuit
Rev. A | Page 5 of 16
ADN2526
ABSOLUTE MAXIMUM RATINGS
VEE connected to supply ground.
Table 3.
Parameter Rating
Supply Voltage, VCC to VEE −0.3 V to +4.2 V
IMODP, IMODN to VEE 1.1 V to 4.75 V
DATAP, DATAN to VEE VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
HBM ESD on IMODP, IMODN 200 V
HBM ESD on All Other Pins 1 kV
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Soldering Temperature
(Less Than 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 16
ADN2526
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DATAN
VCC
DATAP
VCC
14
13
15
16
PIN 1
INDICATO R
1MSET
2CPA
ADN2526
3AL S
TOP VIEW
(Not to Scale)
4VEE
5
6
DN
VCC
NOTES
1. THE EXPOSED PAD ON THE BOTTO M OF THE PACKAGE
MUST BE CONNECT ED TO VCC OR T HE GND PLANE.
IMO
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic I/O1 Description
1 MSET AI Modulation Current Control Input.
2 CPA AI Adjustable Cross Point. Defaults to not connected (NC) mode (floating).
3 ALS DI Automatic Laser Shutdown.
4 VEE P Negative Power Supply. Normally connected to system ground.
5 VCC P Positive Power Supply.
6 IMODN AI Modulation Current Sink, Negative.
7 IMODP AI Modulation Current Sink, Positive.
8 VCC P Positive Power Supply.
9 VEE P Negative Power Supply. Normally connected to system ground.
10 IBIAS AI Bias Current Sink.
11 IBMON AO Bias Current Monitoring Output.
12 BSET AI Bias Current Control Input.
13 VCC P Positive Power Supply.
14 DATAP AI Data Signal Positive Input.
15 DATAN AI Data Signal Negative Input.
16 VCC P Positive Power Supply.
17 (EPAD) Exposed Pad (EPAD) P The exposed pad on the bottom of the package must be connected to VCC or the GND plane.
1
AI = analog input, DI = digital input, P = power, AO = analog output.
12 BSET
11 IBMON
10 IBIAS
9VEE
8
7
VCC
IMODP
07511-004
Rev. A | Page 7 of 16
ADN2526
V
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
27.0
26.5
26.0
25.5
25.0
24.5
RISE T IME (p s)
24.0
23.5
23.0
0 2040608010
IMOD (mA)
Figure 5. Rise Time vs. IMOD
0
07511-005
9
8
7
6
5
4
JITTER (ps)
3
2
1
0
0 2040608010
IMOD (mA)
Figure 8. Deterministic Jitter vs. IMOD
0
07511-008
27.0
26.5
26.0
25.5
25.0
24.5
FALL TIME (ps)
24.0
23.5
23.0
0 2040608010
IMOD (mA)
Figure 6. Fall Time vs. IMOD
0.7
0.6
0.5
0.4
0.3
JITTE R (ps)
0.2
0.1
0
07511-006
0.35
0.30
0.25
(A)
0.20
CC
0.15
TOTAL I
0.10
0.05
0
0 102030405060708090100
IBIAS = 100
IBIAS = 50
IBIAS = 10
IMOD (mA)
Figure 9. Total Supply Current vs. IMOD
0
–5
–10
–15
–20
–25
–30
DIFFERENTIAL |S11| ( dB)
–35
07511-009
0
0 2040608010
IMOD (mA)
0
07511-007
Figure 7. Random Jitter vs. IMOD
–40
FREQUENCY (G Hz)
Figure 10. Differential |S11|
1501234567891011121314
07511-036
Rev. A | Page 8 of 16
ADN2526
0
–5
–10
–15
–20
–25
–30
DIFFERENTIAL |S22| (dB)
–35
07511-014
–40
FREQUENCY (G Hz)
Figure 11. Differential |S22|
1501234567891011121314
07511-035
Figure 14. Electrical Eye Diagram
(11.3 Gbps, PRBS31, IMOD = 80 mA)
16
14
12
10
8
6
OCCURRENCE (%)
4
2
0
RISE TIM E (ps)
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, T
16
14
12
10
8
6
OCCURRENCE (%)
4
2
0
FALL TIME (ps)
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, T
= 85°C)
A
= 85°C)
A
07511-015
3023 24 25 26 27 28 29
07511-012
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for Reference)
07511-016
3023 24 25 26 27 28 29
07511-013
Figure 16. Filtered 10 Gb Ethernet Optical Eye
Rev. A | Page 9 of 16
ADN2526
V
VCC
THEORY OF OPERATION
As shown in Figure 1, the ADN2526 consists of an input stage
and two voltage-controlled current sources for bias and modulation. The bias current, which is available at the IBIAS pin, is
controlled by the voltage applied at the BSET pin and can be
monitored at the IBMON pin. The differential modulation
current, which is available at the IMODP and IMODN pins, is
controlled by the voltage applied to the MSET pin. The output
stage implements the active back-match circuitry for proper
transmission line matching and power consumption reduction.
The ADN2526 can drive a load having differential resistance
ranging from 5 Ω to 50 Ω. The excellent back-termination in
the ADN2526 absorbs the signal reflections from the TOSA
end, enabling excellent optical eye quality, even though the
TOSA is significantly misterminated.
INPUT STAGE
The input stage of the ADN2526 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
CC
50Ω 50Ω
DATA SIGNAL S OURCE
Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs
C
C
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 19.
VCC
ADN2526
800Ω
RR
ADN2526
DATAP
DATAN
I
BMON
I
BIAS
IBMONBSET
IBIAS
07511-018
DATAP
DATAN
Figure 17. Equivalent Circuit of the Input Stage
50Ω
50Ω
VCC
07511-017
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which can otherwise lead to degradation in
the output eye diagram. It is not recommended to drive the
ADN2526 with single-ended data signal sources.
The ADN2526 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the commonmode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance much less than 50 Ω over the required
frequency range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
In SFP+ MSA applications, the DATAP and DATAN pins need
to be connected to the SFP+ connector directly. This connection
requires enhanced ESD protection to support the SFP+ module
hot plug-in application.
200Ω
GND
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
200Ω
2Ω
07511-019
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and VEE, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient
precision resistor must be used for the IBMON resistor (R
Any error in the value of R
that is due to tolerances or to drift
IBMON
IBMON
).
in its value over temperature contributes to the overall error
budget for the IBIAS monitor voltage. If the IBMON voltage is
connected to an ADC for analog-to-digital conversion, R
IBMON
should be placed close to the ADC to minimize errors due to
voltage drops on the ground plane.
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
VCC
BSET
Figure 20. Equivalent Circuit of the BSET Pin
800Ω
200Ω
07511-020
Rev. A | Page 10 of 16
ADN2526
V
V
V
VCCALSV
VCC
IBIAS
CC
2kΩ
100Ω
2Ω
07511-021
Figure 21. Equivalent Circuit of the IBIAS Pin
CC
VCC
CC
IBMON
500Ω
100Ω
07511-022
Figure 22. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
TO LASER CATHODE
IBIAS
L
IBIAS
ADN2526
IBMON IBMON
GND
R
1kΩ
07511-023
V
BSET
BSET
Figure 23. Recommended Configuration for the BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Ta b le 1 ). The
maximum compliance voltage is specified for only two bias
current levels (10 mA and 100 mA), but it can be calculated for
any bias current by
V
COMPLIANCE_MAX
(V) = VCC (V) − 0.75 − 4.4 × IBIAS (1)
See the Applications Information section for examples of
headroom calculations.
The function of the inductor, L, is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Tabl e 7.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Tab l e 5 .
Table 5. ALS Functions
ALS Logic State IBIAS and IMOD
High Disabled
Low Enabled
Floating Enabled
The ALS pin is compatible with 3.3 V CMOS and LVTTL logic
levels. Its equivalent circuit is shown in Figure 24.
CC
100Ω
40kΩ
2kΩ
07511-024
Figure 24. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor, as shown in
Figure 25.
VCC
IMOD
IMODP
IMODN
07511-025
50Ω
gm × V
FROM INPUT STAGE
MSET
800Ω
200Ω
GND
V
O
O
ADN2526
Figure 25. Generation of Modulation Current on the ADN2526
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and amplified by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination.
A small portion of the modulation current flows in the virtual
50 Ω active back-termination resistor. All of the preset IMOD
modulation current, the range specified in Tabl e 1, flows into
the external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 26 and Figure 27. The two 25 Ω
resistors in Figure 27 are not actual resistors. They represent the
active back-termination resistance.
Rev. A | Page 11 of 16
ADN2526
V
V
VCCVCC
V
V
V
V
MSET
CC
800Ω
200Ω
CC
07511-026
Figure 26. Equivalent Circuit of the MSET Pin
IMODPIMODN
25Ω
3.3Ω 3. 3Ω
25Ω
07511-027
Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Ta b l e 7 for the
recommended components.
MSET
ADN2526
MSET
IBIAS
IMODP
IMODN
VEE
VCC
LCL
Z0 = 25Ω Z0 = 25Ω
Z
= 25Ω Z0 = 25Ω
0
C
L
L
TOSA
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2526 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for these pins over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
IMODP, IMODN
CC + 1.1V
NORMAL OPERATION REGION
VCC
CC – 1.1V
VCC
VCC
7511-028
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
220
210
200
190
180
170
160
150
140
(mA/V)
130
120
MSET
/
110
100
MOD
I
90
80
70
60
50
40
0 102030405060
DIFFERENTIAL LOAD RESISTANCE (Ω)
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
MAXIMUM
TYPICAL
MINIMUM
07511-029
Rev. A | Page 12 of 16
07511-030
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2526 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case, with
50 Ω differential transmission lines connecting the ADN2526 to
the load, the load end of the transmission lines are misterminated.
This mistermination leads to signal reflections back to the driver.
The excellent back-termination in the ADN2526 absorbs these
reflections, preventing their reflection back to the load. This
enables excellent optical eye quality to be achieved, even when
the load end of the transmission lines is significantly misterminated. The connection between the load and the ADN2526 must
be made with 50 Ω differential (25 Ω single-ended) transmission
lines so that the driver end of the transmission lines is properly
terminated.
ADN2526
(
)
CROSSPOINT ADJUSTMENT
The optical eye cross point is adjustable between 35% and 65%
using the cross point adjust (CPA) control input. The equivalent
circuit for the CPA pin is shown in Figure 31. In a default CPA
setting, leave CPA unconnected (maintain pin-to-pin compatibility with the ADN2525). The internal bias circuit presents about
1.9 V at the CPA pin and the eye cross point is set to 50%. To set
the cross point at various points, apply an external voltage to the
CPA pin.
junction-to-ambient thermal resistance (θ
accurate results.
THERMAL CO MPOUND
DIE
PACKAGE
PCB
MODULE CASE
T
TOP
T
J
T
PAD
) do not yield
JA
THERMOCOUPLE
7kΩ 7kΩ
7kΩ
VCC
CPA
Figure 31. Equivalent Circuit for CPA Pin
07511-031
POWER SEQUENCE
To ensure reliable operation, the recommended power-up
sequence is: the supply rail to ADN2526 first, then the BSET
pin, followed by the MSET pin, and, finally, the CPA pin.
To turn off the ADN2526, the operation is reversed: shut down
CPA first, then MSET, followed by BSET, and, last, the supply rail.
POWER CONSUMPTION
The power dissipated by the ADN2526 is given by
V
⎛
VCCP
MSET
13.5
+×=
⎜
⎝
where:
VCC is the power supply voltage.
V
is the voltage applied to the MSET pin.
MSET
I
is the sum of the currents that flow into VCC, IMODP,
SUPPLY
and IMODN, which are sank by the ADN2526 when V
V
= 0 V, expressed in amps (see Ta b le 1 ).
MSET
V
is the average voltage presented on the IBIAS pin.
IBIAS
IBIAS is the bias current sank by the ADN2526.
Considering V
from V
BSET
VCCP ×+
/IBIAS = 10 mV/mA as the conversion factor
BSET
to IBIAS, the dissipated power becomes
V
⎛
MSET
⎜
⎝
+×=
To ensure long-term reliable operation, the junction temperature of the ADN2526 must not exceed 125°C, as specified in
Tabl e 2. For improved heat dissipation, the SFP+ module case
can work as a heat sink, as shown in Figure 32. A compact
optical module is a complex thermal environment, and
calculations of device junction temperature using the package
I
SUPPLY
⎞
⎟
⎠
⎞
⎟
⎠
IBIASVI
×+
IBIASSUPPLY
V
BSET
105.13
=
BSET
V
IBIAS
COPPER PLANE
VIAS
Figure 32. Typical Optical Module Structure
07511-032
The parameters in Tab l e 6 can be used to estimate the IC
junction temperature.
Table 6. Definitions
Parameter Description Unit
T
Temperature at the top of the package °C
TOP
T
Temperature at the package exposed paddle °C
PAD
TJ IC junction temperature °C
P Power dissipation W
θ
J-TOP
Thermal resistance from the IC junction to
°C/W
the package top
θ
J-PAD
Thermal resistance from the IC junction to
°C/W
the package exposed paddle
T
TOP
and T
can be determined by measuring the temperature
PAD
at points inside the module, as shown in Figure 32. The thermocouples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 33, the junction temperature can be calculated by
TTP
×+×+××
θθθθ
PADJ
T
=
J
−
−
PADJ
−
−
TOPTOPJ
+
θθ
TOPJ
−
PADPADJ
TOPJ
−
where:
θ
J-TOP
and θ
are given in Ta bl e 2.
J-PAD
P is the power dissipated by the ADN2526.
T
TOP
θ
J-TOP
P
Figure 33. Electrical Model for Thermal Calculations
θ
T
J-PAD
PAD
T
TOP
07511-033
Rev. A | Page 13 of 16
ADN2526
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 34 shows the typical application circuit for the ADN2526.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on or turn off the bias and modulation currents, depending on
the logic level applied to the pin. The data signal source must be
connected to the DATAP and DATAN pins of the ADN2526
using 50 Ω transmission lines. The modulation current outputs,
IMODP and IMODN, must be connected to the load (TOSA)
using 50 Ω differential (25 Ω single-ended) transmission lines.
It is recommended that the components shown in Ta bl e 7 be
used between the ADN2526 and the TOSA for an example ac
coupling circuit. For up-to-date component recommendations,
contact your local Analog Devices, Inc., sales representative.
Working with a TOSA laser sample, the circuit in Figure 34
delivers optical performance shown in Figure 15 and Figure 16.
For additional applications information and optical eye performance of other laser samples, contact your local Analog Devices
sales representative.
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2526 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Well controlled transmission line
impedance must be used for the high speed signal paths. The
length of the transmission lines must be kept to a minimum to
reduce losses and pattern-dependent jitter. The PCB layout
must be symmetrical, on both the DATAP and DATAN inputs
and the IMODP and IMODN outputs, to ensure a balance
between the differential signals. All VCC and VEE pins must be
connected to solid copper planes by using low inductance
connections. When the connections are made through vias,
multiple vias should be used in parallel to reduce the parasitic
inductance. Each VEE pin must be locally decoupled with high
quality capacitors. If proper decoupling cannot be achieved
using a single capacitor, the user can use multiple capacitors in
parallel for each VEE pin. A 20 μF tantalum capacitor must be
used as a general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2526, see
the Amkor Technology® Application Notes for Surface Mount
Assembly of Amkor’s
MicroLeadFrame® (MLF®) Packages.
Table 7. Recommended Components for AC-Coupling
Component Value Description
R1, R2 36 Ω 0603 size resistor
R3, R4 200 Ω 0603 size resistor
C3, C4 100 nF 0603 size capacitor, Phycomp 223878615649
L2, L3 20 nH 0402 size inductor, Murata LQW15AN20NJ0
L6, L7 0402 size ferrite Murata BLM15HG102SN1
L1, L4, L5, L8 10 μH 0603 size inductor, Murata LQM21FN100M70L
VCC
VCC
L1
L2
GND
GND
L3
L4 R2
VCC
R1
C4
C3
GND
BSET
VCC VCC
DATAP
DATAN
MSET
Z0 = 50Ω Z0 = 25Ω Z0 = 25Ω
= 50Ω
Z
0
VCC
3.3V
BSET IBMO N IBI AS VEE
VCC
DATAP
C1
DATAN
C2
VCC
MSET CPA ALS VEE
VCC
C7
200µF
GND
TP1
ADN2526
CPA
R5
1kΩ
ALS
C5
10nF
VCC
IMODP
IMODN
VCC
C6
10nF
GND
GND
VCC
Z0 = 25Ω Z0 = 25Ω
VCC
Figure 34. Typical Application Circuit
L8
L7
L6
L5 R3
VCC
R4
TOSA
7511-034
Rev. A | Page 14 of 16
ADN2526
K
V
is the dc voltage drop across L1, L2, L3, and L4. Assuming
DESIGN EXAMPLE
This design example covers:
• Headroom calculations for the IBIAS, IMODP, and
IMODN pins.
• Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation
currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is V
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Ta b le 1 .
Considering the typical application circuit shown in Figure 34,
the voltage at the IBIAS pin can be written as
V
= VCC − VF − (IBIAS × R
IBIAS
TOSA
) − VLA
where:
VCC is the supply voltage.
V
is the forward voltage across the laser at low current.
F
R
is the resistance of the TOSA.
TOSA
V
is the dc voltage drop across L5, L6, L7, and L8.
LA
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that V
= 0 V, VF = 1 V, and IBIAS =
LA
40 mA
V
= 3.3 − 1 − (0.04 × 25) = 1.3 V
IBIAS
V
= 1.3 V > 0.6 V, which satisfies the requirement.
IBIAS
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V
COMPLIANCE_MAX
= VCC − 0.75 − 4.4 × IBIAS (2)
For this example,
V
COMPLIANCE_MAX
V
= 1.3 V < 2.53 V, which satisfies the requirement.
IBIAS
= VCC – 0.75 − 4.4 × 0.04 = 2.53 V
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC, due to the ac-coupled configuration, and a swing equal
to IMOD
× 25 Ω. For proper operation of the ADN2526, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
= 1 V,
F
LB
that V
= 0 V and IMOD = 60 mA, the minimum voltage at the
LB
modulation output pins is equal to
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2526 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Tab l e 1 . Assuming that IBIAS = 40 mA
and the typical IBIAS/V
ratio of 100 mA/V, the BSET voltage
BSET
is given by
BSET
IBIAS
mA/V100
V
40
100
V4.0
===
(mA)
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Tab l e 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
IMOD
=
V
MSET
where
K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K is equal to 120 mA/V.
Assuming that IMOD = 60 mA and using the preceding
equation, the MSET voltage is given by
V
MSET
(mA)
mA/V120
60
120
V5.0
===
IMOD
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
Rev. A | Page 15 of 16
ADN2526
OUTLINE DIMENSIONS
0.50
EXPOSED
PAD
0.40
0.30
16
1
4
5
P
N
I
N
I
D
*
1.65
1.50 SQ
1.35
0.25 MIN
1
R
O
C
I
A
T
071708-A
0.45
0.50
BSC
1.50 REF
0.60 MAX
BOTTOM VIE W
13
12
9
8
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.
PIN 1
INDICATOR
0.90
0.85
0.80
SEATING
PLANE
12° MAX
3.00
BSC SQ
VIEW
0.30
0.23
0.18
TOP
2.75
BSC SQ
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
*
COMPLIANT
EXCEPT FO R EXPOSED PAD DI MENSION.
TO
JEDEC STANDARDS MO-220-VEED-2
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADN2526ACPZ1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 F0C
ADN2526ACPZ-R21 −40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape & Reel, 250-Piece Reel CP-16-3 F0C
ADN2526ACPZ-R71 −40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape & Reel, 1,500-Piece Reel CP-16-3 F0C
1
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07511-0-8/09(A)
Rev. A | Page 16 of 16
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