Analog Devices ADN2525 Datasheet

10.7 Gbps Active Back-Termination,

FEATURES

Up to 10.7 Gbps operation
Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA)
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
PECL-/CML-compatible data inputs
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Automatic laser shutdown (ALS)

3.3 V operation
Compact 3 mm × 3 mm LFCSP package
Voltage input control for bias and modulation currents
XFP-compliant bias current monitor
Optical evaluation board available

APPLICATIONS

SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/XPAK/MSA 300 optical modules
SR and VSR optical links

Differential Laser Diode Driver

ADN2525

GENERAL DESCRIPTION

The ADN2525 laser diode driver is designed for direct modula­tion of packaged laser diodes having a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2525 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly mis­terminated. The small package provides the optimum solution
for compact modules where laser diodes are packaged in low
pin-count optical subassemblies.

The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The automatic
laser shutdown feature allows the user to turn on/off the bias
and modulation currents by driving the ALS pin with the
proper logic levels.

The product is available in a space-saving 3 mm × 3 mm LFCSP
package specified from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

VCC ALS

VCC

50Ω 50Ω

GND

DATAP

DATAN

800Ω

200Ω

MSET GND BSET

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

VCC

Figure 1.

ADN2525

50ΩIMOD

VCC

800Ω

200Ω

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

200Ω 2Ω

www.analog.com

IMODP

IMODN

IBMON
IBIAS

02461-001

ADN2525

TABLE OF CONTENTS

Specifications..................................................................................... 3

Thermal Specifications ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Input Stage ..................................................................................... 9

Bias Current .................................................................................. 9

Automatic Laser Shutdown (ALS) ........................................... 10

Modulation Current ................................................................... 10

REVISION HISTORY

3/05—Revision 0: Initial Version

Load Mis-termination ............................................................... 12

Power Consumption .................................................................. 12

Applications Information .............................................................. 13

Typical Application Ci rc u it ....................................................... 13

Layout Guidelines....................................................................... 13

Design Example.......................................................................... 14

Headroom Calculations ........................................................ 14

BSET and MSET Pin Voltage Calculation .......................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

ADN2525

SPECIFICATIONS

VCC = VCC
Typical values are specified at 25°C, IMOD = 40 mA.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

BIAS CURRENT (IBIAS)

Bias Current Range 10 100 mA
Bias Current while ALS Asserted 100 µA ALS = high
Compliance Voltage1 0.6 VCC – 1.2 V IBIAS = 100 mA

0.6 VCC – 0.8 V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)

Modulation Current Range 10 80 mA diff R
Modulation Current while ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Random Jitter
Deterministic Jitter3,
Differential |S22| −10 dB 5 GHz < F < 10 GHz, Z0 = 50 Ω differential

−14 dB F < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage1 VCC − 1.1 VCC + 1.1 V

DATA INPUTS (DATAP, DATAN)

Input Data Rate 10.7 Gbps NRZ
Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled
Differential |S11| −16.8 dB F < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential

BIAS CONTROL INPUT (BSET)

BSET Voltage to IBIAS Gain 75 100 120 mA/V
BSET Input Resistance 800 1000 1200 Ω

MODULATION CONTROL INPUT (MSET)

MSET Voltage to IMOD Gain 70 88 110 mA/V See Figure 29
MSET Input Resistance 800 1000 1200 Ω

BIAS MONITOR (IBMON)

IBMON to IBIAS Ratio 10 µA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 %

−4.0 +4.0 %

−2.5 +2.5 %

−2 +2 %

AUTOMATIC LASER SHUTDOWN (ALS)

V

IH

V

IL

I

IL

I

IH

ALS Assert Time 10 µs Rising edge of ALS to fall of IBIAS and IMOD below

ALS Negate Time 10 µs Falling edge of ALS to rise of IBIAS and IMOD above

POWER SUPPLY

V

CC

I

CC5

I

SUPPLY6

1

Refers to the voltage between the pin for which the compliance voltage is specified and GND.

2

The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.

3

Measured using the high speed characterization circuit shown in Figure 3.

4

The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.

5

Only includes current in the ADN2525 VCC pins.

6

Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the section for total supply current calculation. Power Consumption

to VCC

MIN

2, 3

0.4 0.9 ps rms

, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted.

MAX

LOAD

2, 3

24 32.5 ps

2, 3

24 32.5 ps

4

7.2 12 ps p-p

10 mA ≤ IBIAS < 20 mA, R
20 mA ≤ IBIAS < 40 mA, R
40 mA ≤ IBIAS < 70 mA, R
70 mA ≤ IBIAS < 100 mA, R

2.4 V

0.8 V

−20 +20 µA
0 200 µA

10% of nominal; see Figure 2

90% of nominal; see Figure 2

3.07 3.3 3.53 V
39 45 mA V
157 176 mA V

BSET

BSET

= 5 Ω to 50 Ω differential

IBMON

IBMON

IBMON

IBMON

= V

= 0 V

MSET

= V

MSET

= 0 V. I

= ICC + IMODP + IMODN

SUPPLY

= 1 kΩ

= 1 kΩ

= 1 kΩ

= 1 kΩ

Rev. 0 | Page 3 of 16

ADN2525

VEEV

V

THERMAL SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

θ

J-PAD

θ

J-TOP

IC Junction Temperature 125 °C

2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.

65 72.2 79.4 °C/W Thermal resistance from junction to top of package.

ALS

IBIAS

AND IMOD

90%

ALS

NEGATE TIME

t

= 50Ω

Z

0

J2

GND GND GND

J3

GND GND

10%

ALS

ASSERT TIME

Figure 2. ALS Timing Diagram

EE

TP1

VCC

DATAP

DATAN

VCC

VEE

1kΩ

TP2

ADN2525

J8 J5

VBSET

BSET IBMON IBIAS GND

GND

= 50Ω Z0 = 25Ω Z0 = 50Ω

Z

0

10nF

10nF

GND

MSET NC1 ALS GND

VMSET

GND

10Ω

IMODP

IMODN

VCC

VCC

VEE

EE

10nF

10nF

22µF

GND

GND

GND

Z

= 25Ω Z0 = 50ΩZ0 = 50ΩZ0 = 50Ω

0

GND

GND

t

02461-002

GND

BIAS TEE

35Ω

35Ω

GND

GND

BIAS TEE
GND

BIAS TEE: Picosecond Pulse Labs Model 5542-219
Adapter: Pasternack PE-9436 2.92mm female-to-female adapter
Attenuator: Pasternack PE-7046 2.92mm 20dB attenuator

70Ω

GNDGND

VEE

ADAPTER

ADAPTER

ATTENUATOR

ATTENUATOR

GND

50Ω

OSCILLOSCOPE

50Ω

GND

GND GND GND

02461-003

Figure 3. High Speed Characterization Circuit

Rev. 0 | Page 4 of 16

ADN2525

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Min Max Unit

Supply Voltage, VCC to GND −0.3 +4.2 V
IMODP, IMODN to GND VCC − 1 .5 4.75 V
DATAP, DATAN to GND VCC − 1.8 VCC − 0.4 V
All Other Pins −0.3 VCC + 0.3 V
Junction Temperature 150 °C
Storage Temperature −65 +150 °C
Soldering Temperature

(Less than 10 sec)

240 °C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16