Analog Devices ADMCF341BR, ADMCF341 Datasheet

DashDSP™ 28-Lead Flash Mixed-Signal DSP

a

FEATURES
20 MHz Fixed-Point DSP Core

Single-Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units

ALU, Multiplier/Accumulator, Barrel Shifter
Multifunction Instructions
Single-Cycle Context Switch
Powerful Program Sequencer

Zero Overhead Looping

Conditional Instruction Execution
Two Independent Data Address Generators

Memory Configuration

512  16-Bit Data Memory RAM
512  24-Bit Program Memory RAM
4K  24-Bit Program Memory ROM
4K  24-Bit Program Flash Memory

Three Independent Flash Memory Sectors

3584  24-Bit, 256  24-Bit, 256  24-Bit

Low-Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode Support
Integrated Power-On Reset Function
Three-Phase 16-Bit PWM Generation Unit:

16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution to 50 ns
153 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control

with Enhanced Analog Front End

ADMCF341

Individual Enable and Disable for Each PWM Output
High-Frequency Chopping Mode for Transformer

Coupled Gate Drives

External PWMTRIP Pin

Integrated 6-Channel ADC Subsystem

Three Bipolar I
Sample-and-Hold Amplifier and Overcurrent Pro­tection (Usable as Three Dedicated Analog Inputs)

Muxed Auxiliary Analog Inputs

Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency

9-Pin Digital I/O Port

Bit Configurable as Input or Output
Change of State Interrupt Support

Two 16-Bit Auxiliary PWM Timers

Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode

Motor Types

Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
AC Induction Motors (ACIM)

APPLICATIONS
Refrigerator and Air Conditioner Compressor
Washing Machines
Industrial Variable Speed Drives
HVAC

Inputs with Programmable

SENSE

FUNCTIONAL BLOCK DIAGRAM

ADSP-21xx BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 1 DAG 2

ARITHMETIC UNITS

DashDSP is a trademark of Analog Devices, Inc.

MACALU

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

POR TIMER

MEMORY BLOCK

PROGRAM

ROM

4K x 24

PROGRAM

RAM

512 x 24

REV.0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

MOTOR CONTROL PERIPHERALS

PROGRAM

FLASH
4K x 24

DATA

MEMORY

512 x 16

SERIAL PORT

SPORT 0

SPORT 1

7

MULTIPLEXED ON EXTERNAL PINS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADC SUBSYSTEM

V

REF

2.5V

3

ANALOG

INPUTS 16-BIT

PIO

9

3

I

SENSE

AND TRIP

SHA

TIMERS

2 x 16-BIT

AUX

PWM

2

AMP

THREE-

PHASE

WATCH-

DOG

TIMER

6

PWM

(VDD = 5%, GND = 0 V. TA = –40C to +85C. CLKIN = 10 MHz, unless

ADMCF341–SPECIFICATIONS

otherwise noted.)

ANALOG-TO-DIGITAL CONVERTER

Parameter Min Typ Max Unit Conditions/Comments

Signal Input 0.3 3.5 V VAUX0, VAUX1, VAUX2
Resolution
Linearity Error
Zero Offset
Comparator Delay 600 ns
ADC High Level Input Current
ADC Low Level Input Current

NOTES

1

Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

2

2.44KHz sample frequency, VAUX0, VAUX1, VAUX2.

3

Extrapolated point outside of operating range. 2.44KHz sample frequency.

Specifications subject to change without notice.

I

SENSE

Parameter Min Typ Max Unit Conditions/Comments

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

(SNR)
I

SENSE

I

SENSE

I

SENSE

TRIP Threshold Low –690 –430 mV
TRIP Threshold High +430 +690 mV
TRIP Minimum Pulsewidth

NOTES

1

Variation of gain with VDD and temperature.

2

VIN = –400 mV to +400 mV.

3

fIN = 1 kHz sine wave, VIN = –400 mV to +400 mV, fS = 4 kHz.

4

High or low trip threshold.

1

2

3

2

2

–32 0 +7 mV

–10 mAV

3 4 Bits

12 Bits

+10 mAV

= 3.5 V

IN

= 0.0 V

IN

AMPLIFIER–TRIP

Signal Operating Range –400 +400 mV
Signal Input Range –800 +800 mV
Gain –2.6 –2.51 –2.34 % VIN = –400 mV to +400 mV
Gain Channel Matching 5.5 % VIN = –400 mV to +400 mV
Gain Stability
Linearity
Internal Offset Voltage
Internal Offset Stability
Signal-to-Noise Ratio (SNRD)
Signal-to-Noise Ratio Less Distortion 54 dB

3

Total Harmonic Distortion
Input Current –130 +10 mAV
Input Resistance 11.5 kW

1

2

2

2

3

3

4

89 Bits

1.68 1.87 2.1 V

0.8 % VIN = –400 mV to +400 mV

2.1 %
51 dB

–40 dB
–53 dB

= –400 mV to +400 mV

IN

5 ms

CURRENT SOURCE

1

Parameter Min Typ Max Unit Conditions/Comments

Programming Resolution 3 Bits
Tuned Current

NOTES

1

For ADC calibration.

2

0.3 V to 3.5 V I

2

CONST

91 100 109 mA

voltage.

REV. 0–2–

ADMCF341

VOLTAGE REFERENCE

Parameter Min Typ Max Unit Conditions/Comments

Voltage Level (V

)2.442.50 2.55 V –40∞C to +85∞C

REF

Drift 110 ppm/∞C

Specifications subject to change without notice.

POWER-ON RESET

Parameter Min Typ Max Unit Conditions/Comments

Reset Threshold 3.20 3.65 4.10 V
Hysteresis 100 mV
Reset Active Timeout Period 3.2

*216 CLKOUT cycles.

Specifications subject to change without notice.

*

ms

ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit Conditions/Comments

V

IL

V

IH

V

OL

V

OL

V

OH

I

IL

I

IL

I

IH

I

IH

I

IH

I

OZH

I

OZL

I

DD

I

DD

NOTES

1

Output pins PIO0-PIO8, AH, AL, BH, BL, CH, CL.

2

XTAL pin.

3

Internal pull-up, RESET.

4

Internal pull-down, PWMTRIP, PIO0-PIO8.

5

Three stateable pins, DT1, RFS1, TFS1, SCLK1.

6

Outputs not switching.

Specifications subject to change without notice.

Low Level Input Voltage 0.8 V
High Level Input Voltage 2 V
Low Level Output Voltage
Low Level Output Voltage
High Level Output Voltage 4 V I
Low Level Input Current RESET Pin
Low Level Input Current –10 mAV
High Level Input Current RESET Pin
High Level Input Current
High Level Input Current 10 mAV
High Level Three-State Leakage Current
Low Level Three-State Leakage Current5–10 mAV
Supply Current (Idle)
Supply Current (Dynamic)

1

2

3

3

4

6

6

–100 mAV

5

0.4 V I

0.8 V I

30 mAV
100 mAV

100 mAV

55 mA V
135 mA V

2 mA

OL =

= 2 mA

OL

= 0.5 mA

OH

= 0 V

IN

= 0 V

IN

= V

IN

= V

IN

= V

IN

= V

IN

= 0 V

IN

= 5.25 V

DD

= 5.25 V

DD

DD

DD

DD

DD

REV. 0

–3–

ADMCF341

SPECIFICATIONS

(continued)

FLASH MEMORY

Parameter Min Typ Max Unit Conditions/Comments

Endurance 10,000 Cycles Cycle = Erase/Program/Verify
Data Retention 15 Years
Program and Erase Operating Temperature 0 85 ∞C
Read Operating Temperature –40 +85 ∞C

Specifications subject to change without notice.

TIMING PARAMETERS

Parameter Min Max Unit

Clock Signals

Signal tCK is defined as 0.5 t
a frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).
When t

values are within the range of 0.5 t

CK

substituted for all relevant timing parameters to obtain specification value as
in the following example:

ttns ns ns ns

=-=¥-=05 10 05 50 10 15..

CKH CK

Timing Requirements:

t

CKIN

t

CKIL

t

CKIH

CLKIN Period 100 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns

Switching Characteristics:

t

CKL

t

CKH

t

CKOH

CLKOUT Width Low 0.5 tCK – 10 ns
CLKOUT Width High 0.5 tCK – 10 ns
CLKIN High to CLKOUT High 0 20 ns

Control Signals

Switching Characteristics

t

RSP

RESET Width Low 5 tCK* ns

PWM Shutdown Signals

Switching Characteristics

t

PWMTPW

*Applies after power-up sequence is complete.

Specifications subject to change without notice.

PWMTRIP Width Low t

. The ADMCF341 uses an input clock with

CKIN

period, they should be

CKIN

CK

ns

CLKIN

CLKOUT

t

CKIN

t

CKIL

t

CKL

Figure 1. Clock Signals

t

t

CKH

CKOH

t

CKIH

REV. 0–4–

ADMCF341

TIMING PARAMETERS

Parameter Min Max Unit

Serial Ports

Timing Requirements

t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics

t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

SCDD

t

TDE

t

TDV

t

RDV

Specifications subject to change without notice.

SCLK Period 100 ns
DR/TFS/RFS Setup before SCLK Low 15 ns
DR/TFS/RFS Hold after SCLK Low 20 ns
SCLKIN Width 40 ns

CLKOUT High to SCLK

OUT

0.25 t

CK

0.25 tCK + 20 ns
SCLK High to DT Enable 0 ns
SCLK High to DT Valid 30 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 30 ns

OUT

DT Hold after SCLK High 0 ns
SCLK High to DT Disable 30 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 25 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 30 ns

CLKOUT

SCLK

RFS
TFS

RFS

OUT

TFS

OUT

TFS

(ALTERNATE

FRAME MODE)

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

RFS

DR

DT

t

CC

IN

IN

t

t

SCDE

t

RH

TDE

t

t

RD

SCDV

t

t

RDV

TDV

t

t

CC

SCS

t

SCK

t

t

SCDD

SCP

t

SCP

t

SCH

t

SCDH

Figure 2. Serial Port Timing

REV. 0

–5–

ADMCF341

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Supply Voltage (AV

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V

) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

DD

+0.3 V

DD

+0.3 V

DD

Operating Temperature Range (Ambient) . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280∞C

*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

PIN CONFIGURATION

CLKIN

XTAL

I

SENSE

I

SENSE

I

SENSE

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

3

13

2

14

1

ADMCF341

TOP VIEW

(Not to Scale)

PORTA6/DR1 PORTA7/(AUX1/PWMSYNC)

PORTA5/(FL1/DT1) PORTA8/(AUX0/CLKOUT)

PORTA4/(SCLK1/SCLK0) AL

PORTA3/TFS0

PORTA2/RFS0 BL

PORTA1/DT0 BH

PORTA0/DR0

PWMTRIP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AH

CL

CH

RESET

GND

I

CONST

VAUX2

VAUX1

VAUX0

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Pin Type

1 PORTA6/DR1 I/O
2 PORTA5/(FL1/DT1) I/O
3 PORTA4/(SCLK1/SCLK0) I/O
4 PORTA3/TFS0 I/O
5 PORTA2/RFS0 I/O
6 PORTA1/DT0 I/O
7 PORTA0/DR0 I/O
8 CLKIN I
9 XTAL O
10 V

DD

SUP
11 PWMTRIP I
12 I
13 I
14 I

3I

SENSE

2I

SENSE

1I

SENSE

15 VAUX0 I
16 VAUX1 I
17 VAUX2 I
18 I

CONST

O
19 GND GND
20 RESET I
21 CH O
22 CL O
23 BH O
24 BL O
25 AH O
26 AL O
27 PORTA8/(AUX0/CLKOUT) I/O
28 PORTA7/(AUX1/PWMSYNC) I/O

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option

ADMCF341BR –40∞C to +85∞C 20 MHz 28-Lead Wide Body (SOIC) R-28
ADMCF341-EVALKIT N/A N/A Development Tool Kit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADMCF341 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–

ADMCF341

GENERAL DESCRIPTION

The ADMCF341 is a low-cost, single-chip DSP-based control­ler, suitable for permanent magnet synchronous motors, ac
induction motors, and brushless dc motors. The ADMCF341
integrates a 20 MHz, fixed-point DSP core with a complete set
of motor control and system peripherals that permits fast,
efficient development of motor controllers.

The DSP core of the ADMCF341 is completely code-compatible
with the ADSP-21xx DSP family and combines three computa­tional units, data address generators, and a program sequencer.
The computational units are an ALU, a multiplier/accumulator
(MAC), and a barrel shifter. There are special instructions for
bit manipulation, multiplication (⫻ squared), biased rounding,
and global interrupt masking. The system peripherals are the
power-on reset circuit (POR), the watchdog timer, and two
synchronous serial ports. The serial ports are configurable and
double buffered, with hardware support for UART, SCI, and
SPI port emulation. The ADMCF341 provides 512 ⫻ 24-bit
program memory RAM, 4K ⫻ 24-bit program memory ROM,
4K ⫻ 24-bit program FLASH memory, and 512 ⫻ 16-bit data
memory RAM. The user code can be stored and executed from
the flash memory. The program and data memory RAM can be
used for dynamic data storage or can be loaded through the
serial port from an external device as in other ADMCxxx family
parts. The program memory ROM contains a monitor function
as well as useful routines for erasing, programming, and verifying
the flash memory.

The motor control peripherals of the ADMCF341 provide a
12-bit analog data acquisition system with six analog input
channels with three dedicated I

inputs (combining internal

SENSE

amplification, sampling, and overcurrent PWM shutdown
features) and an internal voltage reference. In addition, a three­phase, 16-bit, center-based PWM generation unit can be used

to produce high accuracy PWM signals with minimal processor
overhead. The ADMCF341 also contains two 16-bit auxiliary
PWM timer outputs and nine lines of digital I/O.

Because the ADMCF341 has a limited number of pins, functions
such as the auxiliary PWM timers and the serial communication
ports are multiplexed with the nine programmable digital input/
output (PIO) pins. The pin functions can be independently
selected to allow maximum flexibility for different applications.

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the
ADMCF341. The flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera­tions in parallel. In one processor cycle (50 ns with a 10 MHz
CLKIN) the DSP core can:

∑

Generate the next program address

∑

Fetch the next instruction

∑

Perform one or two data moves

∑

Update one or two data address pointers

∑

Perform a computational operation

This all takes place while the processor continues to:

∑

Receive and transmit through the serial ports

∑

Decrement the interval timer

∑

Generate three-phase PWM waveforms for a power inverter

∑

Generate two signals using the 16-bit auxiliary PWM timers

∑

Acquire four analog signals

∑

Decrement the watchdog timer

DATA

ADDRESS

GENERATOR

#1

INPUT REGS

ALU

OUTPUT REGS

DATA

ADDRESS

GENERATOR

#2

INPUT REGS

OUTPUT REGS

MAC

INSTRUCTION

REGISTER

PM ROM
4K  24

PROGRAM

SEQUENCER

16

R BUS

14

14

24

BUS

EXCHANGE

16

INPUT REGS

SHIFTER

OUTPUT REGS

PM RAM

512  24

CONTROL

LOGIC

Figure 3. DSP Core Block Diagram

PMA BUS

DMA BUS

PMD BUS

DMD BUS

COMPANDING

CIRCUITRY

FLASH

PROGRAM

MEMORY

4K  24

TRANSMIT REG

RECEIVE REG

SERIAL

PORT

6

DM RAM
512  16

TIMER

REV. 0

–7–

ADMCF341

The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations as well as provides support for division
primitives. The MAC performs single-cycle multiply, multiply/add,
and multiply/subtract operations with 40 bits of accumulation.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive-exponent operations. The shifter
can be used to efficiently implement numeric format control,
including floating-point representations. The internal result (R)
bus directly connects the computational units so that the output
of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMCF341 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro­gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modifications (M registers). A length value may be
associated with each pointer (L registers) to implement auto­matic modulo addressing for circular buffers. The circular
buffering feature is also used by the serial ports for automatic
data transfers to and from on-chip memory. DAG1 generates
only data memory addresses and provides an optional bit-reversal
capability. DAG2 may generate either program or data memory
addresses but has no bit-reversal capability. Efficient data trans­fer is achieved with the use of five internal buses:

∑

Program memory address (PMA) bus

∑

Program memory data (PMD) bus

∑

Data memory address (DMA) bus

∑

Data memory data (DMD) bus

∑

Result (R) bus

Program memory can store both instructions and data, permit­ting the ADMCF341 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMCF341 can fetch an operand from on-chip program
memory and the next instruction in the same cycle. The
ADMCF341 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower 8
bits. When it reads data (not instructions) from 24-bit program
memory to a 16-bit data register, the lower 8 bits are placed in
the PX register.

The ADMCF341 can respond to a number of distinct DSP
core and peripheral interrupts. The DSP interrupts comprise a
serial port receive interrupt, a serial port transmit interrupt, a
timer interrupt, and two software interrupts. Additionally, the
motor control peripherals include two PWM interrupts and a
PIO interrupt.

Serial port 0 (SPORT0) provides a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed and unframed data transmit and receive

modes of operation. Serial port 1 (SPORT1) is available with a
limited number of I/Os. It is mainly intended for codebooting to
serial ROMs (SROM) and support of the debugging tools.
SPORT0 and SPORT1 can generate an internal programmable
serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n – 1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an inter­rupt is generated, and the count register is reloaded from a
16-bit period register (TPERIOD).

The ADMCF341 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 50 ns
processor cycle (for a 10 MHz CLKIN). The ADMCF341
assembly language uses an algebraic syntax for ease of coding
and readability. A comprehensive set of development tools
supports program development. For further information on the
DSP core, refer to the ADSP-2100 Family User’s Manual, Third
Edition, with particular reference to the ADSP-2171.

SERIAL PORTS

The ADMCF341 incorporates two complete synchronous serial
ports (SPORT1 and SPORT0) for serial communication and
multiprocessor communication.

Following is a brief list of capabilities of the ADMCF341
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.

∑

SPORTs are bidirectional and have a separate, double-buff­ered transmit and receive section.

∑

SPORTs use an external serial clock or generate their own
serial clock internally.

∑

SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gener­ated. Frame synchronization signals are active high or
inverted, with either of two pulsewidths and timings.

∑

SPORTs support serial data word lengths from 3 bits to
16 bits and provides optional A-law and m-law companding
according to ITU (formerly CCITT) recommendation
G.711.

∑

SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

∑

SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.

∑

SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word, or 32-word, timedivision multi­plexed, serial bitstream.

∑

SPORT0 can be configured as an SPI port (master mode
only). The clock phase and polarity are programmable
through the MODECTRL register.

∑

SPORT1 is the default port for program/data memory boot
loading and for development tools interface. The DT1/FL1
pin can be configured as SROM/E

2

PROM reset signal.

REV. 0–8–

ADMCF341

PIN FUNCTION DESCRIPTION

The ADMCF341 is available in a 28-lead SOIC package.
Table I describes the pins.

Table I. Pin List

Pin Group No. of Input/
Name Pins Output Function

RESET 1I Processor Reset Input
SPORT1

SPORT0

CLKOUT 1

1

1

2 I/O Serial Port 1 Pins (DT1/FL1,

DR1, SCLK1/SCLK0

5 I/O Serial Port 0 Pins (DT0, DR0

1

I/O Processor Clock Output

TFSO, SCLK1/SCLK0

2

)

2

)

CLKIN, XTAL 2 I, O External Clock or Quartz

Crystal Connection Point
PORTA0– 9 I/O Digital I/O Port Pins
PORTA8

1

AUX0–AUX112O Auxiliary PWM Outputs
AH–CL 6 O PWM Outputs
PWMTRIP 1I PWM Trip Signal

1– 3 I I

I

SENSE

3

I

SENSE

SENSE

Inputs

VAUX0–VAUX2 3 I Auxiliary Analog Inputs
I

CONST

1O ADC Constant Current

Source
V

DD

1I Power Supply

GND 1 I Ground

NOTES

1

Multiplexed pins, individually selectable through PORTA_SELECT
and PORTA_DATA registers.

2

SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.

INTERRUPT OVERVIEW

The ADMCF341 can respond to 18 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 11 from the motor control peripherals. The
seven DSP core interrupts are SPORT1 receive (or IRQ0) and
transmit (or IRQ1), SPORT0 receive and transmit, the internal
timer, and two software interrupts. The motor control periph­eral interrupts are the nine programmable I/Os and two from
the PWM (PWMSYNC pulse and PWMTRIP). All motor
control interrupts are multiplexed into the DSP core through
the peripheral IRQ2 interrupt. The interrupts are internally
prioritized and individually maskable. A detailed description of the
entire interrupt system of the ADMCF341 is presented later,
following a more detailed description of each peripheral block.

MEMORY MAP

The ADMCF341 has two distinct memory types: program and
data. In general, program memory contains user code and coef­ficients, while the data memory is used to store variables and
data during program execution. Three kinds of program
memory are provided on the ADMCF341: RAM, ROM, and
FLASH. The motor control peripherals are memory mapped
into a region of the data memory space starting at 0x2000. The
complete program and data memory maps are given in Tables II
and III, respectively.

Table II. Program Memory Map

Memory

Address Range Type Function

0x0000–0x002F RAM Internal Vector Table
0x0030–0x01FF RAM User Program Memory
0x0200–0x07FF Reserved
0x0800–0x17FF ROM Reserved Program Memory
0x1800–0x1FFF Reserved
0x2000–0x20FF FLASH User Program Memory

Sector 0

0x2100–0x21FF FLASH User Program Memory

Sector 1

0x2200–0x2FFF FLASH User Program Memory

Sector 2

0x3000–0x3FFF Reserved

Table III. Data Memory Map

Memory

Address Range Type Function

0x0000–0x1FFF Reserved
0x2000–0x20FF Memory Mapped Registers
0x2100–0x37FF Reserved
0x3800–0x39FF RAM User Data Memory
0x3A00–0x3BFF RAM Reserved
0x3C00–0x3FFF Memory Mapped Registers

FLASH MEMORY SUBSYSTEM

The ADMCF341 has 4K ⫻ 24-bits of user-programmable,
nonvolatile flash memory. A flash programming utility is pro­vided with the development tools, which perform the basic
device programming operations: erase, program, and verify.

The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
sector 0, sector 1, and sector 2, respectively. These sectors are
mapped into external program memory address space.

Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named flash memory control register
(FMCR), flash memory address register (FMAR), flash memory
data register low (FMDRL), and flash memory data register
high (FMDRH). These registers are diagrammed later in this
data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should
not modify them directly. The flash programming utility pro­vides a complete interface to the flash memory.

It should be noted that the core accesses flash memory through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required.

REV. 0

–9–

ADMCF341

Special Flash Registers

The flash module has four nonvolatile 8-bit registers called
special flash registers (SFRs) that are accessible independent of
the main flash array, via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the special flash registers contain all 0s. To read special
flash registers from the user program, call the read_reg routine
contained in ROM. Refer to the ADMCF34x DSP Motor Con-
troller Developers Reference Manual for an example.

Boot-from-Flash Code

A security feature is available in the form of a code that, when
set, causes the processor to execute the program in flash
memory at power-up or reset. In this mode, the flash program­ming utility and debugger are unable to communicate with the
ADMCF341. Consequently, the contents of the flash memory
can be neither programmed nor read.

The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way to
clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in the
ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An
example would be to detect a high level on a PIO pin during
startup initialization and then call the flash_init or auto_erase_reg
routine. The flash_init routine will erase the entire user program
in flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.

Refer to the ADMCF34x DSP Motor Controller Developer’s Refer-
ence Manual for further instructions and an example of using the
boot-from-flash code.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execu­tion at address 0x0800 of internal program ROM. The ROM
monitor program that is located there checks the boot-from­flash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user’s application program.

If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers Reference Manual.

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMCF341
with an external crystal.

CLKOUT

ADMCF341

RESET

XTAL

CLKIN

22pF

10MHz

22pF

Figure 4. Basic System Configuration

Clock Signals

The ADMCF341 can be clocked either by a crystal or a TTL­compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMCF341. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF341 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.

Because the ADMCF341 includes an on-chip oscillator feed­back circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the
processor’s cycle rate of twice the input frequency.

Reset

The ADMCF341 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper unitiza­tion. The ADMCF341 contains an integrated power-on-reset
(POR) circuit that provides a complete system reset on power­up and power-down. The POR circuit monitors the voltage on
the ADMCF341 VDD pin and holds the DSP core and periph­erals in reset while VDD is less than the threshold voltage level,
VRST. When this voltage is exceeded, the ADMCF341 is held
in reset for an additional 216 DSP clock cycles (T
ure 5). During this time (T

), the supply voltage must reach

RST

RST

in Fig-

the recommended operating condition. On power-down, when
the voltage on the VDD pin falls below V

RST

–V

HYST

, the

ADMCF341 will be reset. Also, if the external RESET pin is
actively pulled low at any time after power-up, a complete hard­ware reset of the ADMCF341 is initiated.

V

RST

V

DD

V

V

RST

HYST

–

RESET

T

RST

Figure 5. Power-On Reset Operation

REV. 0–10–

ADMCF341

The ADMCF341 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register,
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET pin low.
The RESET signal must be the minimum pulsewidth specifica­tion, t

. Following the reset sequence, the DSP core starts

RSP

executing code from the internal PM ROM located at 0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL,
memory-mapped at DM (0x3FFF). SPORT1 must be configured
as a serial port by setting Bit 10. SPORT0 and SPORT1 are
enabled by setting Bit 11 and Bit 12.

The DSP core has a wait state control register, MEMWAIT,
memory-mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMCF341,
this register must always contain the value 0x8000. This value
sets the minimum access time to the program memory.

The configurations of both the SYSCNTL and MEMWAIT regis­ters of the ADMCF341 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER
Overview

The PWM generator block of the ADMCF341 is a flexible,
programmable three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
motors (ACIM) or permanent magnet synchronous motors
(PMSM). In addition, the PWM block contains special func­tions that considerably simplify the generation of the required

PWM switching patterns for control of brushless dc motors
(BDCM), including electronically commutated motors (ECM).

The six PWM output signals consist of three high side drive
signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are pro­grammable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the
three pairs of PWM signals.

Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the high side PWM signals
are diverted to the complementary low side output and the low
side signals are diverted to the corresponding high side outputs.

In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques: optical isolation using optocouplers, and trans­former isolation using pulse transformers. The PWM controller
of the ADMCF341 permits mixing of the output PWM signals
with a high-frequency chopping signal to permit an easy inter­face to such pulse transformers. The features of this gate-drive
chopping mode can be controlled by the PWMGATE register.
There is an 8-bit value within the PWMGATE register that
directly controls the chopping frequency. In addition, high­frequency chopping can be independently enabled for the high
side and the low side outputs using separate control bits in the
PWMGATE register.

PWM CONFIGURATION

REGISTERS

PWMTM (15...0)
PWMDT (9...0)
PWMPD (9...0)
PWMSYNCWT (7...0)
MODECTRL (6)

THREE-PHASE

PWM TIMING

CLK RESETSYNC

PWMSYNC

TO INTERRUPT
CONTROLLER

PWMTRIP

PWM DUTY CYCLE

REGISTERS

PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)

UNIT

PWMSEG (8...0)

OUTPUT

CONTROL

UNIT

SYNC

OR

PWMSWT (0)

PWM SHUTDOWN CONTROLLER

PWMGATE (9...0)

OVER-

CURRENT

Figure 6. Overview of the PWM Controller of the ADMCF341

GATE

DRIVE

UNIT

CLK

TRIP

CLKOUT

ANALOG BLOCK

AH
AL
BH

BL
CH
CL

PWMTRIP

I

SENSE

I

SENSE

I

SENSE

1

2

3

REV. 0

–11–