Analog Devices ADMCF340BST, ADMCF340 Datasheet

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DashDSPTM 64-Lead Flash Mixed-Signal DSP

TARGET APPLICATIONS Refrigerator and Air Conditioner Compressors,

Washing Machines

Industrial Variable Speed Drives, HVAC

MOTOR TYPES Permanent Magnet Synchronous Motors (PMSM),

Brushless DC Motors (BDCM), AC Induction Motors (ACIM), Switched Reluctance Motors (SRM)

FEATURES 20 MHz Fixed-Point DSP Core

Single Cycle Instruction Execution (50 ns) ADSP-21xx Family Code Compatibility Independent Computational Units

ALU Multiplier/Accumulator

Barrel Shifter Multifunction Instructions Single Cycle Context Switch Powerful Program Sequencer

Zero Overhead Looping

Conditional Instruction Execution Two Independent Data Address Generators

with Enhanced Analog Front End

ADMCF340

Memory Configuration

512  16-Bit Data Memory RAM 512  24-Bit Program Memory RAM 4K  24-Bit Program Memory ROM 4K  24-Bit Total Program FLASH Memory

Three Independent FLASH Memory Sectors

3584  24-Bit, 256  24-Bit, 256  24-Bit Low Cost Pin-Compatible ROM Option 16-Bit Watchdog Timer Programmable 16-Bit Internal Timer with Prescaler Two Double Buffered Serial Ports with SPI Mode

Support Integrated Power On Reset Function Three Phase 16-Bit PWM Generation Unit

16-Bit Center-Based PWM Generator

Programmable PWM Pulsewidth

Edge Resolution of 50 ns

Programmable Narrow Pulse Deletion

153 Hz Minimum Switching Frequency

Double/Single Update Mode Control

Individual Enable and Disable for Each PWM

Output

High Frequency Chopping Mode for

Transformer-Coupled Gate Drives

FUNCTIONAL BLOCK DIAGRAM

ADSP-21xx BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 1 DAG 2

ARITHMETIC UNITS

DashDSP is a trademark of Analog Devices, Inc.

MACALU

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

POR

MEMORY BLOCK

PROGRAM

ROM

4K  24

PROGRAM

RAM

512  24

TIMER

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

(continued on page 8)

MOTOR CONTROL PERIPHERALS

SENSE

AND TRIP

SHA

TIMERS

2  16-BIT

AUX

PWM

225

AMP

16-BIT

THREE-

PHASE

PWM

WATCH-

DOG

TIMER

PROGRAM

FLASH

4K  24

DATA

MEMORY

512  16

SERIAL PORT

SPORT 0

SPORT 1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

ADC SUBSYSTEM

ANALOG

REF

2.5V

INPUTS

PIO

ADMCF340

(VDD = 5%, GND = 0 V, TA = –40C to +85C, CLKIN = 10 MHz, unless

ANALOG-TO-DIGITAL CONVERTER

Parameter Min Typ Max Unit Conditions/Comments

Signal Input 0.3 3.5 V VAUX0, VAUX1, VAUX2 Resolution Linearity Error Zero Offset Comparator Delay 600 ns ADC High Level Input Current ADC Low Level Input Current

NOTES

Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

2.44 kHz sample frequency, VAUX0, VAUX1, VAUX2

Extrapolated point outside of operating range. 2.44 kHz sample frequency

Specifications subject to change without notice.

–32 0 +7 mV

–10 µAV

otherwise noted.)

12 Bits

3 4 Bits

10 µAV

= 3.5 V

= 0.0 V

AMPLIFIER–TRIP

SENSE

Parameter Min Typ Max Unit Conditions/Comments

Signal Operating Range –400 +400 mV

SENSE

Gain –2.6 –2.51 –2.34 % VIN = –400 mV to +400 mV

SENSE

Gain Channel Matching 5.5 % VIN = –400 mV to +400 mV

SENSE

Gain Stability

SENSE

Linearity

SENSE

Internal Offset Voltage

SENSE

Internal Offset Stability

SENSE

Signal-to-Noise Ratio (SNR)

SENSE

Signal-to-Noise Ratio Less Distortion 54 dB

SENSE

(SNR) I

Total Harmonic Distortion

SENSE

Input Current –200 +10 µAV

SENSE

Input Resistance 11.5 kΩ

SENSE

89 Bits

1.68 1.87 2.1 V

0.8 % VIN = –400 mV to +400 mV

2.1 % 51 dB

–40 dB –53 dB

= –400 mV to +400 mV

TRIP Threshold Low –690 –430 mV TRIP Threshold High 430 690 mV TRIP Minimum Pulsewidth

NOTES

Variation of gain with VDD and temperature

VIN = –400 mV to +400 mV.

fIN = 1 kHz sine wave, VIN = –400 mV to +400 mV, fS = 4 kHz.

High or low trip threshold

CURRENT SOURCE

5 µs

Parameter Min Typ Max Unit Conditions/Comments

Programming Resolution 3 Bits Tuned Current

NOTES

For ADC calibration

0.3 V to 3.5 V I

CONST

91 100 109 µA

voltage

–2–

REV. 0

ADMCF340

VOLTAGE REFERENCE

Parameter Min Typ Max Unit Conditions/Comments

Voltage Level (V

)2.44 2.50 2.55 V –40°C to +85°C

REF

Drift 110 ppm/°C

Speciﬁcations subject to change without notice.

POWER-ON RESET

Parameter Min Typ Max Unit Conditions/Comments

Reset Threshold 3.20 3.65 4.10 V Hysteresis 100 mV Reset Active Timeout Period 3.2

*216 CLKOUT cycles

Speciﬁcations subject to change without notice.

ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit Conditions/Comments

OZH

OZL

NOTES

PWMPOL and PWMSR Pins only

Output pins PORTA0–PORTA8, PORTB0–PORTB15, AH, AL, BH, BL, CH, CL

XTAL Pin

Internal pull-up, RESET

Internal pull-down, PWMTRIP, PORTA0–PORTA8, PORTB0–PORTB15

Three stateable pins, DT1, RFS1, TFS1, SCLK1

Outputs not switching

Speciﬁcations subject to change without notice.

Low Level Input Voltage 0.8 V High Level Input Voltage 2 V Low Level Input Voltage High Level Input Voltage 2.60 V Low Level Output Voltage Low Level Output Voltage High Level Output Voltage 4 V I Low Level Input Current RESET Pin Low Level Input Current –10 µAV High Level Input Current RESET Pin High Level Input Current High Level Input Current 10 µAV High Level Three-State Leakage Current Low Level Three-State Leakage Current6–10 µAV Supply Current (Idle) Supply Current (Dynamic)

–100 µAV

1.75 V

0.4 V I

0.8 V I

30 µAV 100 µAV

100 µAV

55 mA V 135 mA V

2 mA

OL =

= 2 mA

= 0.5 mA

= 0 V

= V

= 0 V

= 5.25 V

REV. 0

–3–

ADMCF340

TIMING PARAMETERS

Parameter Min Max Unit

Clock Signals

Signal TCK is defined as 0.5 t a frequency equal to half the instruction rate; a 10 MHz input clock (which is equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When T

values are within the range of 0.5 t

substituted for all relevant timing parameters to obtain specification value as in the following example:

t T ns ns ns ns

=−=×−=05 10 05 50 10 15..

CKH CK

Timing Requirements:

CKIN

CKIL

CKIH

CLKIN Period 100 150 ns CLKIN Width Low 20 ns CLKIN Width High 20 ns

Switching Characteristics:

CKL

CKH

CKOH

CLKOUT Width Low 0.5 TCK – 10 ns CLKOUT Width High 0.5 TCK – 10 ns CLKIN High to CLKOUT High 0 20 ns

Control Signals

Timing Requirement:

RSP

RESET Width Low 5 TCK* ns

PWM Shutdown Signals

Timing Requirement:

PWMTPW

*Applies after power-up sequence is complete.

Specifications subject to change without notice.

PWMTRIP Width Low T

. The ADMCF340 uses an input clock with

CKIN

period, they should be

CKIN

CLKIN

CLKOUT

CKIN

CKIL

CKL

Figure 1. Clock Signals

CKOH

CKH

CKIH

–4–

REV. 0

ADMCF340

TIMING PARAMETERS

Parameter Min Max Unit

Serial Ports

Timing Requirements:

SCK

SCS

SCH

SCP

Switching Characteristics: t

SCDE

SCDV

SCDH

SCDD

TDE

TDV

RDV

Specifications subject to change without notice.

SCLK Period 100 ns DR/TFS/RFS Setup before SCLK Low 15 ns DR/TFS/RFS Hold after SCLK Low 20 ns SCLKIN Width 40 ns

CLKOUT High to SCLK

OUT

0.25 T

0.25 TCK + 20 ns

SCLK High to DT Enable 0 ns SCLK High to DT Valid 30 ns TFS/RFS TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 30 ns

OUT

DT Hold after SCLK High 0 ns SCLK High to DT Disable 30 ns TFS (Alt) to DT Enable 0 ns TFS (Alt) to DT Valid 25 ns RFS (Multichannel, Frame Delay Zero) to DT Valid 30 ns

CLKOUT

SCLK

RFS TFS

RFS

OUT

TFS

OUT

TFS

(ALTERNATE

FRAME MODE)

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

RFS

SCDE

TDE

SCDV

TDV

RDV

SCDD

SCS

SCH

SCDH

SCP

SCK

SCP

Figure 2. Serial Port Timing

REV. 0

–5–

ADMCF340

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Supply Voltage (AV

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V

) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

+ 0.3 V

Operating Temperature Range (Ambient) . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AGND

DGND1

RESET

PB6

PB7

PB8

PB9

PB10

PB11

PB12

NC = NO CONNECT

PIN CONFIGURATION

ICONST

VAUX7

VAUX2

VAUX6

VAUX1

VAUX5

VAUX0

VAUX4

ADMCF340

PB14ALPB15

TOP VIEW

(Not to Scale)

PA8/(AUX0/CLKOUT)

PA7/(UX1/PWMSYNC)

PIN 1 IDENTIFIER

PB13

SENSE1

DGND2

PWMSR

SENSE2

SENSE3

PA6/DR1

PWMPOL

PA5/(FL1/DT1)

PA4(SCLK1/SCLK0)

PWMTRIP

PA3/TFS0

DVDD1

XTAL

CLKIN

PB5

PB4

PA0/DR0

PB3

PB2

PA1/DT0

PB1

PB0

PA2/RFS0

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option

ADMCF340BST –40°C to +85°C 20 MHz 64-Lead Thin Plastic Quad Flatpack ST-64

(LQFP)

ADMCF340-EVALKIT N/A N/A Development Tool Kit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMCF340 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–6–

REV. 0

PIN FUNCTION DESCRIPTIONS

ADMCF340

Pin Pin No. Mnemonic Type

1 AGND GND 2 DGND1 GND 3 RESET D_IN 4 PB6 D_I/O 5CH D_OUT 6 PB7 D_I/O 7 PB8 D_I/O 8CL D_OUT 9 PB9 D_I/O 10 PB10 D_I/O 11 BH D_OUT 12 PB11 D_I/O 13 PB12 D_I/O 14 BL D_OUT 15 NC No Connect 16 NC No Connect 17 NC No Connect 18 AH D_OUT 19 PB13 D_I/O 20 PB14 D_I/O 21 AL D_OUT 22 PB15 D_I/O 23 PA8/(AUX0/CLKOUT) D_I/O 24 PA7/(AUX1/PWMSYNC) D_I/O 25 DV

2SUP

26 PWMSR D_IN 27 DGND2 GND 28 PA6/DR1 D_I/O 29 PA5/(FL1/DT1) D_I/O 30 PA4/(SCLK1/SCLK0) D_I/O 31 PWMPOL D-IN 32 PA3/TFS0 D_I/O

Pin Pin No. Mnemonic Type

33 NC No Connect 34 PA2/RFS0 D_I/O 35 PB0 D_I/O 36 PB1 D_I/O 37 PA1/DT0 D_I/O 38 PB2 D_I/O 39 PB3 D_I/O 40 PA0/DR0 D_I/O 41 PB4 D_I/O 42 PB5 D_I/O 43 NC No Connect 44 CLKIN D_I/O 45 NC No Connect 46 XTAL A_OUT 47 DV 48 AV

1SUP

SUP

49 PWMTRIP D_IN 50 V3 A_IN 51 I

SENSE3

A_IN 52 V2 A_IN 53 I

SENSE2

A_IN 54 V1 A_IN 55 I

SENSE1

A_IN 56 VAUX4 A_IN 57 VAUX0 A_IN 58 VAUX5 A_IN 59 VAUX1 A_IN 60 VAUX6 A_IN 61 VAUX2 A_IN 62 VAUX7 A-IN 63 ICONST A_OUT 64 NC No Connect

PA is the abbreviation of PORTA; PB is the abbreviation of PORTB.

REV. 0

–7–

ADMCF340

(continued from page 1)

External PWMTRIP Pin Switched Reluctance Motor Mode Selection Pin

PWM Polarity Selection Pin Integrated 13-Channel ADC Subsystem Three Bipolar I

Inputs with Programmable

SENSE

Sample and Hold Amplifier and Overcurrent

Protection (Usable as Three Dedicated Analog Inputs) Three Simultaneous Converting Voltage Inputs Seven Muxed Auxiliary Analog Inputs Internal Voltage Reference (2.5 V) Acquisition Synchronized to PWM Switching

Frequency 25-Pin Digital I/O Port Bit Configurable as Input or Output Change of State Interrupt Support Two 16-Bit Auxiliary PWM Timers Synthesized Analog Output Programmable Frequency 0% to 100% Duty Cycle Two Programmable Operation Modes Independent Mode/Offset Mode

GENERAL DESCRIPTION

The ADMCF340 is a low cost, single-chip DSP-based controller suitable for permanent magnet synchronous, ac induction, switched reluctance, and brushless dc motors. The ADMCF340 integrates a 20 MHz, fixed-point DSP core with a complete set of motor control and system peripherals that permit fast, efficient development of motor controllers.

The DSP core of the ADMCF340 is completely code compatible with the ADSP-21xx DSP family and combines three computa-

tional units, data address generators, and a program sequencer. The computational units comprise an ALU, a multiplier/accumulator (MAC), and a barrel shifter. There are special instructions for bit manipulation, multiplication (x squared), biased rounding, and global interrupt masking. The system peripherals are the power-on reset circuit (POR), the watchdog timer, and two synchronous serial ports. The serial ports are configurable, and double buffered, with hardware support for UART, SCI, and SPI port emulation. The ADMCF340 provides 512 × 24-bit program memory RAM, 4K × 24-bit program memory ROM, 4K × 24-bit program FLASH memory, and 512 × 16-bit data memory RAM. The user code will be stored and executed from the flash memory. The program and data memory RAM can be used for dynamic data storage or can be loaded through the serial port from an external device as in other ADMCxx family parts. The program memory ROM contains a monitor function as well as useful routines for erasing, programming, and verifying the flash memory.

The motor control peripherals of the ADMCF340 provide a 12-bit analog data acquisition system with 13 analog input channels, three dedicated I

functions (combining internal amplifi-

SENSE

cation, sampling, and overcurrent PWM shutdown features), and an internal voltage reference. In addition, a three-phase, 16-bit, center-based PWM generation unit can be used to produce high accuracy PWM signals with minimal processor overhead. The ADMCF340 also contains two 16-bit auxiliary PWM timers and 25 lines of programmable digital I/O.

Several functions such as the auxiliary PWM and the serial communication ports are multiplexed with the nine PORT A (9, PIO) programmable input/output (PIO) pins. The other 16 programmable digital I/O are dedicated. The pin functions can be independently selected to allow maximum flexibility for different applications.

DATA

ADDRESS

GENERATOR

INPUT REGS

ALU

OUTPUT REGS

DATA

ADDRESS

GENERATOR

INPUT REGS

OUTPUT REGS

MAC

INSTRUCTION

PM ROM

4K  24

PROGRAM

SEQUENCER

R BUS

BUS

EXCHANGE

INPUT REGS

SHIFTER

OUTPUT REGS

PM RAM 512  24

CONTROL

LOGIC

Figure 3. DSP Core Block Diagram

–8–

PMA BUS

DMA BUS

PMD BUS

DMD BUS

COMPANDING

CIRCUITRY

FLASH

PROGRAM

MEMORY

4K  24

TRANSMIT REG

RECEIVE REG

SERIAL

PORT

DM RAM 512  16

TIMER

REV. 0

ADMCF340

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the

ADMCF340. The flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle (50 ns with a 10 MHz

CLKIN) the DSP core can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This all takes place while the processor continues to:

•

Receive and transmit through the serial ports

•

Decrement the interval timer

•

Generate three-phase PWM waveforms for a power inverter

•

Generate two signals using the 16-bit auxiliary PWM timers

•

Acquire four analog signals

•

Decrement the watchdog timer

The processor contains three independent computational units:

the arithmetic and logic unit (ALU), the multiplier/accumulator

(MAC), and the shifter. The computational units process 16-bit

data directly and have provisions to support multiprecision com-

putations. The ALU performs a standard set of arithmetic and

logic operations as well as providing support for division primitives.

The MAC performs single-cycle multiply, multiply/add, and

multiply/subtract operations with 40 bits of accumulation. The

shifter performs logical and arithmetic shifts, normalization,

denormalization, and derive-exponent operations. The shifter

can be used to implement numeric format control efficiently,

including floating-point representations. The internal result (R)

bus directly connects the computational units so that the output

of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps and

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADMCF340 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain the loop.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers (I registers). Whenever the pointer is used to access

data (indirect addressing), it is post-modified by the value in

one of four modify (M) registers. A length value may be associated

with each pointer (L registers) to implement automatic modulo

addressing for circular buffers. The circular buffering feature is

also used by the serial ports for automatic data transfers to and

from on-chip memory. DAG1 generates only data memory address

and provides an optional bit-reversal capability. DAG2 may

generate either program or data memory addresses but has no

bit-reversal capability. Efficient data transfer is achieved with

the use of five internal buses:

•

Program memory address (PMA) bus

•

Program memory data (PMD) bus

•

Data memory address (DMA) bus

•

Data memory data (DMD) bus

•

Result (R) bus

Program memory can store both instructions and data, permitting the ADMCF340 to fetch two operands in a single cycle—one from program memory and one from data memory. The ADMCF340 can fetch an operand from on-chip program memory and the next instruction in the same cycle. The ADMCF340 writes data from its 16-bit registers to the 24-bit program memory using the PX Register to provide the lower eight bits. When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX Register.

The ADMCF340 can respond to a number of distinct DSP core and peripheral interrupts. The DSP interrupts comprise a serial port receive interrupt, a serial port transmit interrupt, a timer interrupt, and two software interrupts. Additionally, the motor control peripherals include two PWM interrupts and a PIO interrupt.

The serial port (SPORT0 ) provides a complete synchronous serial interface with optional companding in hardware and a wide variety of framed and unframed data transmit and receive modes of operation. SPORT0 and SPORT1 can generate an internal programmable serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP core and can be used to generate periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycle, where n – 1 is a scaling value stored in the 8-bit TSCALE Register. When the value of the counter reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

The ADMCF340 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Each instruction is executed in a single 50 ns processor cycle (for a 10 MHz CLKIN). The ADMCF340 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. For further information on the DSP core, refer to the ADSP-2100 Family User’s Manual, Third Edition, with particular reference to the ADSP-2171.

SERIAL PORTS

The ADMCF340 incorporates two synchronous serial ports (SPORT1 and SPORT0) for serial communication and multiprocessor communication. SPORT1 is primarily intended for the interfacing of the debugging tools and/or code booting from an external serial memory.

The following is a brief list of capabilities of the ADMCF340 SPORTs.

•

SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.

•

SPORTs can use an external serial clock or generate their own serial clock internally.

•

SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame synchronization signals are active high or inverted, with either of two pulsewidths and timings.

•

SPORTs support serial data-word lengths from three bits to 16 bits and provide optional A-law and m-law companding according to ITU (formerly CCITT) recommendation G.711.

•

SPORTs’ receive and transmit sections can generate unique interrupts on completing a data-word transfer.

REV. 0

–9–

ADMCF340

•

SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data-word. An interrupt is generated after a data buffer transfer.

•

SPORT0 has one pin, SCLK0, shared with SPORT1. During a boot phase (SPORT1 Boot Mode enabled by a bit in the MODECTRL Register), the serial clock of SPORT1 is externally available. The serial clock of SPORT0 is externally available when the SPORT1 is configured in UART Mode.

•

SPORT0 can be configured as SPI port (master mode only). Refer to Table XI for more information. The clock phase and polarity are programmable through the MODECTRL Register. Refer to Table XI for pin configuration.

•

SPORT0 has a multichannel interface to selectively receive and transmit a 24-word or 32-word time division multiplexed serial bitstream.

•

SPORT1 is the default port for program/data memory boot loading and for the development tools interface. The DT1/FL1 Pin can be configured as the SROM/E

The ADMCF340 is available in a 64-lead LQFP package.

PIN FUNCTION DESCRIPTION

Table I. Pin List

Pin Group # of Input/ Name Pins Output Function

PWMPOL 1 I PWM Polarity PWMSR 1 I PWM Switched

RESET 1 I Processor Reset Input SPORT1

SPORT0

CLKOUT

2 I/O Serial Port 1 Pins

5 I/O Serial Port 0 Pins

I/O Processor Clock

CLKIN, XTAL 2 I/O External Clock or

PORTA0–PORTA8 PORTB0–PORTB15 16 I/O Digital I/O Port Pins AUX0–AUX1

9 I/O Digital I/O Port Pins

2O Auxiliary PWM

AH-CL 6 O PWM Outputs PWMTRIP 1 I PWM Trip Signal V1 to V3 3 I I I

SENSE1 to ISENSE3

3I Analog Inputs VAUX0-VAUX7 7 I Auxiliary Analog Inputs ICONST 1 O ADC Constant

3I Power Supply GND 3 I Ground

NOTES

Multiplexed pins, individually selectable through PORTA_SELECT and PORTA_DATA Registers.

SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL Register Bit 4.

prom reset signal.

Reluctance Mode

(DT1/FL1, DR1)

(DT0, DR0, RFS0, TFS0, SCLK1/ SCLK0

)

Output

Quart Crystal Connection Point

Outputs

Inputs

SENSE

Current Source

INTERRUPT OVERVIEW

The ADMCF340 can respond to 34 different interrupt sources with minimal overhead, seven of which are internal DSP core interrupts and 27 are from the motor control peripherals. The seven DSP core interrupts are SPORT1 receive (or IRQ0) and transmit (or IRQ1), SPORT0 receive and transmit, the internal timer, and two software interrupts. The motor control peripheral interrupts are the 25 programmable I/Os and two from the PWM (PWMSYNC pulse and PWMTRIP). All motor control interrupts are multiplexed into the DSP core through the peripheral IRQ2 interrupt. The interrupts are internally prioritized and individually maskable. A detailed description of the entire interrupt system of the ADMCF340 is presented later, following a more detailed description of each peripheral block.

MEMORY MAP

The ADMCF340 has two distinct memory types: program and data. In general, program memory contains user code and coefficients, while the data memory is used to store variables and data during program execution. Three kinds of program memory are provided on the ADMCF340: RAM, ROM, and FLASH. The motor control peripherals are memory mapped into a region of the data memory space starting at 0x2000. The complete program and data memory maps are given in Tables II and III, respectively.

Table II. Program Memory Map

Memory

Address Range Type Function

0x0000–0x002F RAM Internal Vector Table 0x0030–0x01FF RAM User Program Memory 0x0200–0x07FF Reserved 0x0800–0x17FF ROM Reserved Program Memory 0x1800–0x1FFF Reserved 0x2000–0x20FF FLASH User Program Memory

Sector 0

0x2100–0x21FF FLASH User Program Memory

Sector 1

0x2200–0x2FFF FLASH User Program Memory

Sector 2

0x3000–0x3FFF Reserved

Table III. Data Memory Map

Memory

Address Range Type Function

0x0000–0x1FFF Reserved 0x2000–0x20FF Memory Mapped Registers 0x2100–0x37FF Reserved 0x3800–0x39FF RAM User Data Memory 0x3A00–0x3BFF RAM Reserved 0x3C00–0x3FFF Memory Mapped Registers

–10–

REV. 0

ADMCF340

FLASH MEMORY SUBSYSTEM

The ADMCF340 has 4K × 24-bit of user-programmable, nonvolatile flash memory. A flash programming utility is provided with the development tools that performs the basic device programming operations: erase, program, and verify.

The flash memory array is portioned into three asymmetrically sized sectors of 256 words, 256 words, and 3,584 words, labeled Sector 0, Sector 1, and Sector 2, respectively. These sectors are mapped into external program memory address space.

Four flash memory interface registers are connected to the DSP. These 16-bit registers are mapped into the register area of data memory space. They are named Flash Memory Control Register (FMCR), Flash Memory Address Register (FMAR), Flash Memory Data Register Low (FMDRL), and Flash Memory Data Register High (FMDRH). These registers are diagrammed later in this data sheet. They are used by the flash memory programming utility. The user program may read these registers but should not modify them directly. The flash programming utility provides a complete interface to the flash memory.

Note: From the point of view of 2171 core, the flash memory is placed externally. It means the core accesses them through an external memory interface that multiplexes the program memory and data memory buses into a single external bus. Therefore, if more than one external transfer must be made in the same instruction, there will be at least an overhead cycle required. For more details, see Application Note ANF32X-65 Guidelines to Transfer Code from ADMCF32x to ADMC32x.

Special Flash Registers

The flash module has four nonvolatile 8-bit registers called Special Flash Registers (SFRs) that are accessible independently of the main flash array via the flash programming utility. These registers are for general-purpose, nonvolatile storage. When erased, the Special Flash Registers contain all “0s.” To read Special Flash Registers from the user program, call the read_reg routine contained in the ROM. Refer to the ADMCF34x DSP Motor Controller Developers’ Reference Manual for an example.

Boot-from-Flash Code

A security feature is available in the form of a code that when set causes the processor to execute the program in flash memory at power-up or reset. In this mode, the flash programming utility and debugger are unable to communicate with the ADMCF340. Consequently, the contents of the flash memory can be neither programmed nor read.

The boot-from-flash code may be set via the flash programming utility when the user’s program is thoroughly tested and loaded into flash program memory at Address 0x2200. The user’s program must contain a mechanism for clearing the boot-from-flash code if reprogramming the flash memory is desired. The only way to clear boot-from-flash is from within the user program, by calling the flash_init or auto_erase_reg routines that are included in the ROM. The user program must be signaled in some way to call the necessary routine to clear the boot-from-flash code. An example would be to detect a high level on a PIO pin during startup initialization and then call the flash_init or auto-erase-reg routine. The flash_init routine will erase the entire user program in

flash memory before clearing the boot-from-flash code, thus ensuring the security of the user program. If security is not a concern, the auto_erase_reg routine can be used to clear the boot-from-flash code while leaving the user program intact.

Refer to the ADMCF34x DSP Motor Controller Developers’ Reference Manual for further instructions and an example of using the boot-from-flash code.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execution at Address 0x0800 of internal program ROM. The ROM monitor program that is located there checks the boot-from-flash code. If that code is set, the processor jumps to location 0x2200 in external flash program memory, where it expects to find the user’s application program.

If the boot-from-flash code is not set, the monitor attempts to boot from an external device as described in the ADMCF34x

DSP Motor Controller Developers’ Reference Manual.

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMCF340 with an external crystal.

22pF

10MHz

22pF

Figure 4. Basic System Configuration

Clock Signals

CLKOUT

ADMCF340

RESET

XTAL

CLKIN

The ADMCF340 can be clocked either by a crystal or a TTL compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency. If an external clock is used, it should be a TTL compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMCF340. In this mode, with an external clock signal, the XTAL Pin must be left unconnected. The ADMCF340 uses an input clock with a frequency equal to half the instruction rate; a 10 MHz input clock yields a 50 ns processor cycle (which is equivalent to 20 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate that is indicated by the CLKOUT signal when enabled.

Because the ADMCF340 includes an on-chip oscillator feedback circuit, an external crystal may be used instead of a clock source, as shown in Figure 2. The crystal should be connected across the CLKIN and XTAL Pins with two capacitors (see Figure 2). A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output signal (CLKOUT) is generated by the processor at the processor’s cycle rate of twice the input frequency.

REV. 0

–11–

ADMCF340

Reset

The ADMCF340 DSP core and peripherals must be correctly reset when the device is powered up to assure proper unitization. The ADMCF340 contains an integrated power-on-reset (POR) circuit that provides a complete system reset on power-up and power-down. The POR circuit monitors the voltage on the ADMCF340 V in reset while V When this voltage is exceeded, the ADMCF340 is held in reset for an additional 2 this time (T

Pin and holds the DSP core and peripherals

is less than the threshold voltage level, V

DSP clock cycles (T

), the supply voltage must reach the recommended

RST

in Figure 5). During

RST

operating condition. On power-down, when the voltage on the

Pin falls below V

RST –VHYST

, the ADMCF340 will be

reset. Also, if the external RESET Pin is actively pulled low at any time after power-up, a complete hardware reset of the ADMCF340 is initiated.

RST

RESET

RST

HYST

–

Figure 5. Power-On Reset Operation

The ADMCF340 sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT Register, and performs a full reset of all the motor control peripherals. Following a power-up, it is possible to initiate a DSP core and motor control peripheral reset by pulling the RESET Pin low. The RESET signal must be the minimum pulsewidth specification,

. Following the reset sequence, the DSP core starts executing

RSP

code from the internal PM ROM located at 0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL, memorymapped at DM (0x3FFF). SPORT1 must be configured as a serial port by setting Bit 10. SPORT0 and SPORT1 are enabled by setting Bit 11 and Bit 12.

The DSP core has a wait state control register, MEMWAIT, memory-mapped at DM (0x3FFE). The default value of this register is 0xFFFF. For proper operation of the ADMCF340, this register must always contain the value 0x8000. This value sets the minimum access time to the program memory.

The configurations of both the SYSCNTL and MEMWAIT Registers of the ADMCF340 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER Overview

The PWM generator block of the ADMCF340 is a flexible, programmable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction motors (ACIM) or permanent magnet synchronous motors (PMSM). In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of electronically commutated motors (ECM), brushless dc motors (BDCM), or switched reluctance motors (SRM).

The six PWM output signals consist of three high side drive signals (AH, BH, and CH) and three low side drive signals (AL, BL, and CL). The switching frequency, dead time, and minimum pulsewidths of the generated PWM patterns are programmable using, respectively, the PWMTM, PWMDT, and PWMPD registers. In addition, three registers (PWMCHA, PWMCHB, and PWMCHC) control the duty cycles of the three pairs of PWM signals.

PWM CONFIGURATION

REGISTERS

PWMTM (15...0) PWMDT (9...0) PWMPD (9...0) PWMSYNCWT (7...0) MODECTRL (6)

THREE-PHASE

PWM TIMING

CLK RESETSYNC

PWMSYNC

TO INTERRUPT CONTROLLER

PWMTRIP

PWM DUTY CYCLE

REGISTERS

PWMCHA (15...0) PWMCHB (15...0) PWMCHC (15...0)

UNIT

PWMSEG (8...0)

OUTPUT

CONTROL

UNIT

SYNC

PWMSWT (0)

PWM SHUTDOWN CONTROLLER

PWMGATE (9...0)

CURRENT

Figure 6. Overview of the PWM Controller of the ADMCF340

GATE

DRIVE

UNIT

CLK

OVER

TRIP

CLKOUT

ANALOG BLOCK

AH AL BH

BL CH CL

PWMTRIP

SENSE1

SENSE2

SENSE3

–12–

REV. 0

ADMCF340

Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG Register. In addition, three control bits of the PWMSEG Register permit crossover of the two signals of a PWM.

In crossover mode, the high side PWM signals are diverted to the complementary low side output and low side signals are diverted to the corresponding high side output.

In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation techniques: optical isolation using optocouplers, and transformer isolation using pulse transformers. The PWM controller of the ADMCF340 permits mixing of the output PWM signals with a high frequency chopping signal to permit an easy interface to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMGATE Register. There is an 8-bit value within the PWMGATE Register that directly controls the chopping frequency. In addition, high frequency chopping can be independently enabled for the high side and the low side outputs using separate control bits in the PWMGATE Register.

The PWM generator is capable of operating in two distinct modes: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetrical about the midpoint of the PWM period. In the double update mode, a second updating of the PWM duty cycle values is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. This technique also permits the closed-loop controller to change the average voltage applied to the machine winding at a faster rate, allowing wider closed-loop bandwidths to be achieved. The operating mode of the PWM block (single or double update mode) is selected by a control bit in MODECTRL Register.

The PWM generator of the ADMCF340 also provides an internal signal that synchronizes the PWM switching frequency to the A/D operation. In single update mode, a PWMSYNC pulse is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The width of the PWMSYNC pulse is programmable through the PWMSYNCWT Register.

The PWM signals produced by the ADMCF340 can be shut off in a number of different ways. First, there is a dedicated asynchronous PWM shutdown pin, PWMTRIP, which when brought low, instantaneously places all six PWM outputs in the OFF state. In addition, PWM shutdown is initiated when the voltage on any of the three I

input pins exceeds the trip

SENSE

thresholds (high or low). Because these two hardware shutdown mechanisms are asynchronous, and the associated PWM disable circuitry does not use clocked logic, the PWM will shut down even if the DSP clock is not running. The PWM system may also be shut down from software by writing to the PWMSWT Register.

Status information about the PWM system of the ADMCF340 is available to the user in the SYSSTAT Register. In particular,

the status of PWMTRIP is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period.

A functional block diagram of the PWM controller is shown in Figure 6. The generation of the six output PWM signals on pins AH to CL is controlled by four important blocks:

• The three-phase PWM timing unit, that is the core of the PWM controller, generates three pairs of complemented and dead-time-adjusted center-based PWM signals.

• The output control unit allows the redirection of the outputs of the three-phase timing unit for each channel to either the high side or low side output. In addition, the output control unit allows individual enabling/disabling of each of the six PWM output signals.

• The GATE drive unit provides the high chopping frequency and its subsequent mixing with the PWM signals.

• The PWM shutdown controller manages the three PWM shutdown modes (via the PWMTRIP Pin, the analog block, or the PWMSWT Register) and generates the correct RESET signal for the Timing Unit.

• The PWM controller is driven by a clock at the same frequency as the DSP instruction rate, CLKOUT, and is capable of generating two interrupts to the DSP core. One interrupt is generated on the occurrence of a PWMSYNC pulse, and the other is generated on the occurrence of any PWM shutdown action.

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM controller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. There are four main configuration registers (PWMTM, PWMDT, PWMPD, and PWMSYNCWT) that determine the fundamental characteristics of the PWM outputs. In addition, the operating mode of the PWM (single or double update mode) is selected by Bit 6 of the MODECTRL Register. These registers, in conjunction with the three 16-bit duty cycle registers (PWMCHA, PWMCHB, and PWMCHC), control the output of the three-phase timing unit.

PWM Switching Frequency: PWMTM Register

The PWM switching frequency is controlled by the PWM period register, PWMTM. The fundamental timing unit of the PWM controller is T

= 1/f

CLKOUT

where f

CLKOUT

is the CLKOUT frequency (DSP instruction rate). Therefore, for a 20 MHz CLKOUT, the fundamental time increment is 50 ns. The value written to the PWMTM Register is effectively the number of T

clock increments in half a PWM period. The

required PWMTM value is a function of the desired PWM switching frequency (f

PWMTM

) and is given by:

PWM

CLKOUT

×=2

PWM

CLKIN

PWM

Therefore, the PWM switching period, TS, can be written as:

T PWMTM T

=× ×2

SCK

REV. 0

–13–

ADMCF340

For example, for a 20 MHz CLKOUT and a desired PWM switching frequency of 10 kHz (T

= 100 µs), the correct value

to load into the PWMTM Register is:

PWMTM x E=

20 10

××

21010

1000 0 3 8

The largest value that can be written to the 16-bit PWMTM Register is 0xFFFF = 65,535, which corresponds to a minimum PWM switching frequency of:

fHz

PWM,min

20 10

265535

153

for a CLKOUT frequency of 20 MHz.

PWM Switching Dead Time: PWMDT Register

The second important PWM block parameter that must be initialized is the switching dead time. This is a short delay time introduced between turning off one PWM signal (e.g., AH) and turning on its complementary signal (e.g., AL). This short time delay is introduced to permit the power switch being turned off to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short circuit condition from developing across the dc link capacitor of a typical voltage source inverter.

Dead time is controlled by the PWMDT Register. The dead time is inserted into the three pairs of PWM output signals. The dead time, T

, is related to the value in the PWMDT Register by:

T PWMDT T

=××=×22

DCK

PWMDT

CLKOUT

Therefore, a PWMDT value of 0x00A (= 10) introduces a 1 µs delay between the turn-off of any PWM signal (e.g., AH) and the turn-on of its complementary signal (e.g., AL). The amount of the dead time can therefore be programmed in increments of

(or 100 ns for a 20 MHz CLKOUT). The PWMDT Register

2 T

is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum value of 0x3FF (= 1023) corresponds to a maximum programmed dead time of:

=××

1023 2

DCKmax

=×××

1023 2 50 10

102

−

sec

The dead time can be programmed to zero by writing 0 to the PWMDT Register.

PWM Operating Mode: MODECTRL and SYSSTAT Registers

The PWM controller of the ADMCF340 can operate in two distinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL Register. If this bit is cleared, the PWM operates in the single update mode. Setting Bit 6 places the PWM in the double update mode. By default, following either a peripheral reset or power-on, Bit 6 of the MODECTRL Register is cleared. This means that the default operating mode is single update mode.

In single update mode, a single PWMSYNC pulse is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle and is used to latch new values from the PWM configuration registers (PWMTM, PWMDT, PWMPD, and PWMSYNCWT) and the PWM duty cycle registers (PWMCHA, PWMCHB, and PWMCHC) into the three-phase timing unit. The PWMSEG Register is also latched into the output control unit on the rising edge of the PWMSYNC pulse. In effect, this means that the parameters of the PWM signals can be updated only once per PWM period at the start of each cycle. Thus, the generated PWM patterns are symmetrical about the midpoint of the switching period.

In double update mode, there is an additional PWMSYNC pulse produced at the midpoint of each PWM period. The rising edge of this new PWMSYNC pulse is again used to latch new values of the PWM configuration registers, duty cycle registers, and the PWMSEG Register. As a result, it is possible to alter both the characteristics (switching frequency, dead time, minimum pulsewidth, and PWMSYNC pulsewidth) and the output duty cycles at the midpoint of each PWM cycle. Consequently, it is possible to produce PWM switching patterns that are no longer symmetrical about the midpoint of the period (asymmetrical PWM patterns).

In the double update mode, operation in the first half or the second half of the PWM cycle is indicated by Bit 3 of the SYSSTAT Register. In double update mode, this bit is cleared during operation in the first half of each PWM period (between the rising edge of the original PWMSYNC pulse and the rising edge of the new PWMSYNC pulse, which is introduced in double update mode). Bit 3 of the SYSSTAT Register is set during the second half of each PWM period. If required, a user may determine the status of this bit during a PWMSYNC interrupt service routine.

The advantages of the double update mode are that lower harmonic voltages can be produced by the PWM process and wider control bandwidths are possible. However, for a given PWM switching frequency, the PWMSYNC pulses occur at twice the rate in the double update mode. Because new duty cycle values must be computed in each PWMSYNC interrupt service routine, there is a larger computational burden on the DSP in the double update mode.

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF340 produces an internal PWM synchronization pulse at a rate equal to the PWM switching frequency in single update mode and at twice the PWM frequency in the double update mode. This PWMSYNC synchronizes the operation of the PWM unit with the A/D converter system. The width of this PWMSYNC pulse is programmable by the

PWMSYNCWT Register. The width of the PWMSYNC pulse, T

PWMSYNC

, is given by:

TTPWMSYNCWT

PWMSYNC CK

=× +

()

–14–

REV. 0

ADMCF340

TPWMCHA PWMDT T

TPWMTM PWMCHA PWMDT T

AH CK

AL CK

=× ×

22(–)

(– –)

which means that the width of the pulse is programmable from T

to 256 TCK (corresponding to 50 ns to 12.8 µs for a CLKOUT rate of 20 MHz). Following a reset, the PWMSYNCWT Register contains 0x27 (= 39) so that the default PWMSYNC width is 2.0 µs.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC Registers

The duty cycles of the six PWM output signals are controlled by the three duty cycle registers, PWMCHA, PWMCHB, and PWMCHC. The integer value in the register PWMCHA controls the duty cycle of the signals on AH and AL. PWMCHB controls the duty cycle of the signals on BH and BL, and PWMCHC controls the duty cycle of the signals on CH and CL. The duty cycle registers are programmed in integer counts of the fundamental time unit, T

and define the desired on-time of the high side

CK,

PWM signal produced by the three-phase timing unit over half the PWM period. The switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT Register.

The PWM is center-based. This means that in single update mode, the resulting output waveforms are symmetrical and centered in the PWMSYNC period. Figure 7 presents a typical PWM timing diagram illustrating the PWM-related registers’ (PWMCHA, PWMTM, PWMDT, and PWMSYNCWT) control over the waveform timing in both half cycles of the PWM period. The magnitude of each parameter in the timing diagram is determined by multiplying the integer value in each register by T

(typically

50 ns). It may be seen in the timing diagram how dead time is incorporated into the waveforms by moving the switching edges away from the original values set in the PWMCHA Register.

PWMCHA

2  PWMDT

PWMSYNC

SYSSTAT (3)

PWMTM

PWMCHA

2  PWMDT

PWMSYNCWT + 1

PWMTM

Each switching edge is moved by an equal amount (PWMDT × T

) to preserve the symmetrical output patterns. The

PWMSYNC pulse, whose width is set by the PWMSYNCWT Register, is also shown. Bit 3 of the SYSSTAT Register indicates which half cycle is active. This can be useful in double update mode, to be discussed later in this data sheet.

The resultant on-times of the PWM signals shown in Figure 5 may be written as:

The corresponding duty cycles are:

PWMCHA PWMDT

PWMTM PWMCHA PWMDT

–

PWMTM

––

PWMTM

Obviously, negative values of TAH and TAL are not permitted because the minimum permissible value is zero, corresponding to a 0% duty cycle. In a similar fashion, the maximum value is

, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in double update mode are shown in Figure 8. This illustrates a completely general case where the switching frequency, dead time, and duty cycle are all changed in the second half of the PWM period. Of course, the same value for any or all of these quantities could be used in both halves of the PWM cycle. However, it can be seen that there is no guarantee that symmetrical PWM signals will be produced by the timing unit in this double update mode. Additionally, it is seen that the dead time is inserted into the PWM signals in the same way as in the single update mode.

2  PWMDT

PWMCHA

2  PWMDT

Figure 7. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode

REV. 0

PWMSYNC

SYSSTAT (3)

PWMSYNCWT1 + 1

PWMTM

PWMSYNCWT2 + 1

PWMTM

Figure 8. Typical PWM Outputs of Three-Phase Timing Unit in Double Update Mode

–15–

ADMCF340

In general, the on-times of the PWM signals in double update mode are deﬁned by:

TAH = (PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2 ) × T

TAL = (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 –

PWMDT

– PWMDT2) × T

PWMCHA PWMCHA

PWMTM PWMTM

PWMDT PWMDT

−

PWMTM PWMTM

PWMTM PWMTM PWMCHA

()

PWMCHA PWMDT PWMDT

()

–

12 1

PWMTM PWMTM

212

because of the completely general case in double update mode, the switching period is given by:

T PWNMTM PWMTM T

()

SCK

Again, the values of TAH and TAL are constrained to lie between zero and T

PWM signals similar to those illustrated in Figure 7 and Figure 8 can be produced on the BH, BL, CH, and CL outputs by programming the PWMCHB and PWMCHC Registers in a manner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC Registers have been written to at least once. After these registers have been written, the counters in the three-phase timing unit are enabled. Writing to these registers also starts the main PWM timer. If during initialization, the PWMTM Register is written before the PWMCHA, PWMCHB, and PWMCHC Registers, the ﬁrst PWMSYNC pulse (and interrupt if enabled) will be generated (1.5 × T

× PWMTM) seconds after the initial write to the

PWMTM Register in single update mode. In double update mode, the ﬁrst PWMSYNC pulse will be generated (T

× PWMTM)

seconds after the initial write to the PWMTM Register in single update mode.

Effective PWM Resolution

In single update mode, the same values of PWMCHA, PWMCHB, and PWMCHC are used to deﬁne the on-times in both half cycles of the PWM period. As a result, the effective resolution of the PWM generation process is 2 T

(or 100 ns for a 20 MHz

CLKOUT) since incrementing one of the duty cycle registers by one changes the resultant on-time of the associated PWM signals

in each half period (or 2 TCK for the full period).

by T

In double update mode, improved resolution is possible since different values of the duty cycle registers are used to deﬁne the on-times in both the ﬁrst and second halves of the PWM period. As a result, it is possible to adjust the on-time over the whole period in increments of T PWM resolution of T

. This corresponds to an effective

in double update mode (or 50 ns for a

20 MHz CLKOUT).

Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340

16-BIT PWM TIMER

Parameter Min Typ Max Unit

Counter Resolution 16 Bits Edge Resolution (Single Update Mode) 100 ns Edge Resolution (Double Update Mode) 50 ns Programmable Dead Time Range 0 102 µs Programmable Dead Time Increments 100 ns Programmable Pulse Deletion Range 0 51 µs Programmable Pulse Deletion Increments 50 ns PWM Frequency Range 153 Hz PWMSYNC Pulsewidth (T

) 0.05 12.8 µs

CRST

Gate Drive Chop Frequency Range 0.02 5 MHz

–16–

REV. 0

ADMCF340

Table V. Achievable PWM Resolution in Single and Double Update Modes

Resolution Single Update Mode Double Update Mode (Bit) PWM Frequency (kHz) PWM Frequency (kHz)

8 39.1 78.1 9 19.5 39.1 10 9.8 19.5 11 4.9 9.8 12 2.4 4.9

Minimum Pulsewidth: PWMPD Register

In many power converter switching applications, it is desirable to eliminate PWM switching pulses shorter than a certain width. It takes a finite time to both turn on and turn off modern power semiconductor devices. Therefore, if the width of any of the PWM pulses is shorter than some minimum value, it may be desirable to completely eliminate the PWM switching for that particular cycle.

The allowable minimum on-time for any of the six PWM outputs for half a PWM period that can be produced by the PWM controller may be programmed using the PWMPD Register. The minimum on-time is programmed in increments of T

that the minimum on-time produced for any half PWM period,

, is related to the value in the PWMPD Register by:

MIN

T PWMPD T

=×

MIN CK

A PWMPD value of 0x002 defines a permissible minimum on-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-time of each of the six PWM signals. If any of the times are found to be less than the value specified by the PWMPD Register, the corresponding PWM signal is turned OFF for the entire half period, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5, PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz, while operating in single update mode. For this case, the PWM switching frequency is 50 kHz and the dead time is 300 ns. The minimum permissible on-time of any PWM signal over one-half of any period is 500 ns. Clearly, for this example, the dead time adjusted on-time of the AH signal for one-half a PWM period is (5 – 3) × 50 ns = 100 ns. Because this is less than the minimum permissible value, output AH of the timing unit will remain OFF (0% duty cycle). Additionally, the AL signal will be turned ON for the entire half period (100% duty cycle).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by the 9-bit read/write PWMSEG Register. This register sets two distinct features of the output control unit that are directly useful in the control of ECM or BDCM.

The PWMSEG Register contains three crossover bits, one for each pair of PWM outputs. Setting Bit 8 of the PWMSEG Register enables the crossover mode for the AH/AL pair of PWM signals; setting Bit 7 enables crossover on the BH/BL pair of PWM signals; and setting Bit 6 enables crossover on the CH/CL pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high side PWM signal from the timing unit (for example, AH) is diverted to the associated low side output of the output control unit so that the signal will ultimately appear at the AL Pin. Of course, the corresponding low side output of the timing unit is also diverted to the complementary high side output of the output control unit so that the signal appears at Pin AH. Following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of PWM signals.

The PWMSEG Register also contains six bits (Bits 0 to 5) that can be used to individually enable or disable each of the six PWM outputs. If the associated bit of the PWMSEG Register is set, the corresponding PWM output is disabled regardless of the value of the corresponding duty cycle register. This PWM output signal will remain in the OFF state as long as the corresponding enable/disable bit of the PWMSEG Register is set. The PWM output enable function gates the crossover function. After a reset, all six enable bits of the PWMSEG Register are cleared, thereby enabling all PWM outputs by default.

In a manner identical to the duty cycle registers, the PWMSEG is latched on the rising edge of the PWMSYNC signal so that changes to this register only become effective at the start of each PWM cycle in single update mode. In double update mode, the PWMSEG Register can also be updated at the midpoint of the PWM cycle.

In the control of an ECM, only two inverter legs are switched at any time, and often the high side device in one leg must be switched ON at the same time as the low side driver in a second leg. Therefore, by programming identical duty cycles for two PWM channels (for example, let PWMCHA = PWMCHB) and setting Bit 7 of the PWMSEG Register to crossover the BH/BL pair of PWM signals, it is possible to turn ON the high side switch of Phase A and the low side switch of Phase B at the same time. In the control of an ECM, one inverter leg (Phase C in this example) is disabled for a number of PWM cycles. This disable may be implemented by disabling both the CH and CL PWM outputs by setting Bits 0 and 1 of the PWMSEG Register. This is illustrated in Figure 7, where it can be seen that both the AH and BL signals are identical, because PWMCHA = PWMCHB, and the crossover bit for Phase B is set. In addition, the other four signals (AL, BH, CH, and CL) have been disabled by setting the appropriate enable/disable bits of the PWMSEG Register. For the situation illustrated in Figure 9, the appropriate value for the PWMSEG Register is 0x00A7. In ECM operation, because each inverter leg is disabled for a certain period of time, the PWMSEG Register is changed based upon the position of the rotor shaft (motor commutation).

REV. 0

–17–

ADMCF340

PWMCHA = PWMCHB

2  PWMDT

PWMTM PWMTM

2  PWMDT

Figure 9. An example of PWM signals suitable for ECM control. PWMCHA = PWMCHB, BH/BL are a crossover pair. AL, BH, CH, and CL outputs are disabled. Operation is in single update mode.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that simplify the design of isolated gate drive circuits for PWM inverters. If a transformer-coupled power device gate drive amplifier is used, the active PWM signal must be chopped at a high frequency. The PWMGATE Register allows the programming of this high frequency chopping mode. The chopped active PWM signals may be required for the high side drivers only, for the low side drivers only, or for both the high side and low side switches. Therefore, independent control of this mode for both high side and low side switches is included with two separate control bits in the PWMGATE Register.

Typical PWM output signals with high frequency chopping enabled on both high side and low side signals are shown in Figure 10. Chopping of the high side PWM outputs (AH, BH, and CH) is enabled by setting Bit 8 of the PWMGATE Register. Chopping of the low side PWM outputs (AL, BL, and CL) is enabled by setting Bit 9 of the PWMGATE Register. The high chopping frequency is controlled by the 8-bit word (GDCLK) written to Bits 0 to 7 of the PWMGATE Register. The period and the frequency of this high frequency carrier are:

T GDCLK T

=× +

CHOP CK

CHOP

()

[]

CLKOUT

GDCLK

×+

()

[]

The GDCLK value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 19.5 kHz to 5 MHz for a 20 MHz CLKOUT rate. The gate drive features must be programmed before operation of the PWM controller and typically are not changed during normal operation of the PWM controller. Following a reset, by default, all bits of the PWMGATE Register are cleared so that high frequency chopping is disabled.

PWMCHA PWMCHA

2  PWMDT

[4  (GDCLK + 1) 

PWMTM

]

2  PWMDT

PWMTM

Figure 10. Typical PWM signals with high frequency gate chopping enabled on both high side and low side switches. (GDCLK is the integer equivalent of the value in Bits 0 to 7 of the PWMGATE Register.)

PWM Polarity Control, PWMPOL Pin

The polarity of the PWM signals produced at the output pins AH to CL may be selected in hardware by the PWMPOL Pin. Connecting the PWMPOL Pin to DGND selects active LO PWM outputs, such that a LO level is interpreted as a command to turn on the associated power device. Conversely, connecting the PWMPOL Pin to V

selects active HI PWM and the asso-

ciated power devices are turned ON by a HI level at the PWM outputs. There is an internal pull-up on the PWMPOL Pin, so that if this pin becomes disconnected (or is not connected), active HI PWM will be produced. The level on the PWMPOL Pin may be read from Bit 2 of the SYSSTAT Register, where a zero indicates a measured LO level at the PWMPOL Pin.

–18–

REV. 0

ADMCF340

SWITCHED RELUCTANCE MODE

The PWM block of the ADMCF340 contains a switched reluctance (SR) mode that is controlled by the PWMSR Pin. The switched reluctance mode is enabled by connecting the PWMSR Pin to DGND. In this SR Mode, the low side PWM signals from the three-phase timing unit assume permanently ON states, independent of the value written to the duty-cycle registers. The duty cycles of the high side PWM signals from the timing unit are still determined by the three duty cycle registers. Using the crossover feature of the output control unit, it is possible to divert the permanently ON PWM signals to either the high side or low side outputs. This mode is necessary because in the typical power converter configuration for switched or variable reluctance motors, the motor winding is connected between the two power switches of a given inverter leg. Therefore, in order to build up current in the motor winding, it is necessary to turn on both switches at the same time. Typical active LO PWM signals during operation in SR Mode are shown in Figure 8 for operation in double update mode. It is clear that the three low side signals (AL, BL, and CL) are permanently ON and the three high side signals are modulated in the usual manner so that the corresponding high side power switches are switched between the ON and OFF states. The SR Mode can only be enabled by connecting the PWMSR Pin to GND. There are no software means by which this mode can be enabled. There is an internal pull-up resistor on the PWMSR Pin so that if this pin is left unconnected or becomes disconnected the SR Mode is disabled. Of course, the SR Mode is disabled when the PWMSR Pin is tied to V

PWM Shutdown

In the event of external fault conditions, it is essential that the PWM system be instantaneously shut down. Two methods of sensing a fault condition are provided by the ADMCF340. For the ﬁrst method, a low level on the PWMTRIP Pin initiates an instantaneous, asynchronous (independent of DSP clock) shutdown of the PWM controller. This places all six PWM outputs in the OFF state, disables the PWMSYNC pulse and associated interrupt signal, and generates a PWMTRIP interrupt signal. The PWMTRIP Pin has an internal pull-down resistor so that even if the pin becomes disconnected, the PWM outputs will be disabled. The state of the PWMTRIP Pin can be read from Bit 0 of the SYSSTAT Register.

The second method for detecting a fault condition is through the

pins of the analog block of the ADMCF340. When the

SENSE

voltage at any of the I

pins exceeds the trip threshold

SENSE

(high or low), PWMTRIP will be internally pulled low. The negative edge of the internal PWMTRIP will generate a shutdown in the same manner as a negative edge on pin PWMTRIP.

In addition, it is possible through software to initiate a PWM shutdown by writing to the 1-bit read/write PWMSWT Register (0x2061). Writing to this bit generates a PWM shutdown in a manner identical to the PWMTRIP or I

pins. Following

SENSE

a PWM shutdown, it is possible to determine if the shutdown was generated from hardware or software by reading the same PWMSWT Register. Reading this register also clears it.

Restarting the PWM after a fault condition is detected requires clearing the fault and reinitializing the PWM. Clearing the fault requires that PWMTRIP returns to a HI state. After the fault has been cleared, the PWM can be restarted by writing to registers PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the fault is cleared and the PWM Registers are initialized, internal timing of the three-phase timing unit will resume, and the new duty cycle values will be latched on the next rising edge of PWMSYNC.

PWM Registers

The conﬁguration of the PWM Registers is described at the end of the data sheet. The parameters of the PWM block are tabulated in Table IV.

ADC OVERVIEW

The ADC of the ADMCF340 is based upon the single slope conversion technique. This approach offers an inherently monotonic conversion process within the noise and stability of its components, and there will be no missing codes.

The single slope technique has been adopted on the ADMCF340 for four channels that are simultaneously converted. Refer to Figure 11 for the functional schematic of the ADC. The main inputs (V1, V2, and V3) are directly connected to the ADC converter through three front end blocks. Figure 14 shows the block diagram of a single front end block. Each front end block has a bipolar current amplifier (gain = –2.5) designed to acquire the voltage on a current-sensing resistor, whose voltage can be either positive or negative with respect to the power supply ground rail.

The fourth channel has been configured with a serially connected 8-to-1 multiplexer. Table VI shows the multiplexer input selection codes. One of these auxiliary multiplexed channels is used to acquire the internal voltage reference (V

) for calibration purpose.

REF

REV. 0

–19–

ADMCF340

VOLTAGE

CURRENT

VOLTAGE

CURRENT

VOLTAGE

CURRENT

VAUX0

VAUX1

VAUX2

VAUX4

VAUX5

VAUX6

VAUX7

ICONST

VAUX0 (V)

VAUX1 (V)

VAUX2 (V)

VAUX4 (V)

VAUX5 (V)

VAUX6 (V)

VAUX7 (V)

VAUX3 (V)

REF

CAPACITOR EXTERNALCHARGING

MODECTRL REG

<09..10..11>

CHANNEL1

CHANNEL2

CHANNEL3

8-1

MULTIPLEXER

MODECTRL REG <0..1>

ICONST

COMP

CAPACITOR

RESET

PWMSYNC (CONVST)

Figure 11. ADC Overview

ICONST_TRIM

REG <2:0>

FILTER

ADC

REGISTERS

PWMTRIP

MODECTRL

REG <07>

CLK

12-BIT

ADC

TIMER

BLOCK

VAUX

ADC1 ADC2 ADC3

ADCAUX

Single Slope ADC Operations

Comparing each ADC input to a reference ramp voltage and timing the comparison of the two signals performs the conversion process. The actual conversion point is the time point intersection of the input voltage and the ramp voltage (V

) as shown in

Figure 12. This time is converted to counts by the 12-bit ADC Timer Block and is stored in the ADC registers. The ramp voltage used to perform the conversion is generated by driving a fixed current into an off-chip capacitor, where the capacitor voltage is:

VICt

×/

()

Following reset, VC = 0 at t = 0. This reset and the start of the conversion process are initiated by the PWMSYNC pulse, as shown in Figure 12. The width of the PWMSYNC pulse is controlled by the PWMSYNCWT Register and should be programmed according to Figure 12 to ensure complete resetting.

In order to compensate for IC process manufacturing tolerances (and to adjust for capacitor tolerances), the current source of the ADMCF340 is software programmable. The software setting of the magnitude of the ICONST current generator is accomplished by selecting one of eight steps over approximately 20% current range.

Table VI. ADC Auxiliary Channel Selection

MODECTRL(5) MODECTRL(1) MODECTRL(0)

Select ADCMUX ADCMUX1 ADCMUX0

VAUX0 0 0 0 VAUX1 0 0 1 VAUX2 0 1 0 VAUX3 Calibration (V

)0 1 1

REF

VAUX4 1 0 0 VAUX5 1 0 1 VAUX6 1 1 0 VAUX7 1 1 1

Table VII. Port A Multiplexing

PORTA Pin First Alternate Function (Peripheral) Second Alternate Function (Peripheral)

PORTA8 AUX0 (Auxiliary PWM Output) CLKOUT (System CLOCK) PORTA7 AUX1 (Auxiliary PWM Output) PWMSYNC (PWM) PORTA6 DR1 (Data Receive SPORT1) None PORTA5 FL1 (Flag Out SPORT1) DT1 (Data Transmit SPORT1) PORTA4 SCLK1 (Serial Clock SPORT1) SCLK0 (Serial Clock SPORT0) PORTA3 TFS0 (Transmit Frame Sync SPORT0) None PORTA2 RFS0 (Receive Frame Sync SPORT0) None PORTA1 DT0 (Data Transmit SPORT0) None PORTA0 DR0 (Data Receive SPORT0) None

–20–

REV. 0

VIL

PWMSYNC

COMPARATOR

OUTPUT

VIL

– T

PWM

CRST

CMAX

CRST

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single timer that may be clocked at either the DSP rate or half the DSP rate, depending on the setting of the ADCCNT bit (Bit 7) of the MODECTRL Register. When this bit is cleared, the timer counts at a slower rate of CLKIN. When this bit is set, the timer counts at CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3, and ADCAUX are the registers that capture the conversion times, which are the timer values when the associated comparator trips.

100

– nF

NOM

DEFAULT I

1 10 100

CONST

TUNED I

CONST

Figure 13. Timing Capacitor Selection

ADC Resolution

The ADC is intrinsically linked to the PWM block through the PWMSYNC pulse controlling the ADC conversion process. Because of this link, the effective resolution of the ADC is a function of both the PWM switching frequency and the rate at which the ADC counter timer is clocked. For a CLKOUT period of T

and a PWM period of T

, the maximum count

PWM

of the ADC is given by:

Max Count T T T

Where T

PWM

=−

min , /

4095 2

()

for MODECTRL Bit

4095

=−

min , /

()

for MODECTRL Bit

PWM CRST CK

()

PWM CRST CK

is equal to the PWM period if operating in single update mode, or it is equal to half that period if operating in double update mode. For an assumed CLKOUT frequency of

REV. 0

–21–

ADMCF340

20 MHz and PWMSYNC pulsewidth of 2.0 µs, the effective resolution of the ADC block is tabulated for various PWM switching frequencies in Table VIII.

Table VIII. ADC Resolution Examples

PWM MODECTRL[7] = 0 MODECTRL[7] = 1 Frequency Max Effective M ax Effective (kHz) Count Resolution Count Resolution

2.4 4095 12 4095 12 4 2480 >11 4095 12 8 1230 >10 2460 >11 18 535 >9 1070 >10 25 380 >8 760 >9

Programmable Current Source

The ADMCF340 has an internal current source that is used to charge an external capacitor, generating the voltage ramp used for conversion. The magnitude of the output of the current source circuit is subject to manufacturing variations and can vary from one device to the next. Therefore, the ADMCF340 includes a programmable current source whose output can always be tuned to within 5% of the target 100 µA. A 3-bit register, ICONST_TRIM, allows the user to make this adjustment. The output current is proportional to the value written to the register: 0x0 produces the minimum output, and 0x7 produces the maximum output. The default value of ICONST_TRIM after reset is 0x0.

Suggested implementations of the calibration routine are provided through Application Notes and code that can be found by visiting www.analog.com/motorcontrol.

Charging Capacitor Selection

The charging capacitor value is selected based on the sample (PWM) frequency desired. Too small a capacitor value will reduce the available resolution of the ADC by having the ramp voltage rise rapidly and convert too quickly, not utilizing all possible counts available in the PWM cycle. Too large a capacitor may not convert in the available PWM cycle returning 0x000. To select a charging capacitor, use Figure 13, select the sampling frequency desired, determine if the current source is to be tuned to a nominal 100 µA or left in the default (0x0 code) trim state, then determine the proper charge capacitor off the appropriate curve.

VOLTAGE

TRIP REF HIGH

TRIP REF LOW

CURRENT

PWMSYNC

CLOCKOUT

MODECTRL REGISTER CHANNEL SELECTION (I

SHA TIMER

COUNTER

SHA TIMER

OVERCURRENT

COMPARATOR

–25x

/V)

SENSE

SHA

STATE

MACHINE

ADC CONVERSION

SHA

STATUS BIT

(ADC REGISTER)

Figure 14. Analog Front End Block Diagram

TRIP

(TO PWMTRIP FILTER)

VxL

MUX

(TO ADC)

ADMCF340

Analog Front End

The main analog inputs of the ADMCF340 (I I

are connected to the ADC converter through three

SENSE

1 through

front end blocks. Figure 14 shows the block diagram of a single analog front end.

Each analog front end has two analog inputs: voltage and current. A 2-to-1 multiplexer selects which input will be converted; the multiplexer selection is determined by the MODECTRL Register.

The current input (I

) is amplified through a bipolar amplifier

SENSE

(Gain –2.5). There is an output offset that matches the amplifier output signal range to the input signal range of the A/D converter. The amplifier has a built-in over current and open circuit protection. The over current protection shuts down the PWM block when the voltage at any of the I

pins exceeds the trip thresh-

SENSE

old (high or low). The open-circuit protection shuts down the PWM block when any of the I

inputs is in high impedance

SENSE

(for example the current sense resistor or the current transducer is disconnected). The shut-down signals generated by the amplifiers are then OR-ed and filtered in order to avoid spurious trip caused by the switching of the power devices. The amplifier is followed by a sample-and-hold amplifier (SHA). The SHA time is user-programmable through the SHA Timer Register. The sampling time is set as a delay from the rising edge of the PWMSYNC signal and is calculated as:

T SHA CNT T

SAMPLE CK

()

×_2

The SHA Timer Counter has a minimum reload value of 0x0003, which ensures a minimum settling time of the SHA output in case the user is programming the SHA Timer Register to a value smaller than 0x0003. This means that the sampling time is programmable from 5 T

to 65535 T

(corresponding to 250 ns to

3.28 ms for a CLKOUT rate of 20 MHz). The sampling time, however, is limited to the rising edge of the following PWMSYNC

cycle. Each channel has an independent amplifier, SHA, and SHA timing unit/state machine. Figure 15 shows a conversion sequence of a single channel.

At the beginning of the cycle N (rising edge of PWMSYNC signal (1)), the Timer Counter is loaded with the value contained in the SHA_CNT Register. After the Timer Counter has been reloaded, it starts counting down at the CLKOUT rate; in this phase the SHA state-machine forces the SHA in TRACK (sample) status.

When the counter reaches the value of 0x0000 (after the time T

from the rising edge of PWMSYNC), the SHA state-

SAMPLE

machine forces the SHA in HOLD status.

The conversion of the sampled value is then taking place in the cycle N + 1 (from (4) to (5)) in Figure 16 and the result of the conversion is available on the ADC Register at the cycle N + 2 (rising edge of PWMSYNC (5)).

On cycle N + 2, the reload value of the Timer Counter exceeds the period of the PWMSYNC signal. In this case the SHA state machine forces the SHA in HOLD status at the rising edge of PWMSYNC of the next cycle (7). The conversion then takes place on cycle N + 3 and the conversion result is available on the ADC Register at the cycle N + 4 (rising edge of PWMSYNC (9)).

During the acquire phase (the PWMSYNC cycle during the sampling of the input value) the conversion takes place. However, the value on the ADC Register is not considered valid. This condition is signaled by the ADC by setting the LSB of the ADC Register to high.

On cycle N + 4, at the rising edge of the PWMSYNC signal (9), the Timer Counter is reloaded with a value smaller than the PWMSYNC pulsewidth. In this case the SHA samples within the PWMSYNC pulsewidth and the conversion takes place in the same PWMSYNC cycle (from (10) to (11)).

CYCLE

PWMSYNC

SHA TIMER

COUNTER

SHA STATUS

ISENSE INPUT

ADC REGISTER

1 2 3 4 5 6 7 8 9 10 11 12

N – 1 N N + 1 N + 2 N + 3

SAMPLE

X T H T H H T H

DATA READY SAMPLED ON

CYCLE N – 2

INVALID LSB = 1

DATA READY SAMPLED ON

CYCLE N

SAMPLE

TRACK

INVALID

LSB = 1

N + 4 N + 5

SAMPLE

DATA READY SAMPLED ON

CYCLE N + 2

DATA READY SAMPLED ON

Figure 15. ADC Conversion Sequence of a Current Input

–22–

CYCLE N + 4

REV. 0

ADMCF340

AUXPWM

R1 R2

C1 C2

R1 = R2 = 13k C1 = C2 = 10nF

Table IX. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF340

Parameter Test Conditions Min Typ Max Unit

Resolution 16 Bits PWM Frequency 10 MHz CLKIN 0.152 MHz

AUXILIARY PWM TIMERS Overview

The ADMCF340 provides two variable frequency, variable duty cycle, 16-bit, auxiliary PWM outputs that are available at the AUX1 and AUX0 Pins. When enabled, these auxiliary PWM outputs can be used to provide switching signals to other circuits in a typical motor control system such as power factor corrected front-end converters or other switching power converters. Alternatively, by addition of a suitable filter network, the auxiliary PWM output signals can be used as simple single-bit digital-to-analog converters, which is shown in Figure 16. The auxiliary PWM system of the ADMCF340 can operate in two different modes: independent mode or offset mode. The operating mode of the auxiliary PWM system is controlled by Bit 8 of the MODECTRL Register. Setting Bit 8 of the MODECTRL Register places the auxiliary PWM system in the independent mode. In this mode, the two auxiliary PWM generators are completely independent and separate switching frequencies and duty cycles may be programmed for each auxiliary PWM output. In this mode, the 16-bit AUXTM0 Register sets the switching frequency of the signal at the AUX0 output pin. Similarly, the 16-bit AUXTM1 Register sets the switching frequency of the signal at the AUX1 pin. The fundamental time increment for the auxiliary PWM outputs is twice the DSP instruction rate (or 2 T

) and the

corresponding switching periods are given by:

T AUXTM T

201

=× +

AUX CK

()

211

=× +

()

Since the values in both AUXTM0 and AUXTM1 can range from 0 to 0xFFFF, the achievable switching frequency of the auxiliary PWM signals may range from 152.59 Hz to 10 MHz for a CLKOUT frequency of 20 MHz. The on-time of the two auxiliary PWM signals is programmed by the two 16-bit AUXCH0 and AUXCH1 Registers, according to:

T AUX AUXCH T

ON, CK

T AUX AUXCH T

ON, CK

02 0

=×

()

12 1

=×

()

so that output duty cycles from 0% to 100% are possible. Duty cycles of 100% are produced if the on-time value exceeds the period value. Typical auxiliary PWM waveforms in independent mode are shown in Figure 17(a). When Bit 8 of the MODECTRL Register is cleared, the auxiliary PWM channels are placed in offset mode. In offset mode, the switching frequency of the two signals on the AUX0 and AUX1 Pins are identical and controlled by AUXTM0 in a manner similar to that previously described for independent mode. In addition, the on times of both the AUX0 and AUX1 signals are controlled by the AUXCH0 and AUXCH1 Registers as before.

However in this mode, the AUXTM1 Register defines the offset time from the rising edge of the signal on the AUX0 Pin to that on the AUX1 Pin according to:

T AUXTM T

=× +

OFFSET CK

()

×211

For correct operation in this mode, the value written to the AUXTM1 Register must be less than the value written to the AUXTM0 Register. Typical auxiliary PWM waveforms in offset mode are shown in Figure 17(b). Again, duty cycles from 0% to 100% are possible in this mode.

In both operating modes, the resolution of the auxiliary PWM system is 16 bits only at the minimum switching frequency (AUXTM0 = AUXTM1 = 65535 in independent mode, AUXTM0 = 65535 in offset mode). Obviously, as the switching frequency is increased, the resolution is reduced.

Values can be written to the auxiliary PWM Registers at any time. However, new duty cycle values written to the AUXCH0 and AUXCH1 Registers only become effective at the start of the next cycle. Writing to the AUXTM0 or AUXTM1 Registers causes the internal timers to be reset to 0 and new PWM cycles to begin. By default following a reset, Bit 8 of the MODECTRL Register is cleared, thus enabling offset mode. In addition, the registers AUXTM0 and AUXTM1 default to 0xFFFF, corresponding to the minimum switching frequency and zero offset. The on-time registers AUXCH0 and AUXCH1 default to 0x0000.

Figure 16. Auxiliary PWM Output Filter

Auxiliary PWM Interface, Registers and Pins

The registers of the auxiliary PWM system are summarized at the end of the data sheet.

2  AUXCH0

AUX0

2  AUXCH1

AUX1

2  (AUXTM0 + 1)

2  (AUXTM1 + 1)

2  AUXCH1

(a) Independent Mode

REV. 0

–23–

ADMCF340

2  AUXCH0

AUX0

AUX1

2  (AUXTM1 + 1)

Figure 17. Typical Auxiliary PWM Signals (All Times in Increments of T

WATCHDOG TIMER

)

The ADMCF340 incorporates a watchdog timer that can perform a full reset of the DSP and motor control peripherals in the event of software error. The watchdog timer is enabled by writing a timeout value to the 16-bit WDTIMER Register. The timeout value represents the number of CLKIN cycles required for the watchdog timer to count down to zero. When the watchdog timer reaches zero, a full DSP core and motor control peripheral reset is performed. In addition, Bit 1 of the SYSSTAT Register is set so that after a watchdog reset, the ADMCF340 can determine that the reset was due to the timeout of the watchdog timer and not an external reset. Following a watchdog reset, Bit 1 of the SYSSTAT Register may be cleared by writing zero to the WDTIMER Register. This clears the status bit but does not enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled when the first timeout value is written to the WDTIMER Register. To prevent the watchdog timer from timing out, the user must write to the WDTIMER Register at regular intervals (shorter than the programmed WDTIMER period value). On all but the first write to WDTIMER, the particular value written to the register is unimportant, since writing to WDTIMER simply reloads the first value written to this register.

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF340 has 25 programmable digital input/output (PIO) pins. These pins are organized in two separate ports: PORTA (nine pins) and PORTB (16 pins).

The nine pins of PORTA are multiplexed with other on-chip peripheral functions. PORTB has 16 pins that are dedicated to the digital I/O function only.

Each bit of PORTA can be individually selected as PIO or the alternate function through PORTA_SELECT Register. Bit 0 of PORTA_SELECT controls the operation of the PA0 Pin, Bit 1 controls the operation of PA1 and so on. Setting the appropriate bit in the PORTA_SELECT Register causes the corresponding pin to be configured as PIO. Clearing the bit selects the alternate function of the corresponding pin. Following a power-on or reset, all bits of PORTA_SELECT are set such that PIO functionality is selected. The second alternate function of PA7 is selected by Bit 14 of the PORTA_SELCT Register. The second alternate function of PA8 is selected by Bit 15 of PORTA_SELECT Register. The second alternate function of PA4 and PA5 is selected by Bit 4 of MODECTRL Register (SPORT1 Mode: Boot/UART).

2  (AUXTM0 + 1)

2  AUXCH1

(b) Offset Mode

When a pin is operating as PIO, its direction can be set through the corresponding bit of the data direction register (PORTA_DIR or PORTB_DIR).

Clearing any bit of the data direction register configures the corresponding PIO as input while setting the bit configures the PIO as output.

Following a power-on or reset, all bits or PORTA_DIR and PORTB_DIR are cleared, configuring all the PIO lines as inputs.

The data of the PIOs is controlled by the data registers (PORTA_DATA and PORTB_DATA). These registers can be used to read data from those PIOs configured as input and write data to those configured as outputs.

Each PIO can be individually programmed to be an interrupt source by setting the corresponding bit of the interrupt enable register (PORTA_INTEN and PORTB_INTEN). To generate an interrupt, the corresponding bit on the data register (PORTA_DATA and PORTB_DATA) must change state (high-to-low or low-to-high transition). The transition can be on the corresponding pin (PIO configured as input) or by writing into the corresponding bit of the data register (PIO configured as output).

Following a change of state on the data register on a PIO configured as interrupt source the corresponding bit is set in the flag register (PORTA_FLAG and PORTB_FLAG) and a common PIO interrupt is generated.

Reading the flag register is possible to determine which PIO has generated the interrupt. Reading the flag register automatically clears all the bits of the register. Following a power-on or reset, all bits of the interrupt enable registers are cleared (no interrupt enabled).

Each PIO line has an internal pull-down resistor so that following a power-on or reset all the PIO lines will be read as logic lows if left unconnected.

Once a pin has been selected as PIO function, it can be set as input, output, and interrupt source (either configured as input or output).

PIO Registers

The configuration of all registers of the PIO system is shown at the end of the data sheet.

INTERRUPT CONTROL

The ADMCF340 can respond to 34 different interrupt sources with minimal overhead. Seven of these interrupts are internal DSP core interrupts and 27 are from the on-chip peripherals. The seven DSP core interrupts are SPORT0 receive and transmit, SPORT1 receive (or IRQ0 ) and transmit (or IRQ1), the internal timer, and two software interrupts. The Motor Control interrupts are the 25 PIOs and two from the (PWMSYNC pulse and PWMTRIP). All the on-chip

PWM block

peripherals

interrupts are multiplexed into the DSP core via the peripheral IRQ2 interrupt. They are also internally prioritized and individually maskable. The start address in the interrupt vector table for the ADMCF340 interrupt sources is shown in Table X. The interrupts are listed from high priority to the lowest priority. The PWMSYNC interrupt is triggered by a low-to-high transition on the PWMSYNC pulse. The PWMTRIP to-low transition on the PWMTRIP

interrupt is triggered on a high-

pin. A PIO interrupt is detected

on any change of state (high-to-low or low-to-high) on the PIO lines.

–24–

REV. 0

ADMCF340

The entire interrupt control system of the ADMCF340 is configured and controlled by the IFC, IMASK, and ICNTL Registers of the DSP core and the IRQFLAG Register for the PWMSYNC and PWMTRIP interrupts and PORTA_FLAG Register for the PIO interrupts.

Table X. Interrupt Vector Addresses

Interrupt Source Interrupt Vector Address

PWMTRIP 0x002C (Highest Priority) Peripheral Interrupt (IRQ2) 0x0004 PWMSYNC 0x000C PIO 0x0008 Software Interrupt 1 0x0018 Software Interrupt 0 0x001C SPORT0 Transmit Interrupt 0x0010 SPORT0 Receive Interrupt 0x0014 SPORT1 Transmit Interrupt (or IRQ1) 0x0020 SPORT1 Receive Interrupt (or IRQ0) 0x0024 Timer 0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK Register of the DSP core. This register contains individual bits that must be set to enable the various interrupt sources. If any peripheral interrupt is to be enabled, the IRQ2 interrupt enable bit (Bit 9) of the IMASK Register must be set. The configuration of the IMASK Register of the ADMCF340 is shown at the end of the data sheet.

Interrupt Configuration

The IFC and ICNTL Registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC Register is a 16-bit register that may be used to force and/or clear any of the eight DSP interrupts. Bits 0 to 7 of the IFC Register may be used to clear the DSP interrupts while Bits 8 to 15 can be used to force a corresponding interrupt. Writing to Bits 11 and 12 in IFC is the only way to create the two software interrupts. The ICNTL Register is used to configure the sensitivity (edge or level) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/ disable interrupt nesting. Setting Bit 0 of ICNTL configures the IRQ0 as edge-sensitive, while clearing the bit configures it for level-sensitive. Bit 1 is used to configure the IRQ1 interrupt and Bit 2 is used to configure the IRQ2 interrupt. It is recommended that the IRQ2 interrupt always be configured for level-sensitive as this ensures that no peripheral interrupts are lost. Setting Bit 4 of the ICNTL Register enables interrupt nesting. The configuration of both IFC and ICNTL Registers is shown at the end of the data sheet.

INTERRUPT OPERATION

Following a reset, the ROM code on the ADMCF340 must copy a default interrupt vector table into program memory RAM from address 0x0000 to 0x002F. Since each interrupt source has a dedicated four word space in this vector table, it is possible to code short interrupt service routines (ISR) in place. Alternatively, it may be necessary to insert a JUMP instruction to the appropriate start address of the interrupt service routine if more memory is required for the ISR. When an interrupt occurs, the program sequencer ensures that there is no latency (beyond synchronization delay) when processing unmasked interrupts. In the case of the Timer, SPORT0, SPORT1 and software interrupts,

the interrupt controller automatically jumps to the appropriate location in the interrupt vector table. At this point, a JUMP instruction to the appropriate ISR is required. Motor control peripheral interrupts are slightly different. When a peripheral interrupt is detected, a bit is set in the IRQFLAG Register for PWMSYNC and PWMTRIP or in the PORTA_FLAG Register for a PIO interrupt, and the IRQ2 line is pulled low until all pending interrupts are acknowledged. The DSP software must determine the source of the interrupts by reading IRQFLAG register. If more than one interrupt occurs simultaneously, the higher priority interrupt service routine is executed. Reading the IRQFLAG Register clears the PWMTRIP and PWMSYNC bits and acknowledges the interrupt, thus allowing further interrupts when the ISR exits. A user’s PIO interrupt service routine must read the PORTA_FLAG Register to determine which PIO port is the source of the interrupt. Reading register PORTA_FLAG clears all bits in the registers and acknowledges the interrupt, thus allowing further interrupts after the ISR exits. The configuration of all these registers is shown at the end of the data sheet.

SYSTEM CONTROLLER

The system controller block of the ADMCF340 performs the following functions:

1. Manages the interface and data transfer between the DSP core and the motor control peripherals

2. Handles interrupts generated by the motor control peripherals and generates a DSP core interrupt signal IRQ2

3. Controls the ADC multiplexer select lines

4. Enables PWMTRIP and PWMSYNC interrupts

5. Controls the multiplexing of the SPORT1 and SPORT0 pins

6. Controls the PWM single/double update mode

7. Controls the ADC conversion time modes and the SHA timers

8. Controls the auxiliary PWM operation mode

9. Contains a status register (SYSSTAT) that indicates the state of the PWMTRIP Pin, the watchdog timer, and the PWM timer

10. Performs a reset of the motor control peripherals and control registers following a hardware, software, or watchdog initiated reset

SPORT1 and SPORT0 Control

The ADMCF340 has two serial ports: SPORT0 and SPORT1. SPORT1 is available with a limited number of pins and is mainly intended as a secondary port for Development Tools interfacing and/or for Code Booting from an external serial memory. Figure 18 shows the internal multiplexing of the SPORT0 and SPORT1 signals. SPORT0 is intended as general-purpose communication port. SPORT0 can support the following operating modes: SPORT, UART, and SPI.

SPORT1 Configuration

There are two operating modes for SPORT1: Boot Mode and UART Mode. These modes are selectable through Bit 4 of MODECTRL Register. With SPORT1 in Boot Mode, SPORT1 serial clock (SCLK1) is externally available through the SCLK1/ SCLK0 pin. The signal SCLK1 is used to drive the external serial memory input clock.

REV. 0

–25–

ADMCF340

Also SPORT1 Flag signal (FL1) is externally available through the FL1/DT1 Pin. This signal is used to drive the external serial memory input reset.

With SPORT1 configured in UART Mode, the SPORT0 serial clock (SCLK0) is externally available through the SCLK1/ SCLK0 Pin. The SPORT1 data transmit (DT1) is externally available through the FL1/DT1 Pin.

SPORT0 Configuration

SPORT0 can be configured in the following modes:

SPORT Mode UART Mode SPI Mode

SPORT0 can be configured for UART Mode. In this mode, the DR0 and RFS0 signals of the internal serial port are connected together.

MODECTRL REGISTER (04)

SPORT1 BOOT MODE/UART MODE

DT1

FL1

DSP CORE SPORT1

TFS1

RFS1

DR1

SCLK1

SPORT0 can be configured to operate as master SPI interface. The SPI Mode is set through Bit 14 of MODECTRL Register. When SPORT0 is configured as SPI interface, the SPORT I/O pins assume the configuration shown in Table XI.

The Slave Select Pin automatically generates the select signal at each word transfer. This pin can also be used as a general purpose I/O during the SPI transfer without affecting the SPORT operations.

The SPI clock polarity and phase are configurable through Bits 13 and 12 of MODECTRL Register. The SPI transfer using clock phase is shown in Figure 19 and Figure 20.

DT1/FL1

DR1

SCLK1/SCLK0

SCLK0

DT0

DSP CORE SPORT0

MODECTRL REGISTER (15)

SPORT0 SPORT MODE/UART MODE

DR0

TFS0

RFS0

ADMCF340

SPI

CONTROL

BLOCK

MODECTRL REGISTER (14..13..12)

SPORT0 SPI INTERFACE CONTROL

DT0

DR0

TFS0

RFS0

Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram)

–26–

REV. 0

ADMCF340

Table XI. SPORT0 Pin Assignment in SPI Mode

SPORT I/O Signal SPI Mode SPI MODE I/O

DT0 (Data Transmit) MOSI (Master Output/Slave Input) Output DR0 MISO (Master Input Slave Output) Input TFS0 SS (Slave Select) Output RFS0 Unused N/A SCLK0 SCK (Serial Clock) Output

SCK CYCLE #

SCK (POLARITY = 0)

SCK (POLARITY = 1)

MOSI

MISO

SCK CYCLE #

SCK (POLARITY = 0)

SCK (POLARITY = 1)

12345 N

SEE NOTE 1

SEE NOTE 2

NOTE

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

MSB

Figure 19. SPI Transfer Using Clock Phase CPHA = 0

12345 N

LSB

REV. 0

MOSI

SEE NOTE 1

MISO

SEE NOTE 2

NOTE

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

MSB

Figure 20. SPI Transfer Using Clock Phase CPHA = 1

–27–

LSB

ADMCF340

Table XII. Peripheral Register Map

Address (HEX) Name Bits Used Function

0x2000 ADC1 [15 . . . 4] ADC Results for V1/I 0x2001 ADC2 [15 . . . 4] ADC Results for V2/I 0x2002 ADC3 [15 . . . 4] ADC Results for V3/I 0x2003 ADCAUX [15 . . . 4] ADC Results for VAUX 0x2004 PORTA_DIR [8 . . . 0] PA8...PA0 Pins Direction Setting 0x2005 PORTA_DATA [8 . . . 0] PA8...PA0 Pins Input/Output Data 0x2006 PORTA_INTEN [8 . . . 0] PA8...PA0 Pins Interrupt Enable 0x2007 PORTA_FLAG [8 . . . 0] PORTA Pins Interrupt Status 0x2008 PWMTM [15 . . . 0] PWM Period 0x2009 PWMDT [9 . . . 0] PWM Dead Time 0x200A PWMPD [9 . . . 0] PWM Pulse Deletion Time 0x200B PWMGATE [9 . . . 0] PWM Gate Drive Configuration 0x200C PWMCHA [15 . . . 0] PWM Channel A Pulsewidth 0x200D PWMCHB [15 . . . 0] PWM Channel B Pulsewidth 0x200E PWMCHC [15 . . . 0] PWM Channel C Pulsewidth 0x200F PWMSEG [8 . . . 0] PWM Segment Select 0x2010 AUXCH0 [7 . . . 0] AUX PWM Output 0 0x2011 AUXCH1 [7 . . . 0] AUX PWM Output 1 0x2012 AUXTM0 [7 . . . 0] Auxiliary PWM Frequency Value 0x2013 AUXTM1 [7 . . . 0] Auxiliary PWM Frequency Value/Offset 0x2014 Reserved 0x2015 MODECTRL [8 . . . 0] Mode Control Register 0x2016 SYSSTAT [3 . . . 0] System Status 0x2017 IRQFLAG [1 . . . 0] Interrupt Status 0x2018 WDTIMER [15 . . . 0] Watchdog Timer 0x2019 . . . 43 Reserved 0x2044 PORTB_DIR [15 . . . 0] PB15...PB0 Pin Direction Setting 0x2045 PORTB_DATA [15 . . . 0] PB15...PB0 Data and Mode Control 0x2046 PORTB_INTEN [15 . . . 0] PB15...PB0 Pin Interrupt Enable 0x2047 PORTB_FLAG [15 . . . 0] PB15...PB0 Pin Interrupt Status 0x2048 Reserved 0x2049 PORTA_SELECT [15 . . . 0] PIO Mode Select 0x204A . . . 5F Reserved 0x2060 PWMSYNCWT [7 . . . 0] PWMSYNC Pulsewidth 0x2061 PWMSWT [0] PWM S/W Trip Bit 0x2062 . . . 67 Reserved 0x2068 ICONST_TRIM [2. . .0] ICONST_TRIM 0x2069 SHA1_TM [15...0] Sample and Hold Timer 0x206A SHA2_TM [15...0] Sample and Hold Timer 0x206B SHA3_TM [15...0] Sample and Hold Timer 0x2070 Reserved 0x2080 FMCR [15. . .0] Flash Memory Control Register 0x2081 FMAR [11. . .0] Flash Memory Address Register 0x2082 FMDRH [13. . .0] Flash Memory Data Register High 0x2083 FMDRL [15. . .0] Flash Memory Data Register Low 0x2084 . . . FF Reserved

SENSE

1 2 3

–28–

REV. 0

ADMCF340

Table XIII. DSP Core Registers

Address Name Bits Function

0x3FFA SPORT0_Rx_Words1 [15 . . . 0] Multichannel Receive Word Enables 0x3FF9 SPORT0_Rx_Words0 [15 . . . 0] Multichannel Receive Word Enables 0x3FF8 SPORT0_Tx_Words1 [15 . . . 0] Multichannel Transmit Word Enables 0x3FF7 SPORT0_Tx_Words0 [15 . . . 0] Multichannel Transmit Word Enables 0x3FF6 SPORT0_Ctrl_Reg [15 . . . 0] Control Register 0x3FF5 SPORT0_Sclkdiv [15 . . . 0] Serial Clock Divide Modulus 0x3FF4 SPORT0_Rfsdiv [15 . . . 0] Receive Frame Sync Divide Modulus 0x3FF3 SPORT0_Autobuf Ctrl [15 . . . 0] Autobuffer Control Register 0x3FF2 SPORT1_Ctrl_Reg [15 . . . 0] Control Register 0x3FFF SYSCNTL [15 . . . 0] System Control Register 0x3FFE MEMWAIT [15 . . . 0] Memory Wait State Control Register 0x3FFD TPERIOD [15 . . . 0] Interval Timer Period Register 0x3FFC TCOUNT [15 . . . 0] Interval Timer Count Register 0x3FFB TSCALE [7 . . . 0] Interval Timer Scale Register 0x3FFA . . . F3 Reserved 0x3FF2 SPORT1_CTRL_REG [15 . . . 0] SPORT1 Control Register 0x3FF1 SPORT1_SCLKDIV [15 . . . 0] SPORT1 Clock Divide Register 0x3FF0 SPORT1_RFSDIV [15 . . . 0] SPORT1 Receive Frame Sync Divide 0x3FEF SPORT1_AUTOBUF_CTRL [15 . . . 0] SPORT1 Autobuffer Control Register

REV. 0

–29–

ADMCF340

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOT-FROM-FLASH-CODE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

ALWAYS READ 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

ALWAYS READ 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLASH MEMORY CONTROL REGISTER

FLASH MEMORY ADDRESS REGISTER

0000000000000000

ADDRESS 11 ⬇ 0

FLASH MEMORY DATA REGISTER LOW (FMDRL)

0000000000000000

STATUS 5–0 DATA 7–0

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

0000000000000000

000000000000001

0x2080

0x2081

0x2083

0x2082

DATA 23–8

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.

Figure 21. Conﬁguration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–30–

REV. 0

PWMTM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9876543210

0000000

PWMDT (R/W)

00000000000000 00

PWMSEG (R/W)

000000000

DM (0x2008)

PWMTM

PWM

DM (0x2009)

PWMDT

2  PWMTM

TD =

DM (0x200F)

CLKOUT

2  PWMTM

CLKOUT

ADMCF340

SECONDS

0 = NO CROSSOVER 1 = CROSSOVER

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

C CHANNEL CROSSOVER

PWMSYNCWT (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0100011100000000

PWMSWT (R/W)

15 14 13 12 11 10 9876543210

0000 000000000000

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

DM (0x2060)

PWMSYNCWT

PWMSYNC, ON

DM (0x2061)

0 = ENABLE 1 = DISABLE

PWMSYNCWT + 1

CLKOUT

Figure 22. Conﬁguration of PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–31–

ADMCF340

PWMPD (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000

DM (0x200A)

PWMPD

MIN

CLKOUT

0 = DISABLE 1 = ENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000000

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9876543210

PWMGATE (R/W)

0000

PWMCHA (R/W)

PWMCHB (R/W)

DM (0x200B)

000000

GDCLK GATE DRIVE CHOPPING FREQUENCY

CLKOUT

CHOP

4  (GDCLK + 1)

DM (0x200C)

PWM CHANNEL A DUTY CYCLE

DM (0x200D)

PWM CHANNEL B DUTY CYCLE

15 14 13 12 11 10 9876543210

PWMCHC (R/W)

DM (0x200E)

PWM CHANNEL C DUTY CYCLE

Figure 23. Conﬁguration of Additional PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–32–

REV. 0

15 14 13 12 11 10

PORTA_DIR (R/W)

9876543210

0000000000000000

ADMCF340

DM (0x2004)

PA0-PA8

PORTB_DIR (R/W)

15 14 13 12 11 10

0000

15 14 13 12 11 10 9876543210

0000000000000000

9876543210

PB0-PB15

PORTA_DATA (R/W)

9876543210

0000

00000000

PA0-PA8

PORTB_DATA (R/W)

PB0-PA15

0 = INPUT 1 = OUTPUT

0 = LOW LEVEL 1 = HIGH LEVEL

DM (0x2044)

0000000000000000

(NOT USED IN ADMCF341)

DM (0x2005)

DM (0x2045) (NOT USED IN ADMCF341)

PORTA_SELECT (R/W)

1 = PA8

1 = PA7

0 = DR1 1 = PA6

0 = DT1/FL1

1 = PA5

1 = PA4

1000 11111111

DM (0x2049)

0 = DR0 1 = PA0

0 = DT0 1 = PA1

0 = RFS0 1 = PA2

0 = TFS0 1 = PA3

0 = CLOCKOUT

1 = AUX0

0 = PWMSYNC

1 = AUX1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

0 = AUX0/CLOCKOUT

0 = AUX1/PWMSYNC

0 = SCLK1/SCLK0

Figure 24. Conﬁguration of PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–33–

ADMCF340

PORTA_INTEN (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

0 = INTERRUPT DISABLE 1 = INTERRUPT ENABLE

PORTB_INTEN (R/W)

15 14 13 12 11 10 987654 3210

0 000000000000000

(NOT USED IN ADMCF341)

0 = INTERRUPT DISABLE

PORTA_FLAG (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

PORTB_FLAG (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

1 = INTERRUPT ENABLE

0 = INTERRUPT DISABLE 1 = INTERRUPT ENABLE

(NOT USED IN ADMCF341)

0 = INTERRUPT DISABLE 1 = INTERRUPT ENABLE

DM (0x2006)

DM (0x2046)

DM (0x2007)

DM (0x2047)

Figure 25. Conﬁguration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUXCH0 (R/W)

AUXCH1 (R/W)

AUXTM0 (R/W)

AUXTM1 (R/W)

000000000000

= 2  (AUXCH0) 

ON, AUX0

000000000000

= 2  (AUXCH1) 

ON, AUX1

111111111111

AUX0 PERIOD = 2  (AUXTM0 + 1) 

0000

1111

1111111111111111

DM (0x2010)

DM (0x2011)

DM (0x2012)

DM (0x2013)

AUX1 PERIOD = 2  (AUXTM1)  OFFSET = 2  (AUXTM1) 

Figure 26. Conﬁguration of Auxiliary PWM Register

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

–34–

REV. 0

ADMCF340

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC1 (R)

ADC2 (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC3 (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADCAUX (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ICONST_TRIM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

0000 DM (0x2000)

CONVERSION STATUS

DM (0x2001)

0000

CONVERSION STATUS

DM (0x2002)

0000

CONVERSION STATUS

DM (0x2003)

0000

DM (0x2068)

0 = DATA READY

1 = NOT READY

0 = DATA READY

1 = NOT READY

0 = DATA READY

1 = NOT READY

ICONST MIN = BITS 0–2 CLEARED. ICONST MAX = BITS 0–2 SET.

SHA1_TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x2069)

0000000000000000

SHA2 _TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x206A)

0000000000000000

SHA3 _TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x206B)

0000000000000000

Figure 27. Conﬁguration of ADC Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–35–

ADMCF340

0 = SPORT MODE

1 = UART MODE

0 = SPORT

1 = SP1 MODE

0 = STANDARD

1 = REVERSE

0 = PHA0 1 = PHA1

0 = I

SENSE

1 = VOLTAGE

0 = I

SENSE

1 = VOLTAGE

0 = I

SENSE

1 = VOLTAGE

SPORT 0

MODE SELECT

SPORT 0

SPI MODE

SPI CLOCK

POLARITY

SPI CLOCK

PHASE

CHANNEL 3 SELECTION

CHANNEL 2 SELECTION

CHANNEL 1 SELECTION

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODECTRL (R/W)

0000000000000000

SPORT1 MODE

PWM UPDATE

MODE SELECT

DM (0x2015)

PWMTRIP

INTERRUPT

PWMSYNC

INTERRUPT

SELECT

ADC MUX

CONTROL

ADC MUX CONTROL*

0 = DISABLE 1 = ENABLE

0 = BOOT MODE 1 = UART MODE

ADC MUX CONTROL*

0 = SINGLE UPDATE MODE 1 = DOUBLE UPDATE MODE

0 = OFFSET MODE

1 = INDEPENDENT MODE

0 = CLKIN RATE

1 = CLKOUT RATE

AUX PWM

MODE SELECT

ADC

COUNTER

SYSSTAT (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000000

0 = 1ST HALF OF PWM CYCLE 1 = 2ND HALF OF PWM CYCLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM TIMER

STATUS

IRQFLAG (R)

000000000000

WDTIMER (W)

0000000000000000

0000

DM (0x2016)

PWMTRIP

PIN STATUS

WATCHDOG

STATUS

DM (0x2017)

PWMTRIP INTERRUPT

PWMSYNC INTERRUPT

DM (0x2018)

0 = LOW 1 = HIGH

0 = NORMAL 1 = WATCHDOG RESET OCCURRED

0 = NO INTERRUPT 1 = INTERRUPT OCCURRED

Figure 28. Conﬁguration of Status/Control Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

–36–

REV. 0

ADMCF340

Table XIV. Auxiliary Analog Input Selection

Selection MODECTRL (5) MODECTRL (1) MODECTRL (0)

VAUX0 (1) 0 0 0 VAUX1 (1) 0 0 1 VAUX2 (1) 0 1 0 VREF (1) 0 1 1 VAUX4 1 0 0 VAUX5 1 0 1 VAUX6 1 1 0 VAUX7 1 1 1

REV. 0

–37–

ADMCF340

ICNTL

43210

11000

DSP REGISTER

0 = DISABLE 1 = ENABLE

INTERRUPT FORCE INTERRUPT CLEAR

IRQ2

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

SOFTWARE 0

SPORT1 TRANSMIT OR IRQ1

SPORT1 RECEIVE OR IRQ0

INTERRUPT NESTING

IFC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IRQ0 SENSITIVITY

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

0 = LEVEL 1 = EDGE

DSP REGISTER

0000000000000000

TIMER

SPORT1 RECEIVE OR IRQ0

SPORT1 TRANSMIT OR IRQ1

SOFTWARE 0

SOFTWARE 1

SPORT0 RECEIVE

SPORT0 TRANSMIT

0 = DISABLE (MASK) 1 = ENABLE

TIMER

IMASK (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000110

PERIPHERAL (OR IRQ2)

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

DSP REGISTER

TIMER

SPORT1 RECEIVE (OR IRQ0)

SPORT1 TRANSMIT (OR IRQ1)

SOFTWARE 0

IRQ2

0 = DISABLE (MASK) 1 = ENABLE

Figure 29. Conﬁguration of Interrupt Control Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–38–

REV. 0

ADMCF340

SPORT1 CONFIGURE

MEMWAIT (R/W)

SYSCNTL (R/W)

11000000011111

0 = FI, FO, IRQ0, IRQ1, SCLK 1 = SERIAL PORT

0 = DISABLED 1 = ENABLED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT1 ENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1111111 11111111

Figure 30. Conﬁguration of Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

DM (0x3FFF)

DM (0x3FFE)

REV. 0

–39–

ADMCF340

OUTLINE DIMENSIONS

64-Lead Thin Plastic Quad Flatpack [LQFP]

(ST-64)

Dimensions shown in millimeters and (inches)

0.80 (0.0315)

16.25 (0.6398)

16.00 (0.6299) SQ

15.75 (0.6201)

TOP VIEW

(PINS DOWN)

BSC

0.35 (0.0138)

4964

1.60 (0.0630)

PLANE

0.17 (0.0067)

MAX

12 TYP

10

6 2

7 0

0.75 (0.0295)

0.60 (0.0236)

0.45 (0.0177)

SEATING

0.10 (0.0039) MAX LEAD

COPLANARITY

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14.10 (0.5551)

14.00 (0.5512) SQ

13.90 (0.5472)

1.45 (0.0571)

1.40 (0.0551)

1.35 (0.0531)

C02723–0–7/02(0)

–40–

PRINTED IN U.S.A.

REV. 0

Analog Devices ADMCF340BST, ADMCF340 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

ANALOG-TO-DIGITAL CONVERTER

CURRENT SOURCE

VOLTAGE REFERENCE

POWER-ON RESET

ELECTRICAL CHARACTERISTICS

TIMING PARAMETERS

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

ORDERING GUIDE

PIN FUNCTION DESCRIPTIONS

GENERAL DESCRIPTION

DSP CORE ARCHITECTURE OVERVIEW

SERIAL PORTS

PIN FUNCTION DESCRIPTION

INTERRUPT OVERVIEW

MEMORY MAP

FLASH MEMORY SUBSYSTEM

Special Flash Registers

FLASH PROGRAM BOOT SEQUENCE

SYSTEM INTERFACE

Clock Signals

Reset

DSP Control Registers

Three-Phase Timing Unit

PWM Switching Frequency: PWMTM Register

PWM Switching Dead Time: PWMDT Register

PWM Operating Mode: MODECTRL and SYSSTAT Registers

Width of the PWMSYNC Pulse: PWMSYNCWT Register

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC Registers

Effective PWM Resolution

Minimum Pulsewidth: PWMPD Register

Output Control Unit: PWMSEG Register

Gate Drive Unit: PWMGATE Register

PWM Polarity Control, PWMPOL Pin

SWITCHED RELUCTANCE MODE

PWM Shutdown

PWM Registers

ADC OVERVIEW

Single Slope ADC Operations

ADC Resolution

Programmable Current Source

Charging Capacitor Selection

Analog Front End

Auxiliary PWM Interface, Registers and Pins

WATCHDOG TIMER

PROGRAMMABLE DIGITAL INPUT/OUTPUT

PIO Registers

INTERRUPT CONTROL

Interrupt Masking

Interrupt Configuration

INTERRUPT OPERATION

SYSTEM CONTROLLER

SPORT1 and SPORT0 Control

SPORT1 Configuration

SPORT0 Configuration

OUTLINE DIMENSIONS