Analog Devices ADMCF327BR, ADMCF327 Datasheet
28-Lead Flash Memory
a
DSP Switched Reluctance Motor Controller
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
MOTOR TYPE
Switched Reluctance Motors (SR)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 24-Bit Program Memory RAM
512 16-Bit Data Memory RAM
4K 24-Bit Program Memory ROM
4K 24-Bit Program Flash Memory
Three Independent Programmable Sectors
Security Lock Bit
10K Erase/Program Cycles
ADMCF327
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function Options
28-Lead SOIC Package
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
ARITHMETIC UNITS
MACALU
PROGRAM
SEQUENCER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
SHIFTER
POR TIMER
MEMORY BLOCK
PROGRAM
ROM
4K 24
PROGRAM
RAM
512 24
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PROGRAM
FLASH
4K 24
DATA
MEMORY
512 16
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
VREF
2.5V
SERIAL PORT
SPORT 1
6
ANALOG
INPUTS
9-BIT
PIO
2 8-BIT
AUX
PWM
16-BIT
THREE-
PHASE
PWM
WATCH-
DOG
TIMER
(VDD = 5 V 5%, GND = 0 V, TA = –40C to +85C, CLKIN = 10 MHz, unless
ADMCF327–SPECIFICATIONS
otherwise noted)
ANALOG-TO-DIGITAL CONVERTER
Parameter Min Typ Max Unit Conditions/Comments
Signal Input 0.3 3.5 V V1, V2, V3, VAUX0, VAUX1, VAUX2
Resolution
Linearity Error
Zero Offset
Channel-to-Channel Comparator Match
Comparator Delay 600 ns
ADC High Level Input Current
ADC Low Level Input Current
NOTES
1
Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.
2
2.44 kHz sample frequency, V1, V2, V3, VAUX0, VAUX1, VAUX2.
Specifications subject to change without notice.
1
2
2
2
2
2
–20 0 +20 mV
–10 µAV
2 4 Bits
12 Bits
20 mV
10 µAV
= 3.5 V
IN
= 0.0 V
IN
ELECTRICAL CHARACTERISTICS
Parameter Min Typ Max Unit Conditions/Comments
V
V
V
V
V
I
I
I
I
I
I
I
I
I
NOTES
1
Output Pins PIO0–PIO8, AH, AL, BH, BL, CH, CL.
2
XTAL Pin.
3
Internal Pull-Up, RESET.
4
Internal Pull-Down, PWMTRIP, PIO0–PIO8.
5
Three stateable pins DT1, RFS1, TFS1, SCLK1.
6
Outputs not Switching.
Specifications subject to change without notice.
Low Level Input Voltage 0.8 V
IL
High Level Input Voltage 2 V
IH
Low Level Output Voltage
OL
Low Level Output Voltage
OL
High Level Output Voltage 4 V I
OH
Low Level Input Current
IL
Low Level Input Current –10 µAV
IL
High Level Input Current
IH
High Level Input Current 10 µAV
IH
High Level Three-State Leakage Current
OZH
Low Level Three-State Leakage Current5–10 µAV
OZL
Low Level PWMTRIP Current –10 µA@ V
IL
Supply Current (Idle)
DD
Supply Current (Dynamic)
DD
Supply Current Programming
1
2
3
4
6
6
6
–120 µAV
5
0.4 V IOL = 2 mA
0.8 V IOL = 2 mA
90 µAV
90 µAV
41 mA
108 mA
123 mA
= –0.5 mA
OH
= 0 V
IN
= 0 V
IN
= V
IN
DD
= V
IN
DD
= V
IN
DD
= 0
IN
= Max, VIN = 0 V
DD
CURRENT SOURCE
1
Parameter Min Typ Max Unit Conditions/Comments
Programming Resolution 3 Bits
Default Current
2
65 83 95 µA ICONST_TRIM = 0x00
Tuned Current 95 100 105 µA
NOTES
1
For ADC Calibration.
2
0.3 V to 3.5 V ICONST Voltage.
Specifications subject to change without notice.
–2–
REV. 0
ADMCF327
VOLTAGE REFERENCE
Parameter Min Typ Max Unit Conditions/Comments
Voltage Level (V
Output Voltage Drift 35 ppm/°C
Specifications subject to change without notice.
) 2.40 2.50 2.60 V
REF
2.45 2.50 2.55 V T
= 25°C to 85°C SOIC
A
POWER-ON RESET
Parameter Min Typ Max Unit Conditions/Comments
Reset Threshold (V
Hysteresis (V
Reset Active Timeout Period (t
NOTES
1216
CLKOUT Cycles.
Specifications subject to change without notice.
HYST
) 3.2 3.7 4.2 V
RST
) 100 mV
) 3.2
RST
1
ms
FLASH MEMORY
Parameter Min Typ Max Unit Conditions/Comments
Endurance 10,000 Cycles Cycle = Erase/Program/Verify
Data Retention 15 Years
Program and Erase Operating Temperature 0 85
Read Operating Temperature –40 +85
Specifications subject to change without notice.
C
C
REV. 0
–3–
ADMCF327
TIMING PARAMETERS
Parameter Min Max Unit
Clock Signals
Signal tCK is defined as 0.5 t
frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When
values are within the range of 0.5 t
t
CK
all relevant timing parameters to obtain specification value.
Example: t
= 0.5 tCK – 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
CKH
Timing Requirements:
t
CKIN
t
CKIL
t
CKIH
CLKIN Period 100 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns
Switching Characteristics:
t
CKL
t
CKH
t
CKOH
CLKOUT Width Low 0.5 tCK – 10 ns
CLKOUT Width High 0.5 tCK – 10 ns
CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirement:
t
RSP
RESET Width Low 5 t
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
NOTES
1
Applies after power-up sequence is complete.
PWMTRIP Width Low t
. The ADMCF327 uses an input clock with a
CKIN
period, they should be substituted for
CKIN
CK
CK
1
ns
ns
CLKIN
CLKOUT
t
CKIN
t
CKIL
t
CKL
Figure 1. Clock Signals
t
t
CKOH
CKH
t
CKIH
–4–
REV. 0
ADMCF327
Parameter Min Max Unit
Serial Ports
Timing Requirements:
t
SCK
t
SCS
t
SCH
t
SCP
Switching Characteristics:
t
CC
t
SCDE
t
SCDV
t
RH
t
RD
t
SCDH
t
SCDD
t
TDE
t
TDV
t
RDV
Specifications subject to change without notice.
SCLK Period 100 ns
DR/TFS/RFS Setup before SCLK Low 15 ns
DR/TFS/RFS Hold after SCLK Low 20 ns
SCLKIN Width 40 ns
CLKOUT High to SCLK
OUT
0.25 t
0.25 tCK + 20 ns
CK
SCLK High to DT Enable 0 ns
SCLK High to DT Valid 30 ns
TFS/RFS
TFS/RFS
Hold after SCLK High 0 ns
OUT
Delay from SCLK High 30 ns
OUT
DT Hold after SCLK High 0 ns
SCLK High to DT Disable 30 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 25 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 30 ns
CLKOUT
SCLK
RFS
TFS
RFS
OUT
TFS
OUT
TFS
(ALTERNATE
FRAME MODE)
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
RFS
DR
DT
t
CC
IN
IN
t
SCDE
t
t
RH
t
t
TDE
RD
SCDV
t
t
RDV
TDV
t
CC
t
t
SCS
SCH
t
t
SCDH
SCDD
t
SCK
t
SCP
t
SCP
Figure 2. Serial Port Timing
REV. 0
–5–
ADMCF327
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
DD
+ 0.3 V
DD
Flash Memory Erase or/Program
Temperature Range (Ambient) . . . . . . . . . . . . 0°C to 85°C
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION
PIO6/CLKOUT PIO7/AUX1
PIO5/RFS1 PIO8/AUX0
PIO4/DR1A AL
PIO3/SCLK1 AH
PIO2/DR1B BL
PIO1/DT1 BH
PIO0/TFS1 CL
PWMTRIP
1
2
3
4
5
6
ADMCF327
7
TOP VIEW
CLKIN CH
(Not to Scale)
8
XTAL
9
V
10
DD
11
12
V3
13
V2 VAUX1
14
V1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
GND
ICONST
VAUX2
VAUX0
PIN FUNCTION DESCRIPTIONS
Pin Pin Pin
No. Name Type
1 PIO6/CLKOUT I/O
2 PIO5/RFS1 I/O
3 PIO4/DR1A I/O
4 PIO3/SCLK1 I/O
5 PIO2/DR1B I/O
6 PIO1/DT1 I/O
7 PIO0/TFS1 I/O
8 CLKIN I
9 XTAL O
10 V
DD
SUP
11 PWMTRIP I
12 V3 I
13 V2 I
14 V1 I
15 VAUX0 I
16 VAUX1 I
17 VAUX2 I
18 ICONST O
19 GND GND
20
RESET I
21 CH O
22 CL O
23 BH O
24 BL O
25 AH O
26 AL O
27 PIO8/AUX0 I/O
28 PIO7/AUX1 I/O
ORDERING GUIDE
Temperature Instruction Package Package
Model Range Rate Description Option
ADMCF327BR –40°C to +85°C 20 MHz 28-Lead Wide Body (SOIC) R-28
ADMCF327-EVALKIT Development Tool Kit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
WARNING!
the ADMCF327 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
–6–
REV. 0
ADMCF327
GENERAL DESCRIPTION
The ADMCF327 is a low cost, single-chip DSP-based controller,
suitable for permanent magnet synchronous motors, ac induction
motors, and brushless dc motors. The ADMCF327 integrates a
20 MIPS, fixed-point DSP core with a complete set of motor
control and system peripherals that permits fast, efficient development of motor controllers.
The DSP core of the ADMCF327 is the ADSP-2171, which is
completely code-compatible with the ADSP-21xx DSP family
and combines three computational units, data address generators
and a program sequencer. The computational units comprise an
ALU, a multiplier/accumulator (MAC) and a barrel shifter.
The ADSP-2171 adds new instructions for bit manipulation,
multiplication (× squared), biased rounding and global interrupt masking.
The system peripherals are the power-on reset circuit (POR),
the watchdog timer and a synchronous serial port. The serial
port is configurable, and double buffered, with hardware support for UART and SCI port emulation.
The ADMCF327 provides 512 × 24-bit program memory RAM,
4K × 24-bit program memory ROM, 4K × 24-bit program
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PROGRAM
SEQUENCER
14
FLASH memory, and 512 × 16-bit data memory RAM. The
user code will be stored and executed from the flash memory.
The program and data memory RAM can be used for dynamic
data storage or can be loaded through the serial port from an
external device as in other ADMCxxx family parts. The program
memory ROM contains a monitor function as well as useful routines for erasing, programming, and verifying the flash memory.
The motor control peripherals of the ADMCF327 provide a 12-bit
analog data acquisition system with six analog input channels,
and an internal voltage reference. In addition, a three-phase,
16-bit, center-based PWM generation unit can be used to produce
high accuracy PWM signals with minimal processor overhead.
The ADMCF327 also contains two auxiliary PWM outputs
and nine lines of digital I/O.
Because the ADMCF327 has a limited number of pins, functions
such as the auxiliary PWM and the serial communication port
are multiplexed with the nine programmable input/output (PIO)
pins. The pin functions can be independently selected to allow
maximum flexibility for different applications.
FLASH
PM ROM
4K 24
PM RAM
512 24
PMA BUS
PROGRAM
MEMORY
4K 24
DM RAM
512 16
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
16
14
24
BUS
EXCHANGE
16
INPUT REGS
SHIFTER
OUTPUT REGS
R BUS
CONTROL
LOGIC
Figure 3. DSP Core Block Diagram
DMA BUS
PMD BUS
DMD BUS
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT
6
TIMER
REV. 0
–7–
ADMCF327
DSP CORE ARCHITECTURE OVERVIEW
Figure 3 is an overall block diagram of the DSP core of the
ADMCF327, which is based on the fixed-point ADSP-2171.
The flexible architecture and comprehensive instruction set of
the ADSP-2171 allow the processor to perform multiple operations
in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN)
the DSP core can:
• Generate the next program address.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
This all takes place while the processor continues to:
• Receive and transmit through the serial port.
• Decrement the interval timer.
• Generate three-phase PWM waveforms for a power inverter.
• Generate two signals using the 8-bit auxiliary PWM timers.
• Acquire four analog signals.
• Decrement the watchdog timer.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and
logic operations as well as providing support for division primitives.
The MAC performs single-cycle multiply, multiply/add, and
multiply/subtract operations with 40 bits of accumulation. The
shifter performs logical and arithmetic shifts, normalization,
denormalization and derive-exponent operations. The shifter can
be used to efficiently implement numeric format control, including
floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMCF327 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value in one of
four modify (M registers). A length value may be associated with
each pointer (L registers) to implement automatic modulo
addressing for circular buffers. The circular buffering feature is
also used by the serial ports for automatic data transfers to and
from on-chip memory. DAG1 generates only data memory
address and provides an optional bit-reversal capability. DAG2
may generate either program or data memory addresses but has
no bit-reversal capability.
Efficient data transfer is achieved with the use of five
internal buses:
• Program memory address (PMA) bus.
• Program memory data (PMD) bus.
• Data memory address (DMA) bus.
• Data memory data (DMD) bus.
• Result (R) bus.
Program Memory on the ADMCF327 can either be internal
(on-chip RAM) or external (Flash). Internal program memory
can store both instructions and data, permitting the ADMCF327
to fetch two operands in a single instruction cycle—one from
program memory and one from data memory. Operation from
external program memory is described in detail in the ADSP-
2100 Family User’s Manual, Third Edition.
The ADMCF327 writes data from its 16-bit registers to the
24-bit program memory using the PX register to provide the
lower eight bits. When it reads data (not instructions) from
24-bit program memory to a 16-bit data register, the lower
eight bits are placed in the PX register.
The ADMCF327 can respond to a number of distinct DSP
core and peripheral interrupts. The DSP interrupts comprise
a serial port receive interrupt, a serial port transmit interrupt,
a timer interrupt, and two software interrupts. Additionally,
the motor control peripherals include two PWM interrupts
and a PIO interrupt.
The serial port (SPORT1) provides a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. SPORT1 can generate an internal programmable serial clock or accept an external serial clock.
A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n–1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt
is generated, and the count register is reloaded from a 16-bit
period register (TPERIOD).
The ADMCF327 instruction set provides flexible data moves
and multifunction instructions (one or two data moves within a
computation) that will execute from internal program memory
RAM. The ADMCF327 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools support program development. For further
information on the DSP core, refer to the ADSP-2100 Family
User’s Manual, Third Edition, with particular reference to
the ADSP-2171.
–8–
REV. 0
ADMCF327
Serial Port
The ADMCF327 incorporates a complete synchronous serial port
(SPORT1) for serial communication and multiprocessor communication. The following is a brief list of capabilities of the
ADMCF327 SPORT1. Refer to the ADSP-2100 Family User’s
Manual, Third Edition, for further details.
• SPORT1 is bidirectional and has a separate, double-buffered
transmit and receive section.
• SPORT1 can use an external serial clock or generate its own
serial clock internally.
• SPORT1 has independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted,
with either of two pulsewidths and timings.
• SPORT1 supports serial data word lengths from 3 bits to 16 bits
and provides optional A-law and µ-law companding accord-
ing to ITU (formerly CCITT) recommendation G.711.
• SPORT1 receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORT1 can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt is
generated after a data buffer transfer.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals.
The internally generated serial clock may still be used in
this configuration.
• SPORT1 has two data receive pins (DR1A and DR1B), which
are internally multiplexed onto the one DR1 port of the
SPORT1. The particular data receive pin selected is determined by a bit in the MODECTRL register.
PIN FUNCTION DESCRIPTION
The ADMCF327 is available in a 28-lead SOIC package.
Table I describes the pins.
Table I. Pin List
Pin Group # of Input/
Name Pins Output Function
RESET 1 I Processor Reset Input
SPORT1
CLKOUT
CLKIN, XTAL 2 I, O External Clock or Quartz
PIO0–PIO8
AUX0–AUX1
AH–CL 6 O PWM Outputs
PWMTRIP 1 I PWM Trip Signal
V1, V2, V3 3 I Analog Inputs
VAUX0–VAUX2 3 I Auxiliary Analog Input
ICONST 1 O ADC Constant Current Source
V
GND 1 Ground
NOTE
1
Multiplexed pins, individually selectable through PIOSELECT and PIODATA1
registers.
DD
1
1
6 I/O Serial Port 1 Pins (TFS1, RFS1,
DT1, DR1A, DR1B, SCLK1)
1 O Processor Clock Output
1
9 I/O Digital I/O Port Pins
1
2 O Auxiliary PWM Outputs
1 Power Supply
Crystal Connection Point
INTERRUPT OVERVIEW
The ADMCF327 can respond to 16 different interrupt sources
with minimal overhead, five of which are internal DSP core
interrupts and 11 from the motor control peripherals. The five
DSP core interrupts are SPORT1 receive (or IRQ0) and transmit (or IRQ1), the internal timer, and two software interrupts.
The motor control peripheral interrupts are the nine programmable I/Os and two from the PWM (PWMSYNC pulse and
PWMTRIP). All motor control interrupts are multiplexed into the
DSP core through the peripheral IRQ2 interrupt. The interrupts
are internally prioritized and individually maskable. A detailed
description of the entire interrupt system of the ADMCF327 is
presented later, following a more detailed description of each
peripheral block.
MEMORY MAP
The ADMCF327 has two distinct memory types: program memory
and data memory. In general, program memory contains user
code and coefficients, while the data memory is used to store
variables and data during program execution. Three kinds of
program memory are provided on the ADMCF327: RAM, ROM,
and flash memory. The motor control peripherals are memory
mapped into a region of the data memory space starting at 0x2000.
The complete program and data memory maps are given in
Tables II and III, respectively.
Table II. Program Memory Map
Memory
Address Range Type Function
0x0000–0x002F RAM Internal Vector Table
0x0030–0x01FF RAM User Program Memory
0x0200–0x07FF Reserved
0x0800–0x17FF ROM Reserved Program Memory
0x1800–0x1FFF Reserved
0x2000–0x20FF FLASH User Program Memory
Sector 0
0x2100–0x21FF FLASH User Program Memory
Sector 1
0x2200–0x2FFF FLASH User Program Memory
Sector 2
0x3000–0x3FFF Reserved
Table III. Data Memory Map
Memory
Address Range Type Function
0x0000–0x1FFF Reserved
0x2000–0x20FF Memory Mapped Registers
0x2100–0x37FF Reserved
0x3800–0x39FF RAM User Data Memory
0x3A00–0x3BFF RAM Reserved
0x3C00–0x3FFF Memory Mapped Registers
REV. 0
–9–
ADMCF327
FLASH MEMORY SUBSYSTEM
The ADMCF327 has 4K × 24-bit of user-programmable, nonvolatile flash memory. A flash programming utility is provided
with the development tools, which performs the basic device
programming operations: erase, program, and verify.
The flash memory array is partitioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
Sector 0, Sector 1, and Sector 2, respectively. These sectors are
mapped into external program memory address space.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named Flash Memory Control Register
(FMCR), Flash Memory Address Register (FMAR), Flash
Memory Data Register Low (FMDRL) and Flash Memory Data
Register High (FMDRH). These registers are diagrammed later in
this data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should not
modify them directly. The flash programming utility provides
a complete interface to the flash memory.
Special Flash Registers
The flash module has four nonvolatile 8-bit registers called Special
Flash Registers (SFRs) which are accessible independently of the
main flash array, via the flash programming utility. These registers are for general purpose, nonvolatile storage. When erased,
the Special Flash Registers contain all 0s. To read Special Flash
Registers from the user program, call the read_reg routine contained in ROM. Refer to the (ADMCF32x DSP Motor Controller
Developers Reference Manual) for an example.
Boot-from-Flash Code
A security feature is available in the form of a code that, when set,
causes the processor to execute the program in flash memory upon
power-up or reset. In this mode, the flash programming utility
and debugger are unable to communicate with the ADMCF327.
Consequently, the contents of the flash memory can neither
be programmed nor read.
The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way
to clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in
the ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An example
would be to detect a high level on a PIO pin during start-up initialization and then call the flash_init or auto_erase_routine. The
flash_init routine will erase the entire user program in flash
memory before clearing the boot-from-flash code, thus ensuring
the security of the user program. If security is not a concern, the
auto_erase_reg routine can be used to clear the boot-from-flash
code while leaving the user program intact.
Refer to the ADMCF32x DSP Motor Controller Developer’s Reference
Manual for further instructions and an example of using the
boot-from-flash code.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execution at address 0x0800 of internal program ROM. The ROM
monitor program that is located there checks the Boot-fromFlash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user’s application program.
If the Boot-from-Flash code is not set, the monitor attempts
to boot from an external device as described in the ADMCF32x
DSP Motor Controller Developers Reference Manual
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMCF327
with an external crystal.
CLKOUT
ADMCF327
RESET
XTAL
CLKIN
22pF
10MHz
22pF
Figure 4. Basic System Configuration
Clock Signals
The ADMCF327 can be clocked either by a crystal or a TTLcompatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half
the instruction rate. The signal is connected to the CLKIN pin
of the ADMCF327. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF327 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.
Because the ADMCF327 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in Figure 4.
A parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
Reset
The ADMCF327 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper initialization.
The ADMCF327 contains an integrated power-on reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMCF327 V
in reset while V
When this voltage is exceeded, the ADMCF327 is held in reset
for an additional 2
power-down, when the voltage on the V
V
RST–VHYST
pin and holds the DSP core and peripherals
DD
is less than the threshold voltage level, V
DD
16
DSP clock cycles (t
in Figure 5). On
RST
pin falls below
DD
RST
.
, the ADMCF327 will be reset. Also, if the external
RESET pin is actively pulled low at any time after power-up, a
complete hardware reset of the ADMCF327 is initiated.
–10–
REV. 0
ADMCF327
V
RST
V
RESET
DD
t
RST
Figure 5. Power-On Reset Operation
V
RST – VHYST
The ADMCF327 reset sets all internal stack pointers to the
empty stack condition, masks all interrupts, clears the MSTAT
register and performs a full reset of all of the motor control peripherals. Following a power-up, it is possible to initiate a DSP core
and motor control peripheral reset by pulling the RESET pin
low. The RESET signal must meet the minimum pulsewidth
specification, t
. Following the reset sequence, the DSP
RSP
core starts executing code from the internal PM ROM located
at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMCF327, all other
bits in this register must be cleared.
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
resister is 0xFFFF. For proper operation of the ADMCF327,
this register must always contain the value 0x8000 (which is
the default).
The configuration of both the SYSCNTL and MEMWAIT registers of the ADMCF327 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Switched Reluctance Mode
The PWM generator block of the ADMCF327 is a flexible,
programmable, three-phase PWM waveform generator that
can be programmed to generate the required switching patterns
to drive a three-phase voltage source inverter for a Switched
Reluctance Motor.
The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH, and
CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are
programmable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation barrier
in the gate-drive circuits that turn on the power devices of the
inverter. In general, there are two common isolation techniques:
optical isolation using optocouplers, and transformer isolation
using pulse transformers. The PWM controller of the ADMCF327
permits mixing of the output PWM signals with a high frequency
chopping signal to permit an easy interface to such pulse transformers. The features of this gate-drive chopping mode can be
controlled by the PWMGATE register. There is an 8-bit value
within the PWMGATE register that directly controls the chopping
frequency. In addition, high frequency chopping can be independently enabled for the high side and the low side outputs using
separate control bits in the PWMGATE register.
The PWM generator is capable of operating in two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetrical about the midpoint of the PWM period. In the double update
mode, a second updating of the PWM duty cycle values is implemented at the midpoint of the PWM period. In this mode, it is
possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in three-phase PWM inverters. This
technique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The operating mode of the PWM block (single or double update mode) is
selected by a control bit in MODECTRL register.
The PWM generator of the ADMCF327 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In single update mode, a PWMSYNC pulse is
produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMCF327 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, which, when
brought LO, instantaneously places all six PWM outputs in
the LO state. Because this hardware shutdown mechanism is
asynchronous, and the associated PWM disable circuitry does
not use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT register.
Status information about the PWM system of the ADMCF327
is available to the user in the SYSSTAT register. In particular,
the state of PWMTRIP is available, as well as a status bit that
indicates whether operation is in the first half or the second half
of the PWM period.
REV. 0
–11–
Loading...