Analog Devices ADMC401errata a Datasheet

a

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ERRATA

These changes have been made in REV B issued on May 25, 2000

Page No. Description

4 Add “

19 Delete (POR) in the paragraph heading:

33 In the

36 Figure 30: The uppermost “

37 Text in right column, 3

38 Text in right column, section “

ADMC401-ADVEVALKITADMC401-ADVEVALKIT

ADMC401-ADVEVALKIT” and “

ADMC401-ADVEVALKITADMC401-ADVEVALKIT

PWM Shutdown PWM Shutdown

PWM Shutdown section, the following sentence is required to clarify the condition of the

PWM Shutdown PWM Shutdown
three low side PWM signals when the PWMTRIP pin is in the SR Mode

*Note, however, when the PWMTRIP pin is in the SR mode, the three low side PWM signals
from the three-phase timing unit will remain in the ON state

3t3t

3t

3t3t

CKCK

CK”

CKCK

rd

line from top: word “

EET Status RegisterEET Status Register

EET Status Register”, 2

EET Status RegisterEET Status Register

Change from “....the encoder event timer is set to

set to

oneone

one and...”

oneone

ADMC401-PBADMC401-PB

ADMC401-PB” to the Ordering Guide Table

ADMC401-PBADMC401-PB

Reset and Power On Reset CircuitReset and Power On Reset Circuit

Reset and Power On Reset Circuit

Reset and Power On Reset CircuitReset and Power On Reset Circuit

label should be replaced: “

EISZLATCHEISZLATCH

EISZLATCH” should be spelled “

EISZLATCHEISZLATCH

nd

zerozero

zero and ...” to “...the encoder event timer is

zerozero

ADMC401

tt

t

”

tt

CKCK

CK

CKCK

paragraph, 1st sentence:

EISLATCHEISLATCH

EISLATCH”

EISLATCHEISLATCH

The following sentence should be
the EETDELTAT register is valid, representing the time from the direction reversal to the instant
at which the EIUCNT register is read”

39 Table VI: in the Unit Column, the word “

43 Figure 34: There are 2 pin pairs labeled “

SCLK1SCLK1

“

SCLK1”

SCLK1SCLK1

46 Table VIII (continued from previous page): “

EET Delta Timer RegisterEET Delta Timer Register

with “

EET Delta Timer Register”

EET Delta Timer RegisterEET Delta Timer Register

48 Figure 36: The

be shown with a “

49 Figure 37: The

white rectangles; bits 0 through 7. These bits are undefined at reset

REV.A Errata 5/23/00

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

PWMGATE (R/W)PWMGATE (R/W)

PWMGATE (R/W) register and the

PWMGATE (R/W)PWMGATE (R/W)

00

0” not blank (undefined)

00

EIUSCALE EIUSCALE

EIUSCALE register should be blank (undefined) and not have zeros in the

EIUSCALE EIUSCALE

deleteddeleted

deleted: “In the case of a direction reversal, the contents of

deleteddeleted

BitsBits

Bits” should be “

BitsBits

TFS1TFS1

TFS1”. The lower “

TFS1TFS1

EEE Timer Period RegisterEEE Timer Period Register

EEE Timer Period Register” should be swapped

EEE Timer Period RegisterEEE Timer Period Register

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Tel: [phone]World Wide Web Site: http://www.analog.com
Fax: [phone] ©Analog Devices, Inc., 2000

MHzMHz

MHz”

MHzMHz

TFS1 TFS1

TFS1 pins should be labeled

TFS1 TFS1

PWMGATE (R/W)PWMGATE (R/W)

PWMGATE (R/W) register: Bit “

PWMGATE (R/W)PWMGATE (R/W)

00

0” should

00