Analog Devices ADMC330BST Datasheet

Single Chip DSP

a

FEATURES
Seven Analog Input Channels

Acquisition Synchronized to PWM Switching Frequency

Three-Phase 12-Bit PWM Generator

Programmable Deadtime and Narrow Pulse Deletion

2.5 kHz Minimum Switching Frequency
ECM Control Mode
Output Control for Space Vector Modulation
Gate Drive Block (Pulsed PWM Output Capability)
Hardwired Output Polarity Control
External Trip Input

Two 8-Bit Auxiliary PWM Timers

Synthesized Analog Output
39 kHz Frequency
0 to 99.6% Duty Cycle

Eight Bits of Digital I/O Port

Bit Configurable as Input or Output
Change of State Interrupt Support

20 MIPS Fixed Point DSP Core

Powerful Program Sequencer

Zero Overhead Looping
Conditional Instruction Execution

Independent Computational Units

ALU
Multiplier/Accumulator

Barrel Shifter
Multifunction Instructions
Single-Cycle Instruction Execution (50 ns)
Single-Cycle Context Switch

ADSP-2100 Family Code and Function Compatible with

Instruction Set Enhancements

16-Bit Watchdog Timer
Programmable 16-Bit Interval Timer with Prescaler
Two Synchronous Serial Ports

Full Debugger Interface
2 Bootstrap Protocols via Sport 1, Serial and UART

Memory Configuration

2K 3 24-Bit Word Program RAM
1K 3 16-Bit Word Data RAM
2K 3 24-Bit Word Program ROM

Motor Controller

ADMC330

FUNCTIONAL BLOCK DIAGRAM

ADSP-2100 BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 1 DAG 2

ARITHMETIC UNITS

ALU

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

MAC

DATA MEMORY ADDRESS

GENERAL DESCRIPTION

The ADMC330 is a low cost single chip DSP microcontroller
optimized for stand alone ac motor control applications. The
device is based on a 20 MHz fixed-point DSP core (ADSP-

2171) and a set of motor control peripherals including seven
analog input channels and a 12-bit three-phase PWM generator.
The device has two auxiliary 8-bit PWM channels and adds
expansion capability through the serial ports and an 8-bit digital
I/O port. The ADMC330 has internal 2K words program RAM,
and 1K words data RAM, which can be loaded from an external
device via the serial port. There are also 2K words of internal
program ROM, which includes a monitor that adds software
debugging features through the serial port.

The ADMC330 core combines the ADSP-2100 base architec­ture (three computational units, data address generators and a
program sequencer) with two serial ports, a programmable
timer, extensive interrupt capabilities and on-chip program and
data memory.

In addition, the ADMC330 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding and global interrupt masking, for increased
flexibility.

PROGRAM

ROM

2K 3 24

PROGRAM

RAM

2K 3 24

SERIAL PORTS

SPORT 0 SPORT 1

MEMORY

DATA

MEMORY

1K 3 16

TIMER

2 3 8-BIT

AUX

PWM

WATCH-

DOG

TIMER

ANALOG

INPUTS

8-BIT

PIO

12-BIT

3-PHASE

PWM

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

ADMC330–SPECIFICA TIONS

(VDD = 5 V 6 10%, GND = SGND = 0 V, TA = –408C to +858C, unless otherwise noted)

Parameter Min Typ Max Units Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER Charging Capacitor = 1000 pF

2.5 kHz Sample Frequency

Signal Input 0.3 3.2

1

V
Resolution 12 Bits No Missing Codes
Converter Linearity 2 4 Bits
Zero Offset 50 200 mV
Channel-to-Channel Comparator Match 25 mV
Comparator Delay 600 ns
Current Source 9.5 11 13.5 µA
Current Source Linearity 3 %

ELECTRICAL CHARACTERISTICS

Logic Low 0.8 V

V

IL

Logic High 2 V

V

IH

Low-Level Output Voltage 0.4 V IOL = 2 mA

V

OL

Low-Level Output Voltage (XTAL) 0.5 V IOL = 2 mA

V

OL

High-Level Output Voltage 4 V I

V

OH

Low-Level Input Current –10 µAV

I

IL

High-Level Input Current 10 µAV

I

IH

= 0.5 mA

OH

= 0 V

IN

= V

IN

DD

IDDSupply Current (Power-Down Mode) 5 mA
IDDSupply Current (Static) 60 mA

CLOCK

Input Clock (t

) 100 ns 10 MHz Clock Input (CLKIN)

CK

DSP Clock (tCK/2) 50 ns 20 MHz DSP Clock (CLKOUT)

REFERENCE VOLTAGE OUTPUT

Voltage Level 2.2 2.55 2.9 V 100 µA Load
Output Voltage Change T

12-BIT PWM TIMER

Counter Resolution 12

MIN

to T

MAX

20 mV

2

Bits
Edge Resolution 100 ns 10 MHz CLKIN
Programmable Deadtime Range 0 12.5 µs 10 MHz CLKIN
Programmable Deadtime Increments 200 ns 10 MHz CLKIN
Programmable Pulse Deletion Range 0 12.5 µs 10 MHz CLKIN
Programmable Pulse Deletion Increments 100 ns 10 MHz CLKIN
PWM Frequency Range 2.5 kHz 10 MHz CLKIN
PWMSYNC Pulsewidth (T

)2µs 10 MHz CLKIN

CRST

Gate Drive Chop Frequency Range 0.08 5 MHz 10 MHz CLKIN

AUXILIARY PWM TIMERS

Resolution 8 Bits
PWM Frequency 39 kHz 1/256 of 10 MHz CLKIN Clock

NOTES

1

Signal input max V = 3.5 if VDD = 5 V ± 5%.

2

Resolution varies with PWM switching frequency (10 MHz Clock), 25 kHz = 8 bits, 2.5 kHz = 12 bits.

Specifications subject to change without notice.

–2– REV. 0

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . .–0.3 V to +7.0 V

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to V

Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V

Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to V

DD
DD
DD
DD
DD

Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option

ADMC330BST –40°C to +85°C 20 MHz 80-Lead Plastic Thin Quad Flatpack (TQFP) ST-80

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC330 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ADMC330

–3–REV. 0

ADMC330

PIN FUNCTION DESCRIPTIONS

Pin Pin Pin
No. Type Name

1NC
2 I/P VAUX3
3 O/P REFOUT
4 SUP V

DD

5 GND GND
6 BIDIR PIO7
7 BIDIR PIO6
8 BIDIR PIO5

9 BIDIR PIO4
10 BIDIR PIO3
11 BIDIR PIO2
12 BIDIR PIO1
13 BIDIR PIO0
14 O/P AUX1
15 O/P AUX0
16 SUP V

DD

17 I/P PWMTRIP
18 GND GND
19 NC
20 NC

Pin Pin Pin
No. Type Name

21 NC
22 SUP V

DD

23 GND GND
24 NC
25 O/P PWMSYNC
26 O/P CL
27 O/P CH
28 O/P BL
29 O/P BH
30 O/P AL
31 O/P AH
32 NC
33 SUP V

DD

34 GND GND
35 GND GND
36 GND GND
37 GND GND
38 GND GND
39 NC
40 NC

PIN CONFIGURATION

80-Lead Plastic Thin Quad Flatpack (TQFP)

(ST-80)

Pin Pin Pin
No. Type Name

41 NC
42 GND GND
43 GND GND
44 I/P XTAL
45 I/P CLKIN
46 I/P PWMPOL
47 I/P RESET
48 GND GND
49 SUP V

DD

50 O/P CLKOUT
51 GND GND
52 O/P DT1
53 BIDIR TFS1
54 BIDIR RFS1
55 I/P DR1A
56 I/P DR1B
57 BIDIR SCLK1
58 BIDIR DT0
59 NC
60 NC

Pin Pin Pin
No. Type Name

61 NC
62 NC
63 BIDIR TFS0
64 BIDIR RFS0
65 BIDIR DR0
66 BIDIR SCLK0
67 SUP V

DD

68 GND GND
69 GND AGND
70 I/P CAPIN
71 O/P ICONST
72 GND SGND
73 I/P V1
74 I/P V2
75 I/P V3
76 I/P VAUX0
77 I/P VAUX1
78 I/P VAUX2
79 NC
80 NC

61

NC

62

NC

63

TFS0

64

RFS0

65

DR0

66

SCLK0

V

67

DD

68

GND

69

AGND

70

CAPIN

ICONST

71
72

SGND

73

V1

74

V2

75

V3

VAUX0

76

VAUX1

77
78

VAUX2

NC

79
80

NC

NC = NO CONNECT

NC

DT0

NC

SCLK1

DR1B

DR1A

60

59585756555453525150494847

RFS1

TFS1

DT1

GND

CLKOUT

ADMC330

TOP VIEW

(Not to Scale)

PIN 1
IDENTIFIER

2

3

1

NC

VAUX3

REFOUT

4

DD

V

5

GND

6

PIO7

7

PIO6

8

PIO5

9

PIO4

10

PIO3

11

PIO2

DD

V

12

PIO1

GND

13

PIO0

RESET

PWMPOL

46

15

14

AUX1

AUX0

XTAL

CLKIN
454443

16

17

DD

V

PWMTRIP

GND

18

GND

GND
42

19
NC

NC
41

20
NC

40

NC

39

NC

38

GND

37

GND

36

GND

35

GND

34

GND

33

V

32

NC

31

AH

30

AL

29

BH

28

BL

27

CH

26

CL

25

PWMSYNC

24

NC

23

GND
V

22

NC

21

DD

DD

–4– REV. 0

ADMC330

The ADMC330 operates with a 50 ns instruction cycle time.
Every instruction can execute in a single processor cycle.

The flexible architecture and comprehensive instruction set of
the ADMC330 allow the processor to perform multiple opera­tions in parallel. In one processor cycle the ADMC330 can:

• generate the next program address

• fetch the next instruction

• perform one or two data moves

• update one or two data address pointers

• perform a computational operation

This takes place while the processor continues to:

• receive and transmit data through the two serial ports

• decrement the timer

Independently the peripheral blocks can:

• generate three-phase PWM waveforms for a power inverter

• generate two signals using the 8-bit auxiliary PWM timers

• acquire four analog signals

• control eight digital I/O lines

• decrement the watchdog timer

ROM Code Functions

The ADMC330 has a 2K Boot ROM that contains the
following:

• Monitor Program:
Serial Boot Loader for OTP ROM or EEPROM
UART Debugger Interface and Loader

• Math Utilities/Tables:
Sine, cosine, tangent, inverse tangent, log, inverse log,
square root, 1/X, 1/(sine rms), unsigned division, Cartesian
to polar conversion, interpolation

The ADMC330 is similar to an ADSP-2172 in its booting se­quence. The MMAP and BMODE pins are tied high, which
enables the on-chip ROM and starts execution of the monitor
program on power-up or reset. The monitor program first at­tempts to boot load through SPORT1 from a serial memory
device. The loader uses a two-wire (data and clock) serial proto­col. The ADMC330 provides a serial clock to the device equal
to 1/20 of CLKOUT. Default input is from a Xilinx XC1765D
OTP ROM or Atmel AT17C65 EEPROM; other devices are
possible as long as they adhere to the loader protocol. If the
serial load is successful, the code that was downloaded is ex­ecuted at the start of user memory space.

Failing a synchronous boot load, the ADMC330 monitor switches
over to debug mode and waits for commands over SPORT1
from a UART. Debug mode uses a standard RS-232 protocol in
which only the data receive and transmit lines are used by the
ADMC330. This interface is used by the Visual DSP

®

Debugger,

but can also be used by UART devices for boot loading programs.
In addition to the monitor program, the ROM contains the

previously listed math utilities. These routines can be called
from user applications.

Development System

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup­ports the ADMC330. The system builder provides a high level
method for defining the architecture of systems under develop­ment. The assembler has an algebraic syntax that is easy to
program and debug. The linker combines object files into

Visual DSP is a registered trademark of Analog Devices, Inc.

–5–REV. 0

an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
MAKEPROM utility splitter generates PROM programmer
compatible files. The C Compiler, based on the Free Software
Foundation’s GNU C Compiler, generates ADMC330 assem­bly source code. The runtime library includes over 100 ANSI­standard mathematical and DSP-specific functions.

Low cost, easy-to-use hardware development tools include an
ADMC330-EVAL board and a windows based software debugger.
This debugger can be run with either the ADMC330-EVAL
board or the target system by communicating over a two-wire
asynchronous link to a PC.

FUNCTIONAL DESCRIPTION
ADMC330 Peripherals Overview

The ADMC330 set of peripherals was specifically developed to
address the requirements of variable speed control of ac induc­tion motors (ACIM) and electronically commutated synchro­nous motors (ECM). They are memory mapped to a block in
the DSP data memory space allowing single cycle read and/or
write to all peripheral registers. The operation of the peripherals
is synchronized to the DSP core by a clock HCLK, which is
derived from half of the DSP system clock.

Three-Phase PWM Generator

• 12-bit center-based PWM generator including program­mable deadtime and narrow pulse deletion.

• ECM crossover block.

• Output enable block.

• Hardwired output polarity control.

• External trip input.

• Pulsed PWM output capability for transformer coupled gate.

Analog I/O

• Two 8-bit PWM Output Timers—(Synthesized Analog
Output).

• Comparator based Analog Input Acquisition. Analog-to-digital
conversion is accomplished via 4-channel single slope ADC.

Digital I/O

• Eight bits of programmable digital I/O configurable as
interrupt sources.

THREE-PHASE PWM GENERATOR

The ADMC330 PWM controller is a self-contained program­mable waveform generator that produces PWM switching sig­nals for a three-phase power inverter. It includes a waveform
timing edge calculation unit which allows the generation of six
center based PWM signals based on only three duty cycle regis­ter updates every switching cycle. This minimizes the DSP
software required to service the PWM controller and frees up
processor time for the motor control law implementation. In the
default configuration it produces the three-phase center based
PWM waveforms required for three phase sinusoidal inverter.
However, it can also be configured for space vector modulation
schemes, or for controlling brushless dc motors (sometimes
known as electronically commutated motors). It also has func­tions which simplify the interface to the power inverter gate
drive and protection circuits.

The PWM controller is synchronized to the DSP core by the
HCLK which runs at half the DSP clock frequency giving wave­form resolution of 100 ns with a 20 MHz DSP clock. There are

ADMC330

four configuration registers (PWMTM, PWMDT, PWMPD
and PWMGATE), which define basic waveform parameters
such as the master switching frequency, deadtime, minimum
pulsewidth, and gate drive chopping. There PWM output sig­nals on the pins AH through CL are controlled by the input
registers (PWMCHA, PWMCHB, PWMCHC and PWMSEG)
and the control pins PWMTRIP and PWMPOL.

PWM Controller Overview

The PWM controller consists of three units: the center-based
timing unit, output control unit and the gate drive unit as shown
in Figure 1.

• The center-based PWM timing unit is the core of the PWM
controller and produces three pairs of complemented and
deadtime adjusted PWM waveforms as required for ac motor
control.

• The output control unit is a signal switching unit that selects
the appropriate PWM signals to be connected to the output
pins based on the bits set in the segment register (PWMSEG)
as may be required for ECM control or some space vector
modulation schemes.

• The gate drive block sets the logic polarity of the PWM “on”
signal according to the polarity of the PWMPOL pin to match
the gate drive circuit requirement. It can also modulate the
PWM “on” signal with a high frequency carrier (0.08 MHz–
5 MHz) if required for a transformer coupled gate drive circuit.

The DSP-based control algorithm can be synchronized to the
PWM generator by a hardware interrupt signal that is generated
at the end of every PWM switching cycle. This same PWMSYNC
signal is internally connected to the internal analog-to-digital
converter and is also available at an output pin. Finally, the
hardware PWMTRIP pin can be used to shut down the PWM
controller in the event of a fault.

Center-Based PWM Timing Unit

The center-based PWM timing unit is a programmable timer
that generates three pairs of fixed frequency PWM waveforms
suitable for controlling a three-phase power inverter. The unit
contains arithmetic circuits that calculate the PWM signal tim­ing edges from waveform parameters such as the PWM period,

dead time and the duty cycle for each inverter phase. There is
no extra DSP software overhead once the duty cycle for each
phase has been calculated and loaded into the PWM channel
registers.

The PWM Timing Unit produces three pairs of complemented
variable duty cycle waveforms symmetrical about common axes
of the form shown in Figure 2. They are complemented wave­forms, which means that for any pair of PWM waveforms (AH
and AL), they can never both be ON at the same time. They are
deadtime adjusted, which means that for any pair of PWM
waveforms, there is a delay between switching from being ON in
one waveform to being ON in the complemented waveform. A
pulse deletion function is implemented, which means that very
narrow PWM pulses will not be generated.

It is important to note that the deadtime compensation does not
take place on the boundary between consecutive PWM cycles.
Thus both the low side and high side devices can switch on
during the transition from a full-ON state to any other state.
This potentially volatile condition can be avoided by:

• Ensuring that the device never enters to the full-ON or full­OFF states, that is,

PWMCHx ≤ PWMTM –2 × (PWMDT + 1), with PWMPD = 0

• Using an external deadtime compensation circuit.

There is an active high PWMSYNC pulse produced at the be­ginning of each PWM cycle to synchronize the operation of
other peripherals with the switching of the power inverter. This
signal is also internally connected to the ADC block to initiate
conversions, and to the DSP core to generate an interrupt.
Figure 2 shows the center-based PWM operation.

The master switching frequency can range from 2.5 kHz to
25 kHz and is an integral fraction of HCLK clock frequency. It
is set by the value in the 12-bit PWMTM period register, which
sets the total number of clock cycles in a PWM cycle. The
required PWM period as a function of the desired master
switching frequency (f
quency (f

) is given by:

HCLK

) and peripheral system clock fre-

PWM

f

PWMTM =

HCLK

f

PWM

HCLK

PWMSYNC

INTERRUPT

SIGNALS

TIMING CONTROL

REGISTERS

PWMTM

PWMDT

PWMPD

CENTER-BASED

CLK SYNC RESET

REGISTERS

PWM TIMING

UNIT

CHANNEL

PWMCHA

PWMCHB

PWMCHC

OUTPUT CONTROL

REGISTER

PWMSEG

OUTPUT

CONTROL

UNIT

SYNC

Figure 1. PWM Controller Overview

–6– REV. 0

GATE CONTROL

GATE CONTROL

REGISTER

REGISTER

PWMGATE

GATE

DRIVE

UNIT

CLK

AH
AL
BH
BL
CH
CL

PWMPOL

PWMSYNC

PWMTRIP