Analog Devices ADMC300BST, ADMC300-PB, ADMC300 Datasheet

High Performance DSP-Based

a

TARGET APPLICATIONS
Industrial Drives, Servo Drives, Variable Speed Drives,

Electric Vehicles

FEATURES
25 MIPS Fixed-Point DSP Core

Single Cycle Instruction Execution (40 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units

ALU
Multiplier/Accumulator

Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer

Zero Overhead Looping

Conditional Instruction Execution
Two Independent Data Address Generators

Memory Configuration

4K  24-Bit Program Memory RAM
2K  24-Bit Program Memory ROM
1K  16-Bit Data Memory RAM

High-Resolution Multichannel ADC System

Five Independent 16-Bit Sigma-Delta ADCs
76 dB SNR Typical (ENOB > 12 Bits)
Arranged in Two Independently Clocked Banks
Differential or Single-Ended Inputs
Programmable Sample Frequency to 32.5 kHz

Motor Controller

ADMC300

Flexible Synchronization of ADC and PWM Subsystems
Independent Offset Calibration for Each Channel
Two Dedicated ADC Interrupts
Internal 2.5 V Reference
Three Multiplexer Control Pins for External Expansion
Hardware or Software Convert Start
Individual Power-Down for Each Bank

Three-Phase PWM Generation Subsystem

16-Bit Dedicated PWM Generator
Edge Resolution to 40 ns
Programmable Dead Time
Programmable Minimum Pulsewidth
Double Update Mode Allows Duty Cycle

Adjustment on Half Cycle Boundaries
Special Features for Brushless DC Motors
Hardwired Polarity Control
External Dedicated Asynchronous Shutdown Pin

(PWMTRIP)
Additional Shutdown Pins in I/O System
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Transparent Transition to Overmodulation

Range with Duty Cycles of 100%

Programmable Interrupt Controller Manages Priority

and Masking of 11 Peripheral Interrupts

(Continued on Page 7)

FUNCTIONAL BLOCK DIAGRAM

ADSP-2100 BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 2

DAG 1

PROGRAM MEMORY ADDRESS BUS

DATA MEMORY ADDRESS BUS

PROGRAM MEMORY DATA BUS

DATA MEMORY DATA BUS

ARITHMETIC UNITS

ALU

MAC

PROGRAM

SEQUENCER

SHIFTER

PROGRAM

ROM

2K  24

PROGRAM

RAM

4K  24

SERIAL PORTS

SPORT 0

SPORT 1

56

MEMORY

DATA

RAM

1K  16

INTERVAL

TIMER

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

MOTOR CONTROL

PERIPHERALS

PWM

PROGRAM

INTERRUPT

CONTROLLER

SIGMA-DELTA

WATCH-

DOG

TIMER

AUXILIARY

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

3212

EVENT

CAPTURE

TIMERS

PWM

GENERATION

7102

ADCs

ENCODER

INTERFACE

DIGITAL

I/O

ADMC300–SPECIFICATIONS

(VDD = AVDD = 5 V  10%, GND = AGND = 0 V, T

RECOMMENDED OPERATING CONDITIONS

CLKIN = 12.5 MHz, unless otherwise noted)

B Grade

Parameter Min Max Units

V
AV
T

DD

DD

AMB

Digital Supply Voltage 4.50 5.50 V
Analog Supply Voltage 4.50 5.50 V
Ambient Operating Temperature –40 +85 °C

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Max Unit

V

IH

V

IL

V

OH

V

OL

I

IH

I

IH

I

IH

I

IL

I

IL

I

IL

I

OZH

I

OZL

I

DD

I

DD

I

DD

I

DD

I

DD

I

DD

NOTES

1

Bidirectional pins: PIO0–PIO11, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.

2

Input only pins: PWMTRIP, PWMPOL, RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN.

3

Output pins: PWMSYNC, CL, CH, BL, BH, AL, AH, MUX0–MUX2, AUX0, AUX1, CLKOUT, DT0, DT1.

4

Input only pins: RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN.

5

Three-stateable pins: DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.

6

Current reflects device operating with no output loads.

7

Dynamic condition refers to continuous operation of the DSP core, ADC banks and PWM generation in single update mode with PWMTM = 0x0480, ADCDIVA =
ADCDIVB = 0x180. The encoder inputs are quiescent.

8

Disabled refers to powering down both ADC banks and the internal reference generation circuit by setting Bits 10, 11 and 12 of the ADCCTRL register. Current is
total current from AVDD supply.

Specifications subject to change without notice.

Hi-Level Input Voltage1,
Lo-Level Input Voltage1,
Hi-Level Output Voltage1,

Lo-Level Output Voltage1,

Hi-Level Input Current

Hi-Level PWMTRIP, PIO0–PIO11 Current @ VDD = Max, 100 µA

Hi-Level PWMPOL Current @ VDD = Max, 10 µA

Lo-Level Input Current

Lo-Level PWMTRIP, PIO0–PIO11 Current @ VDD = Max, 10 µA

Lo-Level PWMPOL Current @ VDD = Max, 100 µA

Hi-Level Three-State Leakage Current

Lo-Level Three-State Leakage Current

Digital Power Supply Current (Dynamic)6,
Analog Power Supply Current (Disabled)
Analog Power Supply Current (Ref Only) @ AVDD = VDD = Max 6.5 mA
Analog Power Supply Current (Ref + BankA) @ AVDD = VDD = Max 11.0 mA
Analog Power Supply Current (Ref + BankB) @ AVDD = VDD = Max 13.0 mA
Analog Power Supply Current (Ref + BankA/B) @ AVDD = VDD = Max 18.0 mA

2

2

3

3

4

4

5

5

7

8

@ VDD = Max 2.0 V
@ VDD = Min 0.8 V
@ VDD = Min, 2.4 V

= –1.0 mA

I

OH

= Min, VDD – 0.3 V

@ V

DD

I

= –0.1 mA

OH

@ VDD = Min, 0.4 V

= 2.0 mA

I

OL

@ VDD = Max, 10 µA
V

= VDD Max

IN

V

= VDD Max

IN

= VDD Max

V

IN

@ VDD = Max, 10 µA
V

= 0 V

IN

V

= 0 V

IN

V

= 0 V

IN

@ VDD = Max, 10 µA

= VDD Max

V

IN

@ VDD = Max, 10 µA
V

= 0 V

IN

@ VDD = Max 100 mA
@ AVDD = VDD = Max 100 µA

= –40C to +85C,

AMB

–2–

REV. B

ADMC300

ANALOG-TO-DIGITAL CONVERTER

(VDD = AVDD = 5 V  10%, GND = AGND = 0 V, V
CLKIN = 12.5 MHz, unless otherwise noted)

= 2.50 V, T

REFIN

= –40C to +85C,

AMB

Parameter Test Conditions Min Typ Max Unit

Signal-to-Noise Ratio
Total Harmonic Distortion
Common-Mode Rejection Ratio
Channel-Channel Crosstalk

1

(SNR) @VDD = 5.0 V, 72 76 dB

1

(THD) @ fS = 32.55 kHz, –70 dB

2

(CMRR) @ fIN = 1.017 kHz, –82 dB

3

ADCDIVn = 0x180, –76 dB
Gain Error V1–V5 = 4.0 V p-p 5 %
Gain V1N–V5N = V
V

IN

V

DIFF

V

OFFSET

f

MOD, MAX

f

S, MAX

Analog Input Range
Analog Input Voltage (Differential)
DC Offset Voltage
Maximum Sigma-Delta Modulator Rate ADCDIVA = 0x180 2.08 MHz

Maximum ADC Sample Rate

4

4

5

6

ADCDIVB = 0x180

ADCDIVA = 0x180 32.55 kHz

= 2.5 V 10,600 LSB/V

REFIN

0V

DD

VDD/2 V
55 mV

V

ADCDIVB = 0x180

V

REFIN

R

IN

NOTES

1

SNR measured with ADC channel configured in single-ended mode. SNR measurement does not include harmonic distortion, THD includes first six harmonics.
The effective number of bits (ENOB) is related to the SNR by SNR = 6.02 (ENOB) +1.76 dB. Input signal filtered at 1.5 kHz.

2

Input signal applied to both pins of input differential pair of ADC channel.

3

Input signal applied to four ADC channels, dc applied to fifth, measurement taken at fifth ADC channel.

4

Peak-peak input voltage in differential input configuration is half that in single-ended mode.

5

This offset may be corrected for, using the ADC calibration feature.

6

At maximum sigma-delta modulator rate of 2.08 MHz.

7

Input reference pins: REFINA, REFINB.

8

Analog signal input pins: V1–V5, V1N–V5N.

Specifications subject to change without notice.

Reference Input Voltage
Equivalent Input Resistance

7

8

2.4 2.5 2.6 V

25 kΩ

VOLTAGE REFERENCE

(VDD = AVDD = 5 V  10%, GND = AGND = 0 V, T
noted)

= –40C to +85C, CLKIN = 12.5 MHz, unless otherwise

AMB

Parameter Test Conditions Min Typ Max Unit

V

REF

Voltage Level 2.25 2.75 V
Source Current –100 µA

Power Supply Rejection Ratio (PSRR) –5 5 mV/V

Specifications subject to change without notice.

(V

PULSEWIDTH MODULATOR

= AVDD = 5 V  10%, GND = AGND = 0 V, T

DD

otherwise noted)

= –40C to +85C, CLKIN = 12.5 MHz, unless

AMB

Parameter Test Conditions Min Typ Max Unit

Counter Resolution

1

16 Bits

Edge Resolution Double Update Mode 40 ns

T

D

Programmable Dead Time 0 81.84 µs
Programmable Dead Time Increments 80 ns

T

MIN

f

PWM

T

SYNC

f

CHOP

NOTES

1

Resolution varies with PWM switching frequency, 191 Hz = 16 bits, 3.05 kHz = 12 bits, 48.8 kHz = 8 bits (12.5 MHz CLKIN) in single update mode.

Specifications subject to change without notice.

Programmable Pulse Deletion 0 40.92 µs
Programmable Deletion Increments 40 ns
PWM Frequency Range

1

191 Hz

PWMSYNC Pulsewidth 0.04 10.24 µs
Gate Drive Chop Frequency 0.0244 6.25 MHz

–3–REV. B

ADMC300–SPECIFICATIONS

(VDD = AVDD = 5 V  10%, GND = AGND = 0 V, T

ENCODER INTERFACE UNIT

otherwise noted)

Parameter Test Conditions Min Typ Max Unit

f

ENC, MAX

NOTES

1

Assumes perfect quadrature encoder signals.

Specifications subject to change without notice.

Maximum Encoder Pulse Rate

1

(VDD = AVDD = 5 V  10%, GND = AGND = 0 V, T

AUXILIARY PWM OUTPUTS

otherwise noted)

Parameter Test Conditions Min Typ Max Unit

Resolution 8 Bits

f

AUXPWM

Specifications subject to change without notice.

Switching Frequency 48.8 kHz

TIMING PARAMETERS

Parameter Min Max Unit

Clock Signals

t

is defined as 0.5 t

CK

to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns)
yields a 40 ns processor cycle (equivalent to 25 MHz). t

0.5 t

period should be substituted for all relevant timing parameters to obtain

CKI

specification value.
Example: t

= 0.5 tCK – 10 ns = 0.5 (40 ns) – 10 ns = 10 ns.

CKH

Timing Requirements:
t

CKI

t

CKIL

t

CKIH

CLKIN Period 80 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns

Switching Characteristics:
t

CKL

t

CKH

t

CKOH

CLKOUT Width Low 0.5 tCK – 10 ns
CLKOUT Width High 0.5 tCK – 10 ns
CLKIN High to CLKOUT High 0 20 ns

Control Signals

Timing Requirement:

t

RSP

RESET Width Low 5 t

PWM Shutdown Signals

Timing Requirements:

t

PWMTPW

t

PIOPWM

NOTES

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

Specifications subject to change without notice.

PWMTRIP Width Low 3 t
PIO Width Low 3 t

. The ADMC300 uses an input clock with a frequency equal

CKI

values within the range of

CK

t

CKI

= –40C to +85C, CLKIN = 12.5 MHz, unless

AMB

3.1 MHz

= –40C to +85C, CLKIN = 12.5 MHz, unless

AMB

1

CK

CK

CK

t

CKIH

ns

ns
ns

CLKIN

CLKOUT

t

CKIL

t

CKL

Figure 1. Clock Signals

–4–

t

CKOH

t

CKH

REV. B

ADMC300

WARNING!

ESD SENSITIVE DEVICE

Parameter Min Max Unit

Serial Ports

Timing Requirements:

t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics:

t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

SCDD

Specifications subject to change without notice.

SCLK Period 50 ns
DR/TFS/RFS Setup before SCLK Low 5 ns
DR/TFS/RFS Hold after SCLK Low 10 ns
SCLKIN Width 20 ns

CLKOUT High to SCLK

OUT

0.25 t

CK

0.25 tCK + 15 ns
SCLK High to DT Enable 0 ns
SCLK High to DT Valid 20 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 20 ns

OUT

DT Hold after SCLK High 0 ns
SCLK High to DT Disable 20 ns

CLKOUT

SCLK

RFS

TFS

RFS

TFS

DR

OUT

OUT

DT

IN

IN

t

CC

t

SCDV

t

SCDE

t

CC

t

SCStSCH

t

RD

t

RH

Figure 2. Serial Ports

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Supply Voltage (AV

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V

) . . . . . . . . . . . . . . . . .–0.3 V to +7.0 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range (Ambient) . . . –40°C to +85°C

t

SCK

t

SCP

t

SCP

t

SCDD

t

SCDH

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option

ADMC300BST –40°C to +85°C 25 MHz 80-Lead Plastic Thin Quad Flatpack (TQFP) ST-80
ADMC300-ADVEVALKIT Development Tool Kit
ADMC300-PB Evaluation/Processor Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. B

ADMC300

PIN FUNCTION DESCRIPTIONS

Pin Pin Pin
No. Type Name

1GNDGND
2I DR0
3 O DT0
4 I/O RFS0
5 I/O TFS0
6 I/O SCLK0
7 SUP V

DD

8GNDGND
9I PWMTRIP
10 O PWMSYNC
11 O CL
12 O CH
13 O BL
14 GND GND
15 SUP V

DD

16 O BH
17 O AL
18 O AH
19 O MUX0
20 O MUX1

Pin Pin Pin
No. Type Name

21 O MUX2
22 GND GND
23 SUP V

DD

24 O AUX0
25 O AUX1
26 I/O PIO0
27 I/O PIO1
28 I/O PIO2
29 I/O PIO3
30 I/O PIO4
31 GND GND
32 SUP V

DD

33 I/O PIO5
34 I/O PIO6
35 I/O PIO7
36 I/O PIO8
37 I/O PIO9/CONVST
38 I/O PIO10/ETU0
39 I/O PIO11/ETU1
40 GND AGND

PIN CONFIGURATION

80-Lead Plastic Thin Quad Flatpack (TQFP)

(ST-80)

Pin Pin Pin
No. Type Name

41 SUP AV

DD

42 I V5N
43 I V5
44 I V4N
45 I V4
46 I V3N
47 I V3
48 SUP AV

DD

49 GND AGND
50 GND AGND
51 SUP AV

DD

52 I REFINB
53 I REFINA
54 O VREF
55 I V2N
56 I V2
57 I V1N
58 I V1
59 SUP AV

DD

60 GND AGND

Pin Pin Pin
No. Type Name

61 GND GND
62 GND GND
63 I EIZP
64 I EIA
65 I EIB
66 I RESET
67 I PWMPOL
68 GND GND
69 I CLKIN
70 O XTAL
71 O CLKOUT
72 GND GND
73 SUP V

DD

74 I DR1A
75 I DR1B
76 O DT1
77 I/O RFS1/SROM
78 I/O TFS1
79 I/O SCLK1
80 SUP V

DD

GND

GND

EIZP

EIA

EIB

RESET

PWMPOL

GND

CLKIN

XTAL

CLKOUT

GND

V

DR1A

DR1B

DT1

RFS1/SROM

TFS1

SCLK1

V

DD

AV

AGND

59

60

61

62

63

64

65

66

67

68

69

70

71

72

DD

73

74

75

76

77

78

PIN 1

79

DD

IDENTIFIER

80

2

1

DR0

GND

V1

58

3

DT0

V1N

57

4

RFS0

V2

56

5

TFS0

V2N

545552

7

6

V

SCLK0

REFINB

REFINA

VREF

535051

ADMC300

TOP VIEW

(Not to Scale)

8

9

DD

GND

PWMTRIP

DD

AGND

AGND

AV

49

11

10

12

CL

CH

PWMSYNC

V4N

17

AL

V5

434442

18

AH

V5N

19

MUX0

DD

AV

41

20

MUX1

40

AGND

39

PIO11/ETU1

38

PIO10/ETU0

PIO9/CONVST

37

PIO8

36

PIO7

35

PIO6

34

33

PIO5

V

32

DD

GND

31

30

PIO4

PIO3

29

PIO2

28

PIO1

27

PIO0

26

AUX1

25

AUX0

24

V

23

DD

GND

22

MUX2

21

V3N

V3

AV

V4

46

48

45

47

14

15

13

16

DD

BL

BH

V

GND

DD

–6–

REV. B

ADMC300

(Continued from Page 1)

Flexible Encoder Interface Subsystem

Incremental Encoder Interface
Dedicated Three Pin Interface (EIA, EIB, EIZP)
16-Bit Quadrature Counter
Input Encoder Signals to 3.1 MHz
Optional Use of Zero Marker to Reset Counter
Single North Marker Mode—Permits Single

Reset of Counter On Only First Zero Marker
Status Bits to Read Encoder Inputs
Companion Encoder Event System for Accuracy
Enhancements at Low Speeds
Associated EIU Loop Timer Permits Regular,

Programmable Updating of All Encoder and

Event Timer Registers
EIU Timer Can Also Be Used as General Purpose

Timer If Not Linked to EIU Block

Peripheral I/O (PIO) Subsystem

12-Pin Digital I/O Port
Bit Configurable as Input or Output
Each Pin Configurable as Rising Edge, Falling Edge,
High Level or Low Level Interrupt
Four Dedicated PIO Interrupts for PIO0 to PIO3
One Combined Interrupt for PIO4 to PIO11
Each I/O Line Configurable as PWM Trip Source

Two 8-Bit Auxiliary PWM Outputs

Synthesized Analog Output
Fixed 48.8 kHz Operation
0 to 99.6% Duty Cycle

Event Timer Unit

Two Event Timer Channels with Dedicated Event
Capture Blocks
Permits Timing of Duty-Cycle, Period and Frequency
Configurable Event Definition
Dedicated Event Timer Interrupt
Event Timer Readable On-the-Fly

16-Bit Watchdog Timer
Programmable 16-Bit Interval Timer with Prescaler
Two Double Buffered Synchronous Serial Ports

Four Boot Load Protocols via SPORT1

2

PROM/SROM Booting

E

UART Booting (SCI Compatible) with Autobaud

Feature
Synchronous Master Booting with Autobaud Feature
Synchronous Slave Booting with Autobaud Feature

Debugger Interface via SPORT1 with Autobaud (UART

and Synchronous Supported)

ROM Utilities

Full Debugger for Program Development
Preprogrammed Math Functions
Preprogrammed Motor Control Functions—Vector

Transformations
80-Lead TQFP Package
Industrial Temperature Range –40C to +85C

GENERAL DESCRIPTION

The ADMC300 is a single-chip DSP-based controller, suitable
for high performance control of ac induction motors, permanent
magnet synchronous motors and brushless dc motors. The
ADMC300 integrates a 25 MIPS, fixed-point DSP core with a
complete set of motor control peripherals that permits fast,
efficient development of servo motor controllers.

The DSP core of the ADMC300 is the ADSP-2171, which is
completely code compatible with the ADSP-2100 DSP family
and combines three computational units, data address genera­tors and a program sequencer. The computational units com­prise an ALU, a multiplier/accumulator (MAC) and a barrel
shifter. The ADSP-2171 adds new instructions for bit manipu­lation, multiplication (X squared), biased rounding and global
interrupt masking. In addition, two flexible, double-buffered,
bidirectional, synchronous serial ports are included in the
ADMC300.

The ADMC300 provides 4K × 24-bit program memory RAM,
2K × 24-bit program memory ROM and 1K × 16-bit data
memory RAM. The program and data memory RAM can be
boot loaded through the serial port from either a serial SROM/

2

E

PROM, asynchronous (UART) connection, or synchro­nous connection. The program memory ROM includes a
monitor that adds software debugging features through the
serial port. In addition, a number of pre-programmed math­ematical and motor control functions are included in the
program memory ROM.

The motor control peripherals of the ADMC300 comprise a
high performance, five channel ADC system that uses sigma­delta conversion technology offering a typical signal-to-noise
ratio (SNR) of 76 dB, equivalent to 12 bits. In addition, a 16-bit
center-based PWM generation unit can be used to produce high
accuracy PWM signals with minimal processor overhead. The
ADMC300 also contains a flexible encoder interface unit for
position sensor feedback, two auxiliary PWM outputs, twelve
lines of digital I/O, a two-channel event capture system, a 16-bit
watchdog timer, a 16-bit interval timer and a programmable
interrupt controller that manages all peripheral interrupts.

–7–REV. B

ADMC300

DATA

ADDRESS

GENERATOR

#1

INPUT REGS

ALU

OUTPUT REGS

DATA

ADDRESS

GENERATOR

#2

INPUT REGS

OUTPUT REGS

MAC

INSTRUCTION

PROGRAM

SEQUENCER

16

R BUS

REGISTER

OUTPUT REGS

14

14

24

BUS

EXCHANGE

16

INPUT REGS

SHIFTER

PM ROM

2K  24

PM RAM

4K  24

CONTROL

LOGIC

PMA BUS

DMA BUS

PMD BUS

DMD BUS

TRANSMIT REG

RECEIVE REG

Figure 3. DSP Core Block Diagram

SERIAL
PORT 0

5

DM RAM
1K  16

COMPANDING

CIRCUITRY

TRANSMIT REG

RECEIVE REG

SERIAL
PORT 1

6

TIMER

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the
ADMC300, which is based on the fixed-point ADSP-2171. The
ADSP-2171 flexible architecture and comprehensive instruction
set allows the processor to perform multiple operations in paral­lel. In one processor cycle (40 ns with a 12.5 MHz CLKIN) the
DSP core can:

• Generate the next program address.

• Fetch the next instruction.

• Perform one or two data moves.

• Update one or two data address pointers.

• Perform a computational operation.

This all takes place while the processor continues to:

• Receive and transmit through the serial ports.

• Decrement the interval timer.

• Generate PWM signals.

• Convert the ADC input signals.

• Operate the encoder interface unit.

• Operate all other peripherals including the auxiliary PWM and
event timer subsystem.

The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported.
The MAC performs single-cycle multiply, multiply/add, multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormal­ization, and derive exponent operations. The shifter can be used
to efficiently implement numeric format control including floating­point representations.

The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa­tional units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC300 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain the loop.

–8–

REV. B

ADMC300

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and
program memory. Each DAG maintains and updates four
address pointers (I registers). Whenever the pointer is used to
access data (indirect addressing), it is post-modified by the
value in one of four modify (M) registers. A length value may
be associated with each pointer (L registers) to implement
automatic modulo addressing for circular buffers. The circular
buffering feature is also used by the serial ports for automatic
data transfers to and from on-chip memory. DAG1 generates
only data memory address but provides an optional bit-reversal
capability. DAG2 may generate either program or data memory
addresses, but has no bit-reversal capability.

Efficient data transfer is achieved with the use of five internal
buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

Program memory can store both instructions and data, permit­ting the ADMC300 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMC300 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.

The ADMC300 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.

The ADMC300 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP core interrupts include
serial port receive and transmit interrupts, timer interrupts,
software interrupts and external interrupts. The motor control
peripherals also produce interrupts to the DSP core.

The two serial ports (SPORTs) provide a complete synchro­nous serial interface with optional companding in hardware and
a wide variety of framed and unframed data transmit and re­ceive modes of operation. Each SPORT can generate an inter­nal programmable serial clock or accept an external serial clock.
Boot loading of both the program and data memory RAM of
the ADMC300 is through the serial port SPORT1.

A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n–1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt
is generated and the count register is reloaded from a 16-bit
period register (TPERIOD).

The ADMC300 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 40 ns
processor cycle (for a 12.5 MHz CLKIN). The ADMC300
assembly language uses an algebraic syntax for ease of coding
and readability. A comprehensive set of development tools
support program development. For further information on the
DSP core, refer to the ADSP-2100 Family User’s Manual, Third
Edition, with particular reference to the ADSP-2171.

Serial Ports

The ADMC300 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communication and
multiprocessor communication. Following is a brief list of capa­bilities of the ADMC300 SPORTs. Refer to the ADSP-2100
Family User’s Manual, Third Edition, for further details.

• SPORTs are bidirectional and have a separate, double­buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their
own serial clock internally.

• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted, with
either of two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 bits to 16
bits and provide optional A-law and µ-law companding ac-
cording to ITU (formerly CCITT) recommendation G.711.

• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An inter­rupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word, time-division multi­plexed, serial bitstream.

• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals.
The internally generated serial clock may still be used in this
configuration.

• SPORT1 is the default input for program and data memory
boot loading. The RFS1 pin can be configured internal to
the ADMC300 as an SROM/E

• SPORT1 has two data receive pins (DR1A and DR1B). The
DR1A pin is intended for synchronous boot loading from the
external SROM/E
the data receive pin for boot loading from an external UART
(SCI compatible) or synchronous connection, as the data
receive pin for the debugger communicating over the
debugger interface, or as the data receive pin for a general
purpose SPORT after booting. These two pins are internally
multiplexed onto the one DR1 port of the SPORT. The par­ticular data receive pin selected is determined by a bit in the
MODECTRL register.

2

PROM. The DR1B pin can be used as

2

PROM reset signal.

–9–REV. B

ADMC300

PIN FUNCTION DESCRIPTION

The ADMC300 is available in an 80-lead TQFP package. Table I
contains the pin descriptions.

Table I. Pin List

Pin #
Group of Input/
Name Pins Output Function

RESET 1 I Processor Reset Input.
SPORT0 5 I/O Serial Port 0 Pins (TFS0, RFS0,

DT0, DR0, SCLK0).

SPORT1 6 I/O Serial Port 1 Pins (TFS1,

RFS1, DT1, DR1A, DR1B,

SCLK1).
CLKOUT 1 O Processor Clock Output.
CLKIN, XTAL 2 I, O External Clock or Quartz Crystal

Connection Point.
PIO0–PIO11 12 I/O Digital I/O Port, External Con-

vert Start and Event Timer

Pins.
AUX0–AUX1 2 O Auxiliary PWM Outputs.
AH–CL 6 O PWM Outputs.
PWMTRIP 1 I PWM Trip Signal.
PWMPOL 1 I PWM Polarity Pin.
PWMSYNC 1 O PWM Synchronization Pin.
V1–V5 5 I Noninverting Inputs of the Dif-

ferential ADCs’ Input Amplifiers.
V1N–V5N 5 I Inverting Inputs of the Differen-

tial ADCs’ Input Amplifiers.
REFINA– 2 I Voltage reference inputs for

REFINB ADCs.
VREF 1 O Voltage Reference Output.
MUX0–MUX2 3 O Multiplexer Control Lines.
EIA, EIB, EIZP 3 I Encoder Interface Pins.
AV

DD

AGND 4 Analog Ground.
V

DD

GND 9

INTERRUPT OVERVIEW

4 Analog Power Supply.

6 Digital Power Supply.

Digital Ground.

The ADMC300 can respond to nineteen different interrupt
sources, eight of which are internal DSP core interrupts and
eleven interrupts from the motor control peripherals. The eight
DSP core interrupts comprise the peripheral (IRQ2), SPORT0
receive, SPORT0 transmit, SPORT1 receive (or IRQ0), SPORT1
transmit (or IRQ1), two software and the interval timer interrupts.
In addition, the motor control peripherals add eleven interrupts
that include two ADC, two PWM, five peripheral I/O, one en­coder interface and one event timer interrupt. The interrupts are
internally prioritized and individually maskable. All peripheral
interrupts are multiplexed into the DSP core through the pe­ripheral IRQ2 interrupt. The programmable interrupt controller
manages the masking and vector addressing of all eleven periph­eral interrupts. A detailed description of the operation of the
entire interrupt system of the ADMC300 is given later, after a
more detailed description of the various peripheral systems.

Windows is a registered trademark of Microsoft Corporation.

–10–

Memory Map

The ADMC300 has two distinct memory types; program
memory and data memory. In general, program memory con­tains user code and coefficients, while the data memory is used
to store variables and data during program execution. Both pro­gram memory RAM and ROM is provided on the ADMC300.
Program memory RAM is arranged in two noncontiguous 2K ×
24-bit blocks, one starting at address 0x0000 and the other at
0x1800. Program memory ROM is located at address 0x0800.
Data memory is arranged as a 1K × 16-bit block starting at
address 0x3800. The motor control peripherals are memory
mapped into a region of the data memory space starting at
0x2000. The complete program and data memory maps are
given in Tables II and III respectively.

Table II. Program Memory Map

Memory

Address Range Type Function

0x0000–0x005F RAM Interrupt Vector Table
0x0060–0x071F RAM User Program Space
0x0720–0x07DF RAM Reserved by Debugger
0x07E0–0x07FF RAM Reserved by Monitor
0x0800–0x0E20 ROM ROM Monitor
0xE21–0xFD6 ROM ROM Math and Motor

Control Utilities
0xFD7–0x0FFF ROM Reserved
0x1000–0x17FF Unused
0x1800–0x1FFF RAM User Program Space
0x2000–0x3FFF Unused

Table III. Data Memory Map

Memory

Address Range Type Function

0x0000–0x1FFF Unused
0x2000–0x20FF Memory Mapped Registers
0x2100–0x37FF Unused
0x3800–0x3B5F RAM User Data Space
0x3B60–0x3BFF RAM Reserved by Monitor
0x3C00–0x3FFF Memory Mapped Registers

ROM Code

The 2K × 24-bit block of program memory ROM starting at ad­dress 0x0800 contains a monitor function that is used to download
and execute user programs via the serial port. In addition, the
monitor function supports an interactive mode in which com­mands are received and processed from a host. An example of such
a host is the Windows

®

-based Motion Control Debugger that is
part of the software development system for the ADMC300. In
the interactive mode, the host can access both the internal DSP
and peripheral motor control registers of the ADMC300, read and
write to both program and data memory, implement breakpoints
and perform single-step and run/halt operation as part of the pro­gram debugging cycle.

In addition to the monitor function, the program memory ROM
contains a number of useful mathematical and motor control util­ities that can be called as subroutines from the user code. A com­plete list of these ROM functions is given in Table IV. The start
address of the function in the program memory ROM is also given.
Refer to the ADMC300 DSP Motor Controller Developer’s Reference
Manual for more details of the ROM functions.

REV. B

ADMC300

Table IV. ROM Utilities

Utility Address Function

PER_RST 0x07E4 Peripheral Reset.
UMASK 0x0E21 Limits Unsigned Value to Given

Range.

PUT_VECTOR 0x0E28 Facilitates User Setup of Vector

Table.

SMASK 0x0E35 Limits Signed Value to Given

Range.
ADMC_COS 0x0E55 Cosine Function.
ADMC_SIN 0x0E5C Sine Function.
ARCTAN 0x0E72 Arctangent Function.
RECIPROCAL 0x0E94 Reciprocal (1/x) Function.
SQRT 0x0EAA Square Root Function.
LN 0x0EE4 Natural Logarithm Function.
LOG 0x0EE7 Logarithm (Base 10) Function.
FLTONE 0x0F03 Fixed Point to Floating Point

Conversion.
FIXONE 0x0F08 Floating Point to Fixed Point

Conversion.
FPA 0x0F0C Floating Point Addition.
FPS 0x0F1B Floating Point Subtraction.
FPM 0x0F2B Floating Point Multiplication.
FPD 0x0F34 Floating Point Division.
FPMACC 0x0F55 Floating Point Multiply and

Accumulate.
PARK 0x0F77 Forward and Reverse Park

Transformation (Vector

Rotation).
REV_CLARK 0x0F8B Reverse Clark Transformation.
FOR_CLARK 0x0FA1 Forward Clark Transformation.
SDIVQINT 0x0FAB Unsigned Single Precision

Division (Integer).
SDIVQ 0x0FB4 Unsigned Single Precision

Division (Fractional).
EXIT 0x0FC6 Exit to Debugger after Running

User Program.

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMC300
with an external crystal and serial E

2

PROM for boot loading of

program and data memory RAM.

CLKOUT

ADMC300

RESET

XTAL

CLKIN

DR1A

SCLK1

RFS1/ SROM

20pF

12.5 MHz

20pF

DATA

CLK

RESET

SERIAL

2

E

PROM

Figure 4. Basic System Configuration

Clock Signals

The ADMC300 can be clocked by either a crystal or a TTL­compatible clock signal. The CLKIN input cannot be halted,

changed during operation or operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC300. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC300
uses an input clock with a frequency equal to half the instruc­tion rate; a 12.5 MHz input clock yields a 40 ns processor cycle
(which is equivalent to 25 MHz). Normally instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.

Because the ADMC300 includes an on-chip oscillator circuit,
an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in
Figure 4. A parallel-resonant, fundamental frequency, micro­processor-grade crystal should be used. A clock output signal
(CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency.

Reset

The RESET signal initiates a master reset of the ADMC300.
The RESET signal must be asserted during the power-up se­quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

DD

is ap­plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini­mum pulsewidth specification, t

RSP

.

If an RC circuit is used to generate the RESET signal, the use of
an external Schmitt trigger is recommended.

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis­ters and performs a full reset of all of the motor control periph­erals. When the RESET line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1.

Boot Loading

On power-up or reset, the ADMC300 is configured so that
execution begins at the internal PM ROM at address 0x0800.
This starts execution of the internal monitor function that first
performs some initialization functions and copies a default inter­rupt vector table to addresses 0x0000–0x005F of program memory
RAM. The monitor next attempts to boot load from an external
SROM or E

2

PROM on SPORT1 using the three wire connec-

tion of Figure 4. The monitor program first toggles the RFS1/
SROM pin of the ADMC300 to reset the serial memory device.
If an SROM or E

2

PROM is connected to SPORT1, data is

clocked into the ADMC300 at a rate CLKOUT/26. Both

–11–REV. B

ADMC300

program and data memory RAM can be loaded from the SROM/

2

E

PROM. After the boot load is complete, program execution
begins at address 0x0060. This is where the first instruction of
the user code should be placed.

If boot loading from an E

2

PROM is unsuccessful, the monitor
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea­ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:

• A UART boot loader such as a Motorola 68HC11 SCI port.

• A synchronous slave boot loader (the clock is external).

• A synchronous master boot loader (the ADMC300 provides

the clock).

• A UART debugger interface.

• A synchronous master debugger interface.

• A synchronous slave debugger interface.

With the debugger interface, the monitor enters interactive
mode in which it processes commands received from the
external device.

REFINA

DSP Control Registers

The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con­figured as a serial port when Bit 10 is set, or as flags and inter­rupt lines when this bit is cleared. For proper operation of the
ADMC300, all other bits in this register must be cleared (which
is their default).

The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC300, this register must always contain the value 0x8000
(which is the default).

The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC300 is shown at the end of the data sheet.

ANALOG-TO-DIGITAL CONVERSION SYSTEM

A functional block diagram of the ADC system of the ADMC300
is shown in Figure 5. The ADC system provides the high perfor­mance conversion required for precision applications. It integrates
five completely independent analog-to-digital converters based
on sigma-delta conversion technology. Each ADC channel may

REFINB

V1

V1N

V2

V2N

V3

V3N

V4

V4N

V5

V5N

CONVST(PIO9)

CALIBRATION

MULTIPLEXER

ADCCAL (4…0)

16-BIT 

16-BIT 

16-BIT 

16-BIT 

16-BIT 

ADC BANKA

ADC BANKB

UPDATE

ADC REGISTER

UPDATE CONTROL

ADC1 (15…0)

ADC2 (15…0)

ADC3 (15…0)

ADC4 (15…0)

ADC5 (15…0)

DSP DATA

MEMORY

ADCDIVA (11…6)
ADCDIVB (11…6)
ADCSYNC (6…0)

BUS

MUX0

MUX1

MUX2

MULTIPLEXER

CONTROL

ADCCTRL (15…0)

Figure 5. Functional Block Diagram of ADC System of ADMC300

–12–

INTERNAL

VOLTAGE
REFERENCE
GENERATOR

V

REF

REV. B

ADMC300

V

REF

0.1F

ADMC300

VREF

VxN

REFINA

REFINB

0.1F

be configured as either a differential or single-ended input for
maximum flexibility in interfacing to external sensors and inputs.
The sigma-delta converter consists of two stages, a modulator
and a sinc filter, that combine to produce a 16-bit conversion.
For each channel, signal-to-noise ratios of 76 dB may be achieved,
corresponding to greater than 12 bits of resolution from each

as the RC filter shown in Figure 6, which provides a more than
30 dB attenuation to signals above 1 MHz (3 dB at 34 kHz) is ade­quate. The additional antialiasing band limiting required by the
Nyquist criterion for the 32.5 kHz sampling rate (a cutoff of

16.25 kHz) is supplied by the high order sinc filter in the digital
domain.

converter. Input signals up to 16.27 kHz may be converted.

For maximum flexibility, the five ADCs are arranged as two

ADMC300

banks; ADC1 and ADC2 forming Bank A, and ADC3, ADC4
and ADC5 forming Bank B. The characteristics of each bank,
such as sampling rate, internal or external conversion, synchro­nization to the PWM block, operating modes, may be con­trolled independently. The ADC registers of each bank may be
loaded from an internal signal whose frequency may be pro­grammed as a precise fraction of the CLKIN frequency. Alter­natively, the ADCs may be updated by an external signal on

VIN + V

–VIN + V

REF

REF

100

0.0047F

100

0.047F

Vx

VxN

0.047F

the CONVST pin. There are two dedicated ADC interrupts;
one for each bank of converters that can be used to signal that
the ADCs of the particular bank have been updated.

The ADC system also contains a built-in calibration function
that may be used to null any offsets within the ADC converters.

REF

0.1F

REFINA

REFINB

V

Each ADC channel may be placed in the calibration state indi­vidually or in combination with other channels.

In addition, the ADC system provides three multiplexer control

Figure 6. Differential Configuration for ADC Input of
ADMC300

pins that may be used in conjunction with an external multi­plexer to permit external signal expansion.

ADMC300

There is a separate reference input for each bank of converters.
However, the ADMC300 also provides a reference output that
could be buffered and used as a reference source for either or

VIN + V

REF

100

0.047F

Vx

both banks.

Input Configuration

The input to each ADC may be applied to the ADMC300 in

VxN

either a single-ended or differential configuration. In many
cases, a single-ended configuration is easier to provide but the
differential connection permits the reduction of common-mode
noise from the input signal. Each ADC input may be config­ured for single-ended or differential inputs as appropriate,
completely independent of the other channels. Figure 6 illus-

V

REF

0.1F

REFINA

REFINB

trates a typical differential configuration for the inputs of one
ADC channel of the ADMC300. The input signals are applied
to pins Vx and VxN (for example V1 and V1N). For correct
operation and maximum input dynamic range, the inputs sig-

IN

REF

+ V

.

REF

,

nals should be centered on the reference voltage level, V
Therefore, the signal applied to the Vx pin should be V
where V

is the analog input voltage. The corresponding signal

IN

Figure 7. Single-Ended Configuration for ADC Input of
ADMC300

applied to the inverting terminal of the differential input, VxN,

+ V

is then –V

IN

ADC input is actually 2 V
The input RC combination of 100 Ω and 0.047 µF provides a

first-order low-pass antialiasing filter with a cutoff frequency of

so that the differential signal applied to the

REF

IN

.

34 kHz. An advantage to sigma-delta ADCs is that the initial
(analog) signal filtering required for antialiasing is much more
modest than that required by other ADCs. With the sigma-delta
ADC, the input filter needed for the analog signal only has to
cut off at one-half of the modulator frequency, rather than the
lower effective sampling frequency. For the ADMC300, the
modulator runs 64 times faster than the sampling frequency.
Thus for a 32.5 kHz sampling rate, the modulator frequency
is 2.08 MHz, meaning the needed cutoff for the analog input
signal is 1.04 MHz. Therefore, a simple first order filter, such

Figure 8. Connection of Internal Voltage Reference of
ADMC300

–13–REV. B