Analog Devices ADMC201AP Datasheet

a

Motion Coprocessor

ADMC201

FEATURES
Analog Input Block

11-Bit Resolution Analog-to-Digital (A/D) Converter
7 Single-Ended (SE) Analog Inputs

4 Simultaneously Sampled Analog Inputs
Expansion with 4 Multiplexed Inputs

3.2 ␮s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability

12-Bit PWM Timer Block

Three-Phase Center-Based PWM

1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown

Vector Transformation Block

12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations

2.9 ␮s Transformation Time

Programmable Digital I/O Port

6-Bit Configurable Digital I/O
Change of State Interrupt Support

DSP & Microcontroller Interface

12 Bit Memory Mapped Registers
Twos Complement Data Format

6.25 MHz to 25 MHz Operating Clock Range
68-Pin PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range

GENERAL DESCRIPTION

The ADMC201 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro­controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC201 provides the neces­sary motor control functions: analog current data acquisition,
vector transformation, digital inputs/outputs, and PWM drive
signals.

PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs

A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is

1.6 µs and conversion time per channel is 3.2 µs (using a 12.5 MHz
system clock).

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

RESET

WR

A0–3

RD
CS

IRQ

CLK

REFOUT

REFIN

CONVST

AUX

AUX0
AUX1
AUX2
AUX3

PWMSYNC

AP

BP

CP

STOP

EMBEDDED

CONTROL

SEQUENCER

INTERNAL

REFERENCE

U
V

W

A

B

C

11-BIT

A/D

CONVERTER

MULTIPLEXER

EXPANSION

BLOCK

12-BIT

PWM TIMER

BLOCK

D0–D11

DATABUS

CONTROL BUS

CONTROL

REGISTERS

VECTOR

TRANSFORMATION

BLOCK

PROG.

DIGITAL

I/O

PORT

PIO 0–5

Flexible Analog Channel Sequencing

The ADMC201 supports acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and
the data can be read in any order. The sampling and conversion
time for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).

Embedded Control Sequencer

The embedded control sequencer off-loads the DSP or micro­processor, reducing the instructions required to read analog
input channels, control PWM timers and perform vector trans­formations. This frees the host processor for performing control
algorithms.

Fast DSP/Microprocessor Interface

The high speed digital interface allows direct connection to 16-bit
digital signal processors and microprocessors. The ADMC201
has 12 bit memory mapped registers with twos complement
data format and can be mapped directly into the data memory
map of a DSP. This allows for a single instruction read and write
interface.

Integration

The ADMC201 integrates a four channel simultaneous sampling
analog-to-digital converter, four channel analog multiplexer,
analog reference, vector transformation, six digital inputs/outputs,
and three-phase PWM timers into a 68-pin PLCC. Integration
reduces cost, board space, power consumption, and design and
test time.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(VDD = +5 V ⴞ 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz;

ADMC201–SPECIFICATIONS

TA = –40ⴗC to +85ⴗC unless otherwise noted)

Parameter ADMC201AP Units Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

1

Resolution 11 Bits Twos Complement Data Format
Relative Accuracy ± 2 LSB max Integral Nonlinearity
Differential Nonlinearity ± 2 LSB max
Bias Offset Error ± 5 LSB max Any Channel
Bias Offset Match 4 LSB max Between Channels
Full-Scale Error ± 6 LSB max Any Channel
Full-Scale Error Match 4 LSB max Between Channels
Conversion Time/Channel 40 System CLK Cycles
Signal-to-Noise Ratio (SNR)

2

60 dB min fIN = 600 Hz Sine Wave, f

= 55 kHz, 600 Hz

SAMPLE

Channel-to-Channel Isolation

Two-/Three-Phase Mode –58 dB max Sine Wave Applied to Unselected Channels

Three-/Three-Phase Mode –55 dB max

ANALOG INPUTS

Input Voltage Level 0–5 Volts
Analog Input Current 100 µA max
Input Capacitance 10 pF typ

TRACK AND HOLD

Aperture Delay 200 ns max Any Channel
Aperture Time Delay Match 20 ns max Between Channels
SHA Acquisition Time 20 System CLK Cycles
Droop Rate 5 mV/ms max

REFERENCE INPUT

Voltage Level 2.5 V dc
Reference Input Current 50 µA max

REFERENCE OUTPUT

Voltage Level 2.5 Volts
Voltage Level Tolerance ± 5 % max Full Load
Drive Capability ± 200 µA max

LOGIC

V

IL

V

IH

V

OL

V

OH

0.8 V max

2.0 V min

0.4 V max I

4.5 V min I

= 400 µA, VDD = 5 V

SINK

= 20 µA, VDD = 5 V

SOURCE

Input Leakage Current 1 µA max
Three-State Leakage Current 1 µA max
Input Capacitance 20 pF typ

12-BIT PWM TIMERS

Resolution 12 Bits
Programmable Deadtime Range 0–10.08 µs
Programmable Deadtime Increments 2 System CLK Cycles 160 ns
Programmable Pulse Deletion Range 0–10.16 µs
Programmable Deletion Increments 1 System CLK Cycle 80 ns
Minimum PWM Frequency 1.5 kHz Resolution Varies with PWM Switching Frequency

(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits,
5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre­quencies are Available with Lower Resolution

VECTOR TRANSFORMATION Park & Clarke Transformation

Radius Error 0.7 % max
Angular Error 30 arc min max
Reverse Transformation Time 37 System CLK Cycles
Forward Transformation Time 40 System CLK Cycles

EXTERNAL CLOCK INPUT

Range 6.25–25 MHz If > 12.5 MHz, Then It Is Necessary to Divide Down

via SYSCTRL Register

INTERNAL SYSTEM CLOCK

Range 6.25–12.5 MHz

POWER SUPPLY CURRENT

I

DD

NOTES

1

Measurements made with external reference.

2

Tested with PWM Switching Frequency of 25 kHz.

Specifications subject to change without notice.

20 mA max

–2–

REV. B

ADMC201

(

)

Table I. Timing Specifications (VDD = 5 V, ⴞ 5%; TA = –4

0ⴗC to +85ⴗC)

Number Symbol Timing Requirements Min Max Units

1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
24 t

NOTE

1

All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).

clk CLK Period 40 160 ns

per

clk CLK Pulsewidth, High 20 ns

pwh

clk CLK Pulsewidth, Low 20 ns

pwl

csb_wrb CS Low before Falling Edge of WR 0ns

su

addr_wrb ADDR Valid before Falling Edge of WR 0ns

su

data_wrb DATA Valid before Rising Edge of WR 13 ns

su

wrb_data DATA Hold after Rising Edge of WR 4.5 ns

hd

wrb_addr ADDR Hold after Rising Edge of WR 4.5 ns

hd

wrb_csb CS Hold after Rising Edge of WR 4.5 ns

hd

1

wrb

pwl

1

wrb

pwh

wrb_clk_h

hd

wrb_clk_h

su

wrb_clk_l

su

clk_wrb_l

hd

csb_rdb CS Low before Falling Edge of RD 0ns

su

addr_rdb ADDR Valid before Falling Edge of RD 0ns

su

rdb_addr ADDR Hold after Rising Edge of RD 0ns

hd

rdb_csb CS Hold after Rising Edge of RD 0ns

hd

rdb RD Pulsewidth, Low 20 ns

pwl

rdb RD Pulsewidth, High 20 ns

pwh

rdb_clk_h RD Low before Rising Edge of CLK 7.5 ns

su

rdb_clk_h RD Low after Rising Edge of CLK 7.5 ns

hd

resetb RESET Pulsewidth, Low 2 × t

pwl

1

1

1

1

9

WR Pulsewidth, Low 20 ns
WR Pulsewidth, High 20 ns
WR Low after Rising Edge of CLK 7 ns
WR High before Rising Edge of CLK 7 ns
WR High before Falling Edge of CLK 10 ns
WR High after Falling Edge of CLK 10 ns

clk ns

per

Number Symbol Switching Characteristics Min Max Units

25 t
26 t
27 t
28 t

RESET

rdb_data DATA Valid after Falling Edge of RD 23 ns

dly

rdb_data DATA Hold after Rising Edge of RD 0ns

hd

_pio Digital I/O Pulsewidth, High 2 × t

pwh

_pio Digital I/O Pulsewidth, Low 2 × t

pwl

CLK

1

2

3

CLK

CS

Figure 1. Clock Input Timing

A0–A3

CLK

24

WR

DATA

Figure 2. Reset Input Timing

12

NOTE:
ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN
ONE SYSTEM CLOCK CYCLE

clk ns

per

clk ns

per

13

15

9

8

11

10

4

6

5

7

i.e., 0 WAIT STATES

14

Figure 3. Write Cycle Timing Diagram

REV. B

–3–

ADMC201

WARNING!

ESD SENSITIVE DEVICE

CLK

CS

A0–A3

RD

DATA

23

25

16

17

22

20

26

18

21

19

Figure 4. Read Cycle Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to V

Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V

Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to V

Part Temperature Package Package

DD

Number Range Description Option

DD

DD

ADMC201AP –40°C to +85°C 68-Pin PLCC P-68A

DD

DD

Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at
these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC201 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

PIN DESIGNATIONS

ADMC201

Pin Mnemonic Type Description

1 D9 BIDIR Data Bit 9
2 D10 BIDIR Data Bit 10
3 D11 BIDIR Data Bit 11, MSB
4 PIO0 BIDIR Programmable Digital I/O Bit 0
5 PIO1 BIDIR Programmable Digital I/O Bit 1
6 PIO2 BIDIR Programmable Digital I/O Bit 2
7 PIO3 BIDIR Programmable Digital I/O Bit 3
8 PIO4 BIDIR Programmable Digital I/O Bit 4
9 PIO5 BIDIR Programmable Digital I/O Bit 5
10 V

DD

11 A3 I/P Address Bit 3, MSB
12 A2 I/P Address Bit 2
13 A1 I/P Address Bit 1
14 A0 I/P Address Bit 0, LSB
15 NC No Connect
16 RESET I/P Chip Reset

17 CONVST I/P A/D Conversion Start
18 IRQ O/P Interrupt Request (Pull-Up Required)
19 V

DD

20 DGND GND Digital Ground
21 CLK I/P External Clock Input
22 WR I/P Write Select
23 RD I/P Output Enable/Read
24 CS I/P Chip Select
25 NC No Connect
26 V

DD

27 AGND GND Analog Ground
28 AGND GND Analog Ground
29 U I/P Analog Input U
30 V I/P Analog Input V
31 W I/P Analog Input W
32 SGND GND Analog Signal Ground
33 REFIN I/P Analog Reference Input
34 AUX3 I/P Auxiliary Analog Input 3
35 AUX2 I/P Auxiliary Analog Input 2
36 AUX1 I/P Auxiliary Analog Input 1
37 AUX0 I/P Auxiliary Analog Input 0

SUP +5 V Digital Power Supply

SUP +5 V Digital Power Supply

SUP +5 V Analog Power Supply

Pin Mnemonic Type Description

38 REFOUT O/P Internal 2.5 V Analog Reference
39 V

DD

SUP +5 V Digital Power Supply
40 DGND GND Digital Ground
41 DGND GND Digital Ground
42 DGND GND Digital Ground
43 DGND GND Digital Ground
44 V

DD

SUP +5 V Digital Power Supply
45 NC No Connect
46 DGND GND Digital Ground
47 STOP I/P PWM Timer Output Disable
48 PWMSYNC O/P PWM Synchronization Output
49 CP O/P PWM Timer Output C Prime
50 C O/P PWM Timer Output C
51 BP O/P PWM Timer Output B Prime
52 NC No Connect
53 B O/P PWM Timer Output B
54 AP O/P PWM Timer Output A Prime
55 A O/P PWM Timer Output A
56 DGND GND Digital Ground
57 DGND GND Digital Ground
58 DGND GND Digital Ground
59 V

DD

SUP +5 V Digital Power Supply
60 D0 BIDIR Data Bit 0, LSB
61 D1 BIDIR Data Bit 1
62 D2 BIDIR Data Bit 2
63 D3 BIDIR Data Bit 3
64 D4 BIDIR Data Bit 4
65 D5 BIDIR Data Bit 5
66 D6 BIDIR Data Bit 6
67 D7 BIDIR Data Bit 7
68 D8 BIDIR Data Bit 8

Pin Types Pin Types

I/P = Input Pin BIDIR = Bidirectional Pin
O/P = Output Pin SUP = Supply Pin
GND = Ground Pin

REV. B

10

V

DD

11

A3

12

A2

13

A1

14

A0

15

NC

16

RESET

17

CONVST

18

IRQ

19

V

DD

20

DGND

21

CLK

22

WR

23

RD

24

CS

25

NC

26

V

DD

NC = NO CONNECT

PIN CONFIGURATION

PIO3

PIO5

PIO2

PIO4

9618765 686766656463624321

PIO1

PIO0

D11

D10

D9

ADMC201

TOP VIEW

(Not to Scale)

27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42

U

V

AGND

W

AGND

SGND

AUX3

REFIN

AUX2

D7

D8

PIN 1
IDENTIFIER

AUX0

AUX1

D5

D6

DD

V

REFOUT

D4

DGND

D3

DGND

–5–

D2

D1

DGND

DGND

60

D0

59

V

58

DGND

57

DGND

56

DGND

55

A

54

AP

53

B

52

NC

51

BP

50

C

49

CP

48

PWMSYNC

47

STOP

46

DGND

45

NC

44

V

DD

DD