Datasheet ADM8839 Datasheet (Analog Devices)

Charge Pump Regulator

for Color TFT Panels

ADM8839

FEATURES
3 Voltages (+5 V, +15 V, –15 V) from

a Single 3 V Supply

Power Efficiency Optimized for Use

with TFT in Mobile Phones
Low Quiescent Current
Low Shutdown Current (<5 A)
Shutdown Function
Option to Use External LDO

APPLICATIONS
Hand-held Instruments
TFT LCD Panels
Cellular Phones

LDO_ON/OFF

SHDN

FUNCTIONAL BLOCK DIAGRAM

C5, 2.2␮F

CC

VOLTAGE

DOUBLER

LDO

VOLTAGE

REGULATOR

DOUBLE

VOLTAGE

TRIPLER

TRIPLE

VOLTAGE

INVERTER

GND

C1+

C1–

VOUT
LDO_IN

+5VOUT
+5VIN

C2+

C2–

C3+

C3–

+15VOUT

C4+

C4–

–15VOUT

ADM8839

OSCILLATOR

CONTROL

LOGIC

TIMING

GENERATOR

SHUTDOWN

CONTROL

V

DISCHARGE

C1, 2.2␮F

C6, 2.2␮F

+5V

C7, 2.2␮F

C2, 0.22␮F

C3, 0.22␮F

+15V

C8, 0.22␮F

C4, 0.22␮F

–15V

C9, 0.22␮F

GENERAL DESCRIPTION

The ADM8839 is a charge pump regulator used for color thin film
transistor (TFT) liquid crystal displays (LCDs). Using charge
pump technology, the device can be used to generate three
voltages (+5 V ± 2%, +15 V, –15 V) from a single 3 V supply.
These voltages are then used to provide supplies for the LCD
controller (5 V) and the gate drives for the transistors in the
panel (+15 V and –15 V). Only a few external capacitors are
needed for the charge pumps. An efficient low dropout (LDO)
voltage regulator ensures that the power efficiency is high and
provides a low ripple 5 V output. This LDO can be shut down
and an external LDO can be used to regulate the 5 V doubler
output and drive the input to the charge pump section that
generates the +15 V and –15 V outputs, if required by the user.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

The ADM8839 has a power save shutdown feature. The 5 V
output consumes the most power, so power efficiency is also
maximized on this output with an oscillator enabling scheme
(Green Idle™). This effectively senses the load current that is
flowing and turns on the charge pump only when charge needs
to be delivered to the 5 V pump doubler output.

The ADM8839 is fabricated using CMOS technology for minimal
power consumption. The part is packaged in a 20-lead LFCSP
(lead frame chip scale package).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(VCC = 3 V – 10%, 40%; TA = –40C to +85C; C1, C5, C6, C7 = 2.2 F; C2, C3,

ADM8839–SPECIFICATIONS

C4, C8, C9 = 0.22 F; unless otherwise noted.)

Parameter Test Conditions Min Typ Max Unit

INPUT VOLTAGE, V

CC

SUPPLY CURRENT, I

CC

Unloaded 250 500 ␮A

2.7 4.2 V

Shutdown Mode, TA = 25°C 5 ␮A

+5 V OUTPUT

Output Voltage IL = 10 ␮A to 8 mA 4.9 5.0 5.1 V
Output Current 58 mA
Output Ripple 8 mA Load 10 mV p-p
Transient Response IL Stepped from 10 ␮A to 8 mA 5 ␮s

+15 V OUTPUT

Output Voltage I

= 1 ␮A to 150 ␮A 14.0 15.0 16.0 V

L

Output Current 1 150 ␮A
Output Ripple IL = 100 ␮A50mV p-p

–15 V OUTPUT

Output Voltage I

= –1 ␮A to –150 ␮A –16.0 –15.0 –14.0 V

L

Output Current –150 –1 ␮A
Output Ripple IL = –100 ␮A50mV p-p

POWER EFFICIENCY R5V

Load = 5 mA, 82 %

OUT

⫾15 V Load = ⫾150 ␮A,
V

= 3.0 V

CC

CHARGE PUMP FREQUENCY 60 100 140 kHz
CONTROL PINS, SHDN

Input Voltage, V

SHDN

SHDN Low = Shutdown Mode 0.3 ⫻ V
SHDN High = Normal Mode 0.7 ⫻ V

CC

CC

V
V

Digital Input Current ⫾1 ␮A
Digital Input Capacitance* 10 pF

LDO_ON/OFF

Input Voltage Low = External LDO 0.3 ⫻ V

High = Internal LDO 0.7 ⫻ V

CC

CC

V
V

Digital Input Current ⫾1 ␮A
Digital Input Capacitance* 10 pF

*Guaranteed by design. Not 100% production tested.

Specifications are target values and are subject to change without notice.

TIMING SPECIFICATIONS

(VCC = 3 V, TA = 25C; C1, C5, C6, C7 = 2.2 F; C2, C3, C4, C8, C9 = 0.22 F.)

Parameter Test Conditions/Comments Min Typ Max Unit

POWER-UP SEQUENCE

+5 V Rise Time, t

R5V

+15 V Rise Time, t
–15 V Fall Time, t

FM15V

R15V

10% to 90%, Figure 1 250 ␮s
10% to 90%, Figure 1 3 ms
90% to 10%, Figure 1 3 ms

Delay between –15 V Fall

and +15 V, t

DELAY

Figure 1 600 ␮s

POWER-DOWN SEQUENCE

+5 V Fall Time, t
+15 V Fall Time, t
–15 V Rise Time, t

Specifications are subject to change without notice.

F5V

F15V

RM15V

90% to 10%, Figure 1 35 ms
90% to 10%, Figure 1 10 ms
10% to 90%, Figure 1 20 ms

REV. A–2–

ADM8839

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.0 V

THERMAL CHARACTERISTICS

20-Lead LFCSP Package:

= 31°C/W

␪

JA

Input Voltage on Digital Inputs . . . . . . . . . . . –0.3 V to +6.0 V

Output Short-Circuit Duration to GND . . . . . . . . . . . . .10 sec

ORDERING GUIDE

Output Voltage

+5 V Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7.0 V

–15 V Output . . . . . . . . . . . . . . . . . . . . . . . . –17 V to +0.3 V

+15 V Output . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

Model Temperature Range Package Option

ADM8839ACP –40°C to +85°C CP-20

Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mW

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM8839 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A

–3–

ADM8839

PIN CONFIGURATION

17 15VOUT

18 GND

19 C1

20 C1

16 C4

VCC 1

VOUT 2

LDO_IN 3

5VOUT 4

5VIN 5

PIN 1
INDICATOR

ADM8839

TOP VIEW

SHDN 7

LDO_ON/OFF 6

8

V

CC

GND 9

15 C4
14 C2
13 C2
12 C3
11 C3

15VOUT 10

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1V

CC

Positive Supply Voltage Input. Connect this pin to the 3 V supply with a 2.2 µF decoupling capacitor.

2 VOUT Voltage Doubler Output. This was derived by doubling the 3 V supply. A 2.2 µF capacitor to

ground is required on this pin.

3 LDO_IN Voltage Regulator Input. The user may bypass this circuit by using the LDO_ON/OFF pin.

4 +5VOUT 5 V Output. This was derived by doubling and regulating the 3 V supply. A 2.2 µF capacitor

to ground is required on this pin to stabilize the regulator.

5 +5VIN 5 V Input. This is the input to the voltage tripler and inverter charge pump circuits.
6 LDO_ON/OFF Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of

the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge
pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler
output. The output of this LDO is then fed back into the voltage tripler and inverter circuits of
the ADM8839.

7 SHDN Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down the timing

generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus
driving them to 0 V.

8V

CC

Connect this pin to VCC.

9GND Connect this pin to GND.

10 +15VOUT 15 V Output. This was derived by tripling the 5 V regulated output. A 0.22 µF capacitor

is required on this pin.

11, 12 C3–, C3+ External capacitor C3 is connected between these pins. A 0.22 µF capacitor is recommended.

13, 14 C2–, C2+ External capacitor C2 is connected between these pins. A 0.22 µF capacitor is recommended.

15, 16 C4–, C4+ External capacitor C4 is connected between these pins. A 0.22 µF capacitor is recommended.

17 –15VOUT –15 V Output. This was derived by tripling and inverting the 5 V regulated output. A 0.22 µF

capacitor is required on this pin.

18 GND Device Ground.

19, 20 C1–, C1+ External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended.

REV. A–4–

LDO O/P VOLTAGE – V

LOAD CURRENT – mA

LDO POWER EFFICIENCY – %

75

76

77

78

79

80

81

84

82

31578246

83

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

DEVICE AT +25C

DEVICE AT –40C

Typical Performance Characteristics–ADM8839

DEVICE AT +85C

REV. A

4.70

3.12.7 3.5 3.92.9 3.3 3.7 4.1 4.2
SUPPLY VOLTAGE – V

TPC 1. LDO O/P Voltage Variation
over Temperature and Supply

5.020

5.015

5.010

5.005

LDO O/P VOLTAGE – V

5.000

4.995
20 468135 7

I

– mA

LOAD

TPC 2. LDO O/P Voltage vs. Load Current

100

90

80

70

60

50

+15V/–15V POWER EFFICIENCY – %

40

30

3010 50 70 1009020 40 60 80

I

– A

LOAD

TPC 3. +15 V/–15 V Power Efficiency vs. Load Current

–5–

TPC 4. LDO Power Efficiency vs. Load Current,
V

= 3 V

CC

400

350

300

250

SUPPLY CURRENT – A

200

150

3.12.7 3.5 3.92.9 3.3 3.7 4.1 4.2

SUPPLY VOLTAGE – V

TPC 5. Supply Current vs. Supply Voltage

15.1

15.0

14.9

14.8

14.7

14.6

14.5

14.4

OUTPUT VOLTAGE – V

14.3

14.2

14.1
500 100 150 200

–15V AT 25C

I

LOAD

+15V AT 25C

– A

TPC 6. +15 V/–15 V Output Voltage vs. Load
Current, Typical Configuration

ADM8839

+15V OUTPUT

5VOUT

–15V OUTPUT

TPC 7. +15 V and –15 V Outputs at Power-Up

V

RIPPLE (DOUBLER OUTPUT RIPPLE)

OUT

LDO OUTPUT RIPPLE

RIPPLE

V

CC

LOAD ENABLE

5V OUTPUT

TPC 10. Output Transient Response for
Maximum Load Current

+15V OUTPUT

–15V OUTPUT

TPC 8. Output Ripple on LDO (5 V Output)

LOAD DISABLE

5V OUTPUT

TPC 9. 5 V Output Transient Response,
Load Disconnected

5VOUT

TPC 11. +15 V and –15 V Outputs at Power-Down

REV. A–6–

POWER SEQUENCING

In order for the TFT panel to power up correctly, the gate drive
supplies must be sequenced such that the –15 V supply is up
before the +15 V supply. The ADM8839 controls this sequence.
When the device is turned on (a logic high on SHDN), the
ADM8839 allows the –15 V output to ramp immediately but
holds off the +15 V output. It continues to do this until the
negative output has reached –3 V. At this point, the positive
output is enabled and allowed to ramp to +15 V. This sequence
is highlighted in Figure 1.

V

CC

SHDN

t

R5V

+5V

+15V

–15V

90%

10%

t

FM15V

10%

t

DELAY

90%

10%

90%

–3V

t

R15V

t

F5V

t

F15V

t

RM15V

Figure 1. Power Sequence

TRANSIENT RESPONSE

The ADM8839 features extremely fast transient response, mak­ing it very suitable for fast image updates on TFT LCD panels.
This means that even under changing load conditions, there is
still very effective regulation of the 5 V output. TPCs 9 and 10
show how the 5 V output responds when a maximum load is
dynamically connected and disconnected. Note that the output
settles within 5 µs to less than 1% of the output level.

BOOSTING THE CURRENT DRIVE OF THE 15 V SUPPLY

The ADM8839 ⫾15 V output can deliver 150 µA of current in
the typical configuration, as shown in Figure 2. It is also pos­sible to draw 100 µA from the +15 V output and 200 µA from
the –15 V output, or vice versa. It is possible to draw only a
maximum of 300 µA combined from both the +15 V and the
–15 V outputs at any time (see Figure 3). In this configuration,
+5VOUT (Pin 4) is connected to +5VIN (Pin 5), as shown in
the Functional Block Diagram.

C5, 2.2F

CC

VOLTAGE

DOUBLER

LDO

VOLTAGE

REGULATOR

DOUBLE

VOLTAGE

TRIPLER

TRIPLE

VOLTAGE

INVERTER

GND

LDO_ON/OFF

SHDN

ADM8839

OSCILLATOR

CONTROL

LOGIC

TIMING

GENERATOR

SHUTDOWN

CONTROL

V

DISCHARGE

Figure 2. Typical Configuration

15.1

15.0

14.9

OUTPUT VOLTAGE – V

14.8

14.7

14.6

14.5

14.4

14.3

14.2

14.1
500 100 150 200

I

+15V AT 25C

–15V AT 25C

– A

LOAD

Figure 3. +15 V/–15 V Output Voltage vs. Load
Current, Typical Configuration

ADM8839

C1+

C1, 2.2F

C1–

VOUT
LDO_IN

C6, 2.2F

+5VOUT

+5VIN

C2+

C2–

C3+

C3–

+15VOUT

C4+

C4–

–15VOUT

C7, 2.2F

C2, 0.22F

C3, 0.22F

C8, 0.22F

C4, 0.22F

C9, 0.22F

+5V

+15V

–15V

REV. A

–7–

ADM8839

S

It is possible to configure the ADM8839 to supply up to 400 µA
on the ± 15 V outputs by changing its configuration slightly, as
shown in Figure 4.

C5, 2.2␮F

V

OSCILLATOR

LDO_ON/OFF

GENERATOR

SHUTDOWN

HDN

ADM8839

CONTROL

LOGIC

TIMING

CONTROL

CC

DISCHARGE

GND

VOLTAGE
DOUBLER

LDO

VOLTAGE

REGULATOR

DOUBLE

VOLTAGE

TRIPLER

TRIPLE

VOLTAGE

INVERTER

C1+

C1–

VOUT
LDO_IN

+5VOUT

+5VIN

C2+

C2–

C3+

C3–

+15VOUT

C4+

C4–

–15VOUT

C1, 2.2␮F

C2, 0.22␮F

C3, 0.22␮F

C8, 0.22␮F

C4, 0.22␮F

C9, 0.22␮F

CURRENT BOOST

CONFIGURATION

CONNECTION

C6, 2.2␮F

+5V

C7, 2.2␮F

+15V

–15V

The configuration in Figure 4 can supply up to 400 µA of current
on both the +15 V and the –15 V outputs. If the load on the
± 15 V does not draw any current, the voltage on the ±15 V out­puts can rise up to ±16.5 V (see Figure 5). In this configuration,
VOUT (Pin 2) is connected to +5VIN (Pin 5).

17.0

16.5

16.0

15.5

15.0

OUTPUT VOLTAGE – V

14.5

14.0
0 100 200 300 400 500

+15V AT 25ⴗC

–15V AT 25ⴗC

I

– ␮A

LOAD

Figure 5. +15 V/–15 V Output Voltage vs. Load
Current, Current Boost Configuration

C03075–0–2/03(A)

Figure 4. Current Boost Configuration

20-Lead Leadframe Chip Scale Package [LFCSP]

4.0

BSC SQ

PIN 1

INDICATOR

1.00

0.90

0.80

SEATING

PLANE

12 MAX

TOP

VIEW

0.50
BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

OUTLINE DIMENSIONS

4 ⫻ 4 mm Body

(CP-20)

Dimensions shown in millimeters

0.60

MAX

0.60

1.00 MAX

0.65 NOM

0.20
REF

3.75

BSC SQ

0.05

0.02

0.00

MAX

0.75

0.55

0.35

COPLANARITY

15

11

0.08

16

BOTTOM

10

VIEW

0.30

0.23

0.18

20

1

2.25

2.10 SQ

1.95

5

6

PRINTED IN U.S.A.

Revision History

2/03 – Data Sheet Changed from Rev. 0 to Rev. A

Changed SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

–8–