Datasheet ADM8690, ADM8691 Datasheet (ANALOG DEVICES)

Microprocessor

www.BDTIC.com/ADI

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

FEATURES

Upgrade for ADM690 to ADM695, MAX690 to MAX695
Specified over temperature
Low power consumption (0.7 mW)
Precision voltage monitor
Reset assertion down to 1 V V

CC

Low switch on resistance 0.7 Ω normal, 7 Ω in backup
High current drive (100 mA)
Watchdog timer: 100 ms, 1.6 s, or adjustable
400 nA standby current
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
Available in TSSOP package

APPLICATIONS

Microprocessor systems
Computers
Controllers
Intelligent instruments
Automotive systems

PRODUCT HIGHLIGHTS

The ADM8690, ADM8692, and ADM8694 are available in
8-lead, PDIP packages and provide:

1. P

ower-on reset output during power-up, power-down, and

RESET

brownout conditions. The
operational with V

2. B

attery backup switching for CMOS RAM, CMOS

as low as 1 V.

CC

microprocessor, or other low power logic.

reset pulse if the optional watchdog timer has not been

3. A

toggled within a specified time.

4. A 1.3 V t

hreshold detector for power-fail warning, low battery

detection, or to monitor a power supply other than 5 V.

The ADM8691, ADM8693, and ADM8695 are available in 16-lead

nd small outline packages (including TSSOP) and

PDIP a
provide three additional functions:

output remains

V

BATT

V

WATCHDOG
INPUT (WDI)

POWER FAIL

INPUT (PFI)

V

BATT

V

CE

OSC IN

OSC SEL

WATCHDOG
INPUT (WDI)

POWER FAIL

INPUT (PFI)

Supervisory Circuits

FUNCTIONAL BLOCK DIAGRAMS

CC

1

4.65V

WATCHDOG

TRANSITI ON DETECT OR

(1.6s)

1.3V

1

VOLTAG E DETECTO R = 4.65V (ADM8690, ADM8694)

4.40V (ADM8692)

2

RESET PULSE WIDT H = 50ms (AD8690, ADM8692)

200ms (ADM8694)

Figure 1. ADM8690/ADM8692/ADM8694

CC

IN

1

4.65V

RESET AND
WATCHDOG

TIME BASE

WATCHDOG

TRANSIT ION DETE CTOR

1.3V

1

VOLTAG E DETECT OR = 4.65V (ADM8691, ADM86 95)

Figure 2. ADM8691/ADM8693/ADM8695

GENERATO R

BATT ON

RESET

GENERATOR

4.40V (ADM8693)

RESET

ADM8690/
ADM8692/

ADM8694

WATCHDOG

2

ADM8691/
ADM8693/
ADM8695

TIMER

V

OUT

RESET

POWER FAIL
OUTPUT (PFO)

V

OUT

CE

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

00093-001

00093-002

rite protection of CMOS RAM or EEPROM.

1. W

djustable reset and watchdog timeout periods.

2. A

3. S

eparate watchdog timeout, backup battery switchover, and

low V

status outputs.

CC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

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TABLE OF CONTENTS

Features.............................................................................................. 1

Power-Fail Warning Comparator............................................. 13

Applications....................................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Circuit Information........................................................................ 10

Battery Switchover Section........................................................ 10

Power-Fail

Watc h d og T i me r

Watc h d og O utp u t (

RESET

Output......................................................... 10

RESET

............................................................ 11

WDO

) ........................................................12

Application Information................................................................ 14

Increasing the Drive Current.................................................... 14

Using a Rechargeable Battery for Backup............................... 14

Adding Hysteresis to the Power-Fail Comparator................. 14

Monitoring the Status of the Battery ....................................... 14

Alternate Watchdog Input Drive Circuits............................... 15

Typical Applications....................................................................... 16

ADM8690, ADM8692, and ADM8694 ................................... 16

ADM8691, ADM8693, and ADM8695 ................................... 16

RESET

Output ............................................................................ 16

Power-Fail Detector ................................................................... 17

RAM Write Protection............................................................... 17

Watchdog Timer......................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

CE

Gating and RAM Write Protection

(ADM8691/ADM8693/ADM8695)......................................... 12

REVISION HISTORY

9/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings....................................... 6

Updated Ordering Guide............................................................... 20

2/97—Revision 0: Initial Version

Rev. A | Page 2 of 20

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GENERAL DESCRIPTION

The ADM869x family of supervisory circuits offers complete
single- chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include microprocessor reset, backup battery switchover,
watchdog timer, CMOS RAM write protection, and power
failure warning. The complete family provides a variety of
configurations to satisfy most microprocessor system
requirements.

The ADM869x family is fabricated using an advanced epitaxial
CMOS p

Table 1. Product Selection Guide

Part
Number

ADM8690 50 ms 4.65 V 1.6 s Yes No No
ADM8691 50 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8692 50 ms 4.4 V 1.6 s Yes No No
ADM8693 50 ms or ADJ 4.4 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8694 200 ms 4.65 V 1.6 s Yes No No
ADM8695 200 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes

rocess combining low power consumption (0.7 mW),

Nominal
Reset Time

Nominal VCC Reset
Threshold

Nominal Watchdog
Timeout Period

extremely fast chip enable gating (3 ns), and high reliability.
RESET

assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need of an external pass transistor.

See Tab le 1 for a product selection guide listing the characteristics
o

f each device in the ADM869x family. To place an order, use

the Ordering Guide provided as the last section of this data sheet.

Battery Backup
Switching

Base Drive
Ext PNP

Chip Enable
Signals

Rev. A | Page 3 of 20

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SPECIFICATIONS

VCC = full operating range, V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

BATTERY BACKUP SWITCHING

VCC Operating Voltage Range

ADM8690, ADM8691, ADM8694, ADM8695 4.75 5.5 V
ADM8692, ADM8693 4.5 5.5 V

V

Operating Voltage Range

BATT

ADM8690, ADM8691, ADM8694, ADM8695 2.0 4.25 V
ADM8692, ADM8693 2.0 4.0 V

V

Output Voltage VCC − 0.005 VCC − 0.0025 V I

OUT

V
V

in Battery Backup Mode V

OUT

Supply Current (Excludes I
Supply Current in Battery Backup Mode 0.4 1 µA VCC = 0 V, V
Battery Standby Current 5.5 V > VCC > V

+ = Discharge, − = Charge −0.1 +0.02 µA TA = 25°C
Battery Switchover Threshold 70 mV Power-up
VCC – V

50 mV Power-down

BATT

Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V I
BATT ON Output Short-Circuit Current 55 mA BATT ON = V

0.5 2.5 25 µA BATT ON = 0 V source current

RESET AND WATCHDOG TIMER

Reset Voltage Threshold

ADM8690, ADM8691, ADM8694, ADM8695 4.5 4.65 4.73 V

ADM8692, ADM8693 4.25 4.4 4.48 V
Reset Threshold Hysteresis 40 mV
Reset Timeout Delay

ADM8690, ADM8691, ADM8692, ADM8693 35 50 70 ms OSC SEL = high

ADM8694, ADM8695 140 200 280 ms OSC SEL = high
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long period
70 100 140 ms Short period
Watchdog Timeout Period, External Clock 3840 4064 4097 cycles Long period
768 1011 1025 cycles Short period
Minimum WDI Input Pulse Width 50 ns VIL = 0.4, VIH = 3.5 V
RESET Output Voltage @ VCC = 1 V
RESET, LOW LINE Output Voltage

3.5 V I
RESET, WDO Output Voltage

3.5 V I
Output Short-Circuit Source Current 1 10 25 µA
Output Short-Circuit Sink Current 25 mA
WDI Input Threshold

1

Logic Low 0.8 V

Logic High 3.5 V
WDI Input Current 1 10 µA WDI = V

−10 −1 µA WDI = 0 V

= 2.8 V, TA = T

BATT

) 140 200 µA I

OUT

MIN

to T

, unless otherwise noted.

MAX

− 0.2 VCC − 0.125 V I

CC

− 0.005 V

BATT

− 0.002 V I

BATT

4 20 mV I

0.05 0.4 V I

0.4 V I

= 1 mA

OUT

≤ 100 mA

OUT

= 250 µA, VCC < V

OUT

= 100 µA

OUT

= 2.8 V

BATT

+ 0.2 V

BATT

= 3.2 mA

SINK

= 4.5 V sink current

OUT

= 10 µA, VCC = 1 V

SINK

= 1.6 mA, VCC = 4.25 V

SINK

= 1 µA

SOURCE

= 1.6 mA

SINK

= 1 µA

SOURCE

OUT

BATT

− 0.2 V

Rev. A | Page 4 of 20

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Parameter Min Typ Max Unit Test Conditions/Comments

POWER-FAIL DETECTOR

PFI Input Threshold 1.25 1.3 1.35 V VCC = 5 V
PFI Input Current −25 ±0.01 +25 nA
PFO Output Voltage

0.4 V I

3.5 V I
PFO Short-Circuit Source Current
PFO Short-Circuit Sink Current

1 3 25 A
25 mA

CHIP ENABLE GATING

CEIN Threshold

0.8 V V

3.0 V VIH
CEIN Pull-Up Current
CE

Output Voltage

OUT

V
V
CE Propagation Delay

3 µA

0.4 V I

− 1.5 V I

OUT

− 0.05 V I

OUT

3 7 ns

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 500 kHz OSC SEL = 0 V
OSC IN Frequency with External Capacitor 4 kHz OSC SEL = 0 V, C

1

WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.

= 3.2 mA

SINK

= 1 µA

SOURCE

PFI = low, PFO = 0 V
PFI = high, PFO = V

IL

= 3.2 mA

SINK

= 3.0 mA

SOURCE

= 1 µA, VCC = 0 V

SOURCE

OSC

OUT

= 47 pF

Rev. A | Page 5 of 20

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VCC −0.3 V to +6 V
V

−0.3 V to +6 V

BATT

All Other Inputs −0.3 V to V
Input Current

VCC 200 mA
V

50 mA

BATT

GND 20 mA

Digital Output Current 20 mA
Power Dissipation, N-8 PDIP 400 mW

θJA Thermal Impedance 120°C/W

Power Dissipation, R-8 SOIC 400 mW

θJA Thermal Impedance 120°C/W

Power Dissipation, N-16 PDIP 600 mW

θJA Thermal Impedance 135°C/W

Power Dissipation, RU-16 TSSOP 600 mW

θJA Thermal Impedance 158°C/W

Power Dissipation, R-16 SOIC_N 600 mW

θJA Thermal Impedance 110°C/W

Power Dissipation, RW-16 SOIC_W 600 mW

θJA Thermal Impedance 73°C/W

Operating Temperature Range

Industrial (A Version) −40°C to +85°C

Lead Temperature (Soldering, 10 sec) 300°C
Storage Temperature Range −65°C to +150°C

OUT

+ 0.5 V

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 20

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

BATT

V

2

OUT

ADM8691/

V

3

V

V

GND

OUT

CC

PFI

1

ADM8690/
ADM8692/

2

ADM8694

3

TOP VIEW

(Not to Scale)

4

8

7

6

5

V

BATT

RESET

WDI

PFO

00093-003

Figure 3. ADM8690, ADM8692, and ADM8694

Configuration

Pin

Figure 4. ADM8691, ADM8693, and ADM8695

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

CC

4

5

6

7

8

Pin

ADM8693/
ADM8695

TOP VIEW

(Not to Scale)

Configuration

Table 4. Pin Function Descriptions

Mnemonic Function

VCC Power Supply Input. 5 V nominal.
V

Backup Battery Input.

BATT

V

OUT

Output Voltage. V
100 mA to power CMOS RAM. Connect V

CC

or V

is internally switched to V

BATT

to VCC if V

OUT

, depending on which is at the highest potential. V

OUT

OUT

and V

are not used.

BATT

GND Ground. This is the 0 V ground reference for all signals.
RESET Logic Output. RESET goes low if VCC falls below the reset threshold, or the watchdog timer is not serviced within its timeout

period. The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/ADM8695)
after VCC returns above the threshold. RESET also goes low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms
(ADM8694/ADM8695) if the watchdog timer is enabled but not serviced within its timeout period. The RESET
be adjusted on the ADM8691/ADM8693/ADM8695, as shown in Table 5. The RESET output has an internal 3 µA pull-up, and
can either connect to an open collector reset bus or directly drive a CMOS gate without an external pull-up resistor.

WDI

Watchdog Input. WDI is a three-level input. If WDI remains either high or low f
RESET

pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer can be

or longer than the watchdog timeout period,

disabled if WDI is left floating or is driven to midsupply.

PFI

Power-Fail Input. PFI is the noninverting input to the po
Connect PFI to GND or V

when not used.

OUT

wer-fail comparator. When PFI is less than 1.3 V, PFO

PFO Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less than 1.3 V. The comparator is

turned off and PFO goes low when VCC is below V

BATT

.
CEIN Logic Input. The input to the CE gating circuit. When not in use, connect this pin to GND or V
CE

Logic Output. CE

OUT

the reset threshold, CE

BATT ON

Logic Output. BATT ON goes high when V
switched to V
output current above the 100 mA rating of V

LOW LINE

Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset

is a gated version of the CEIN signal. CE

OUT

is forced high. See Figure 21 and Figure 22.

OUT

is internally switched to the V

. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the

CC

OUT

OUT

.

tracks CEIN when VCC is above the reset threshold. If VCC is below

OUT

input. It goes low when V

BATT

threshold.

RESET
OSC SEL

Logic Output. RESET is an active high output. I

t is the inverse of RESET

Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset

tive time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has

ac

.

a 3 µA internal pull-up (see Table 5).

OSC IN

Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be

onnected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see

c
Table 5 and Figure 17, Figure 18, Figure 19, and Figure 20). With OSC SEL high or floating, the in
the reset active time is fixed at 50 ms typical (ADM8691/ADM8693) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout period immediately
after a reset is 1.6 s typical.

WDO

Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout
period. WDO
and WDO

is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled

remains high. WDO also goes high when LOW LINE goes low.

16

RESET

RESET

15

WDO

14

CE

13

IN

12

CE

OUT

11

WDI

PFO

10

9

PFI

00093-004

can supply up to

OUT

pulse width can

goes low.

.

OUT

is internally

OUT

ternal oscillator is enabled and

Rev. A | Page 7 of 20

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TYPICAL PERFORMANCE CHARACTERISTICS

5.00

1.315

(V)

V

(V)

OUT

V

4.99

4.98

4.97

OUT

4.96

4.95

4.94

2.800

2.798

2.796

2.794

2.792

2.790

2.788

10 20

30 40

Figure 5. V

50 60 70 80 90 100

I

(mA)

OUT

vs. I

OUT

Normal Operation

OUT

1.310

1.305

1.300

1.295

1.290

PFI INPUT THRESHOLD (V)

1.285

1.280

00093-015

–60 –30 0 30 60 90 120

TEMPERATURE (° C)

00093-018

Figure 8. PFI Input Threshold vs. Temperature

53

VCC = 5V

52

51

ADM869 0/

RESET ACTIVE TIME (ms)

50

ADM869 1/
ADM869 2/
ADM8693

2.786

150 250 350 450 550 650 750 850 950 1050

Figure 6. V

A4 3.36V

100

90

10

0%

1V 1V 500ms

OUT

vs. I

I

OUT

(µA)

OUT

Battery Backup

Figure 7. Reset Output Voltage vs. Supply Voltage

49

00093-016

20 40 60 80 100 120

TEMPERATURE (° C)

00093-019

Figure 9. Reset Active Time vs. Temperature

4.69

VCC = 5V

4.67

4.65

4.63

4.61

4.59

RESET VOLTAGE THRESHOLD (V)

4.57

0093-017

4.55

–60 –30 0 30 60 90 120

TEMPERATURE (°C)

00093-020

Figure 10. Reset Voltage Threshold vs. Temperature

Rev. A | Page 8 of 20

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6

VCC = 5V

5

= 25°C

T

A

4

1.35

1.25

3

2

1

PFI

0

PFO

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TIME (µs)

V

PFI

1.3V

PFO

5V

10kΩ

30pF

00093-023

Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor

1.35

1.25

6

PFI

5

4

3

2

1

0

PFO

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

V

PFI

1.3V

TIME (µs)

PFO

30pF

VCC = 5V
T

A

Figure 11. Power-Fail Comparator Response Time Falling

6

VCC = 5V

5

T

= 25°C

A

4

3

2

1

PFI

0

V

1.3V

PFI

PFO

30pF

= 25°C

00093-021

1.35

PFO

1.25

0 1020304050607080

TIME (µs)

90

00093-022

Figure 12. Power-Fail Comparator Response Time Rising

Rev. A | Page 9 of 20

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CIRCUIT INFORMATION

BATTERY SWITCHOVER SECTION

The battery switchover circuit compares VCC to the V
and connects V
when V

is 50 mV higher than V

CC

is 70 mV greater than V
hysteresis prevents repeated rapid switching if V

to whichever is higher. Switchover occurs

OUT

as VCC falls, and when VCC

BATT

as VCC rises. This 20 mV of

BATT

CC

slowly or remains nearly equal to the battery voltage.

V

CC

BATT

GATE DRIVE

100
mV

INTERNAL
SHUTDOWN SIGNAL

700
mV

Figure 14. Battery Switchover Schematic

WHEN
V

BATT

> (VCC + 0.7V)

During normal operation, with VCC higher than V
is internally switched to V

through an internal PMOS tran-

OUT

sistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the V

terminal. V

OUT

normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to V
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.

If the continuous output current requirement at V

− V

100 mA, or if a lower V

CC

voltage differential is desired,

OUT

an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.

A 7 Ω MOSFET switch connects the V

input to V

BATT

battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery back up of CMOS RAM or other low power CMOS
circuitry. The supply current in battery back up is typically 0.4 μA.

The ADM8690/ADM8691/ADM8694/ADM8695 operate with

ttery voltages from 2.0 V to 4.25 V, and the ADM8692/

ba
ADM8693 operate with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad­size, double-layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 μA maximum) flows out of the V

terminal. This current

BATT

is useful for maintaining rechargeable batteries in a fully

input,

BATT

falls very

V

OUT

BATT ON
(ADM8690,
ADM8695)

, VCC

BATT

is

OUT

. The

OUT

exceeds

OUT

during

OUT

0093-005

charged condition. This extends the life of the backup battery by
c

ompensating for its self-discharge current. Also note that this
current poses no problem when lithium batteries are used for
backup because the maximum charging current (0.1 μA) is safe
for even the smallest lithium cells.

If the battery switchover section is not used, V
connected to GND and V

POWER-FAIL RESET OUTPUT

RESET

is an active low output that provides a
the microprocessor whenever V
V

falls below the reset threshold, the

CC

low. The nominal reset voltage threshold is 4.65 V (ADM8690/
ADM8691/ADM8694/ADM8695) or 4.4 V (ADM8692/
ADM8693).

V

CC

t

RESET

LOW LINE

On power-up,
ADM8694 and ADM8695) after V
reset threshold. This allows time for the power supply and micro­processor to stabilize. On power-down, the
low with V
is held in a stable shutdown condition.

RESET

This
ADM8695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to
Figure 17, Figure 18, Figure 19, and Figure 20.

The guaranteed minimum and maximum thresholds of the

M8690/ADM8691/ADM8694/ADM8695 are 4.5 V and

AD

4.73 V, and the guaranteed thresholds of the ADM8692/ADM8693
are 4.25 V and 4.48 V. The ADM8690/ADM8691/ADM8694/
ADM8695 are, therefore, compatible with 5 V supplies with a
+10%, −5% tolerance and the ADM8692/ADM8693 are com­patible with 5 V ± 10% supplies. The reset threshold comparator
has approximately 50 mV of hysteresis. The response time of
the reset voltage comparator is less than1 μs. If glitches are
present on the V
V

should be decoupled close to the device.

CC

1

t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

Figure 15. Power-Fail Reset Timing

RESET

as low as 1 V. This ensures that the microprocessor

CC

active time is adjustable on the ADM8691/ADM8693/

line that could cause spurious reset pulses,

CC

should be

BATT

should be connected to VCC.

OUT

RESET

signal to

is at an invalid level. When

CC

RESET

output is forced

V1

V2V2

t

1

remains low for 50 ms (200 ms for

rises above the appropriate

CC

RESET

output remains

Tabl e 5 and

V1

00093-006

Rev. A | Page 10 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

www.BDTIC.com/ADI

In addition to
contain an active high RESET output. This is the complement of
RESET
reset signal.

WATCHDOG TIMER RESET

The watchdog timer circuit monitors the activity of the micro­processor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
period, a
timeout period is preset at 1.6 seconds on the ADM8690/
ADM8692/ADM8694. The ADM8691/ADM8693/ADM8695
can be configured for either a fixed short 100 ms, or a long

1.6 second timeout period, or for an adjustable timeout period. If
the short period is selected, some systems are unable to service
the watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by V
threshold.

RESET

, the ADM8691/ADM8693/ADM8695

and is intended for processors requiring an active high

RESET

pulse is generated. The nominal watchdog

falling below the reset

CC

The normal (short) timeout period becomes effective following

RESET

e first transition of WDI after

th

has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.

WDI

WDO

t

2

RESET

t

1

t

= RESET TIME

1

t

= NORMAL ( SHORT) W ATCHDOG T IMEOUT PERIOD

2

t

= WATCHDOG TIME OUT PERI OD IMME DIATELY FOLL OWING A RESET

3

Figure 16. Watchdog Timeout Period and Reset Active Time

t

1

t

3

t

1

00093-007

Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period Reset Active Period
OSC SEL OSC IN Normal Immediately After Reset ADM8691/ADM8693 ADM8695

Low1 External clock input 1024 CLKs 4096 CLKs 512 CLKs 2048 CLKs
Low1 External capacitor 400 ms × C/47 pF 1.6 s × C/47 pF 200 ms × C/47 pF 520 ms × C/47 pF
Floating or high Low 100 ms 1.6 s 50 ms 200 ms
Floating or high Floating or high 1.6 s 1.6 s 50 ms 200 ms

1

With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal

internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F

(Hz) = 184,000/C (pF).

OSC

Rev. A | Page 11 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

C

C

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On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 seconds
but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted, as shown
in

Tabl e 5 . Figure 17, Figure 18, Figure 19, and Figure 20 show

e various oscillator configurations that can be used to adjust

th
the reset pulse width and watchdog timeout period.

The internal oscillator is enabled when OSC SEL is high or

loating. In this mode, OSC IN selects between the 1.6 second

f
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.

WATCHDOG OUTPUT (WDO)

The Watchdog Output
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input.
below the reset threshold.

0 TO 500kHz

WDO

(ADM8691/ADM8693/ADM8695)

WDO

is also set high when VCC goes

8

OSC SEL

CLOCK

7

OSC IN

Figure 17. External Clock Source

ADM8691/
ADM8693/

ADM8695

00093-008

CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)

The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when V
invalid level. There are two additional pins (
that can be used to control the chip enable or write inputs of
CMOS RAM. When V

CE

, with a 3 ns propagation delay. When VCC falls below the

of

IN

reset voltage threshold or V
high, independent of

CE

typically drives the CE, CS, or write input of battery

OUT

backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when V
invalid level. Similar protection of EEPROMs can be achieved
using the

V

CC

RESET

NC

Figure 20. Internal Oscillator (100 ms Watchdog)

CE

to drive the store or write inputs.

OUT

ADM8691
ADM8693
ADM8695

E

IN

Figure 21. Chip Enable Gating

t

1

8

OSC SEL

7

OSC IN

is present,

CC

BATT

CE

.

IN

VCC LOW = 0
V

OK = 1

CC

V1

ADM8691/
ADM8693/

ADM8695

00093-011

is at an

CC

CE

and

IN

CE

is a buffered replica

OUT

, an internal gate forces

is at an

CC

CE

OUT

00093-012

V2V2

t

1

CE

CE

OUT

OUT

)

V1

8

OSC SEL

ADM8691/
ADM8693/

ADM8695

7

OSC

OSC IN

00093-009

Figure 18. External Capacitor

8

NC

OSC SEL

ADM8691/
ADM8693/

ADM8695

7

NC

OSC IN

00093-010

Figure 19. Internal Oscillator (1.6 Second Watchdog)

Rev. A | Page 12 of 20

LOW LINE

CE

CE

OUT

IN

t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

0093-013

Figure 22. Chip Enable Timing

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

R

www.BDTIC.com/ADI

POWER-FAIL WARNING COMPARATOR

An additional comparator is provided for early warning of
failure in the microprocessor power supply. The power-fail
input (PFI) is compared to an internal 1.3 V reference. The
power-fail output (
than 1.3 V. Typically, PFI is driven by an external voltage divider
that senses either the unregulated dc input to the system 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the 5 V power supply falls below the
reset threshold.
microprocessor so that data can be stored in RAM and the shut­down procedure executed before power is lost.

INPUT

POWE

PFO

) goes low when the voltage at PFI is less

PFO

is normally used to interrupt the

ADM869x

R1

POWER

R2

FAIL

INPUT

Figure 23. Power-Fail Comparator

1.3V

PFO

POWER
FAIL
OUTPUT

00093-014

Table 6. Input and Output Status in Battery Backup Mode

Signal Status

V

OUT

is connected to V

V

OUT

via an internal PMOS

BATT

switch.
RESET
RESET

LOW LINE

Logic low.

Logic high. The open-circuit output voltage is equal

.

to V

OUT

Logic low.
BATT ON Logic high. The open-circuit voltage is equal to V

WDI

WDI is ignored. It is internally disconnected from the

ternal pull-up resistor and does not source or sink

in

current as long as its input voltage is between GND

and V

. The input voltage does not affect supply

OUT

current.
WDO
PFI

PFO

CEIN is ignored. It is internally disconnected from its

CE

IN

Logic high. The open circuit voltage is equal to V

The power-fail comparator is turned off and has no

ect on the power-fail output.

eff

Logic low.

internal pull-up and does not source or sink current

as long as its input voltage is between GND and

V

. The input voltage does not affect supply

OUT

current.
CE

OUT

Logic high. The open circuit voltage is equal to V
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.

OUT

OUT

OUT

.

.

.

Rev. A | Page 13 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

V

V

V

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APPLICATION INFORMATION

INCREASING THE DRIVE CURRENT

If the continuous output current requirements at V

– V

100 mA, or if a lower V

CC

voltage differential is desired,

OUT

an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.

5V INPUT

POWER

0.1µF 0.1µF

BATTERY

Figure 24. Increasing the Drive Current

PNP TRANSISTOR

V

BATT

CC

BATT

ON

ADM8691/

V

ADM8693/

ADM8695

V

OUT

OUT

exceed

USING A RECHARGEABLE BATTERY FOR BACKUP

If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to V

because this

OUT

eliminates the discharge path that would exist during power-

OUT

.

CC

–

BATT

R

R

V

OUT

0.1µF

down if the resistor is connected to V

V

I =

V

BATT

CC

ADM869x

5V INPUT

POWER

RECHARGEABLE

0.1µF

BATTERY

Figure 25. Rechargeable Battery

ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR

For increased noise immunity, hysteresis can be added to the
power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the
Figure 26. When
summing junction at the PFI pin. When
combination of R3 and R4 sources current into the PFI
summing junction. This results in differing trip levels for the
comparator.

PFO

output and the PFI input as shown in

PFO

is low, Resistor R3 sinks current from the

PFO

is high, the series

00093-024

00093-025

7V TO 15

POWER

5V

PFO

0V

INPUT

0V V

7805

R

1

R

2

V

L

V

IN

Figure 26. Adding Hysteresis to the Power-Fail Comparator

MONITORING THE STATUS OF THE BATTERY

The power-fail comparator can be used to monitor the status of
the backup battery instead of the power supply, if desired. This
is shown in Figure 27. The PFI input samples the battery voltage
a

nd generates an active low
drops below a chosen threshold. It can be necessary to apply a
test load to determine the loaded battery voltage. This is done
under processor control using
high during the battery backup mode, the test load is not
applied to the battery while it is in use, even if the
microprocessor is not powered.

20kΩ

R

10MΩ

1

R

10MΩ

2

Figure 27. Monitoring the Battery Status

BATTERY

OPTIONAL

TEST LOAD

5V

PFI

ADM869x

H

V

BATT

PFI

CE

V

CC

1.3V

R

3

1+

VH = 1.3V

= 1.3V

1+

V

L

ASSUMING R

HYSTERESIS V

PFO

signal when the battery voltage

CE

. Because

OUT

5V INPUT

POWER

V

CC

ADM869x

OUT

PFO

R

R

1

1

+

)(

R

R

2

3

R

R1 (5V – 1.3V)

1

–

R

(1.3V (R3 + R4))

R

2

3

< < R3 THEN

4

– VL = 5V

H

PFO

CE

IN

R

4

CE

LOW BATTERY
SIGNAL TO
MICROPRO CESSOR
I/O PIN

FROM
MICROPRO CESSOR
I/O PIN APPLIES
TEST LOAD
TO BATTERY

TO
MICROPRO CESSOR
NMI

)(

R

1

)(

R

2

is forced

OUT

00093-026

00093-027

Rev. A | Page 14 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

W

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ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS

The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.

ATCHDOG

STROBE

CONTROL

INPUT

Figure 28. Programming the Watchdog Input

This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer preventing
the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
extend the watchdog period rather than disable the watchdog.

WDI

ADM869x

00093-028

This can be done under program control using the circuit

n Figure 29. When the control input is high, the

shown i

EL pin is low and the watchdog timeout is set by the

OSC S
external capacitor. A 0.01 μF capacitor sets a watchdog time­out delay of 100 seconds. When the control input is low, the
OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which
diode is used, as shown in
in

ternal timeout is set at 100 ms; with D2 inserted, the timeout

Figure 29. With D1 inserted, the

is set at 1.6 seconds.

CONTROL

1

INPUT

D1

Figure 29. Programming the Watchdog Input

OSC SEL

D2

1

LOW = INTERNAL TIMEOUT

HIGH = EXTE RNAL TIMEOUT

ADM869x

OSC IN

0093-029

Rev. A | Page 15 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

R

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TYPICAL APPLICATIONS

ADM8690, ADM8692, AND ADM8694

Figure 30 shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. V
powers the CMOS RAM. Under normal operating conditions
with V
failure occurs, V
maintaining power for the CMOS RAM. A
generated when V
ADM8694 or 4.4 V for the ADM8692.
50 ms (200 ms for the ADM8694) after V

present, V

CC

is internally connected to VCC. If a power

OUT

decays and V

CC

is switched to V

OUT

RESET

falls below 4.65 V for the ADM8690/

CC

RESET

remains low for

returns to 5 V.

CC

pulse is also

The watchdog timer input (WDI) monitors an input/output line
f

rom the microprocessor system. This line must be toggled once
every 1.6 seconds to verify correct software execution. Failure to
toggle the line indicates that the microprocessor system is not
correctly executing its program and can be tied up in an endless
loop. If this happens, a reset pulse is generated to initialize the
microprocessor.

If the watchdog timer is not needed, the WDI input should be

t floating.

lef

The power-fail input, PFI, monitors the input power supply via
a r

esistive divider network. The voltage on the PFI input is
compared with a precision 1.3 V internal reference. If the input
voltage drops below 1.3 V, a power-fail output (

PFO

generated. This warns of an impending power failure and can
be used to interrupt the processor so that the system can be shut
down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power-fail threshold
voltage (V

5V

BATTERY

Figure 30. ADM8690/ADM8692/ADM8694 Typical Application Circuit A

).

T

= (1.3 R1/R2) + 1.3 V

V

T

R1/R2 = (V

R

1

R

2

/1.3) − 1

T

V

CC

PFI

ADM8690/
ADM8692/

V

ADM8694

RESET

V

BATT

+

GND

OUT

PFO

WDI

0.1µF

POWER

CMOS RAM
POWER

MICROPROCESSOR

SYSTEM

RESET

NMI

I/O LINE

Figure 31 shows a similar application, but in this case the PFI
input monitors the unregulated input to the 7805 voltage
regulator. This gives an earlier warning of an impending power
failure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to
be completed before the power is lost.

OUT

, thereby

BATT

) signal is

Rev. A | Page 16 of 20

00093-030

INPUT

POWER

V > 8V

R

1

R

2

BATTERY

7805

+

PFI

ADM8690/
ADM8692/

ADM8694

V

BATT

Figure 31. ADM8690/ADM8692/ADM8694 Typical Application Circuit B

ADM8691, ADM8693, AND ADM8695

A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 32. CMOS RAM is powered from V
When 5 V power is present, this is routed to V
V

is routed to V

BATT

, but if more current is required, an external PNP transistor

V

CC

OUT

can be added. When V
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 μF capacitor is connected to V
supply the transient currents for CMOS RAM. When V
lower than V
backup battery to V

INPUT POWE
5V

3V

BATTERY

R

1

R

2

NC

Figure 32. ADM8691/ADM8693/ADM8695 Typical Application

, an internal 20 Ω MOSFET connects the

BATT

OUT

0.1µF

V

CC

V

BATT

ADM8691/
ADM8693/

ADM8695

PFI
GND

OSC IN

OSC SEL

LOW LINE

SYSTEM STATUS

INDICATO RS

RESET OUTPUT

The internal voltage detector monitors VCC and generates a
RESET

output to hold the microprocessor reset line low when

V

is below 4.65 V (4.4 V for ADM8693). An internal timer

CC

RESET

holds
V

rises above 4.65 V (4.4 V for the ADM8693). This prevents

CC

repeated toggling of
and recovers with each power line cycle.

The crystal oscillator normally used to generate the clock for
micr

oprocessors can take several milliseconds to stabilize.
Because most microprocessors need several clock cycles to
reset,

oscillator has started. The power-up

low for 50 ms (200 ms for the ADM8695) after

RESET

must be held low until the microprocessor clock

5V

V

CC

V

RESET

GND

. V

is higher than V

CC

0.1µF

0.1µF

CMOS RAM
POWER

MICROPROCESSOR

RESET

NMI

I/O LINE

BATT

OUT

PFO

WDI

can supply up to 100 mA from

OUT

.

0.1µF

BATT

V

OUT

ON

CE

OUT

CE

IN

WDI

PFO

RESET

WDO

RESET

, even if the 5 V power drops out

RESET

RESET

CMOS

RAM

ADDRESS

DECODE

0.1µF

pulse lasts 50 ms

POWER

SYSTEM

.

OUT

. If VCC fails,

OUT

, the BATT ON

to

OUT

is

CC

A0 TO 15

I/O LINE

NMI

RESET

MICROPROCESSOR

SYSTEM

00093-031

00093-032

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

www.BDTIC.com/ADI

(200 ms for the ADM8695) to allow for this oscillator start-up
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used. Refer to

Table 5 and Figure 17, Figure 18, Figure 19, and
Figure 20. The manual reset switch and the 0.1 μF capacitor
co

nnected to the reset line can be omitted if a manual reset is
not needed. An inverted, active high, RESET output is also
available.

POWER-FAIL DETECTOR

The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the
voltage at PFI falls below 1.3 V, the power-fail output (

PFO

)
drives the processor’s NMI input low. If, for example, a power­fail threshold of 4.8 V is set with Resistor R
microprocessor has the time when V

and Resistor R2, the

1

falls from 4.8 V to 4.65 V

CC

to save data into RAM. An earlier power-fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This allows more time for microprocessor
housekeeping tasks to be completed before power is lost.

RAM WRITE PROTECTION

The ADM8691/ADM8693/ADM8695
chip select inputs of the CMOS RAM.
long as V

is above the 4.65 V (4.4 V for the ADM8693) reset

CC

threshold.

CE

line drives the

OUT

CE

follows

OUT

CE

as

IN

microprocessor from writing erroneous data into RAM during

ower-up, power-down, brownouts, and momentary power

p
interruptions.

WATCHDOG TIMER

The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every

1.6 seconds to verify proper software execution. If a hardware
or software failure occurs such that WDI is not toggled, the
ADM8691/ADM8693 issues a 50 ms (200 ms for the ADM8695)
RESET

pulse after 1.6 seconds. This typically restarts the micro-

processor power-up routine. A new

1.6 seconds until WDI is again strobed. If a different watchdog
timeout period is required, a capacitor should be connected to
OSC IN or an external clock can be used. Refer to
Figure 17, Figure 18, Figure 19, and Figure 20.

The watchdog output (

WDO

not serviced within its timeout period. Once
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.

RESET

The

output has an internal 3 μA pull-up and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.

RESET

pulse is issued every

Tabl e 5 and

) goes low if the watchdog timer is

WDO

goes low, it

If V

falls below the reset threshold,

CC

independent of the logic level at

CE

goes high,

OUT

CE

. This prevents the

IN

Rev. A | Page 17 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

5

0.280 (7.11)

4

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

1

PIN 1

0.100 (2.54)

0.210
(5.33)

MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA

Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

ensions shown in inches and (millimeters)

Dim

0.800 (20.32)

0.790 (20.07)

0.780 (19.81)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

16

1

PIN 1

0.100 (2.54)

0.210

(5.33)

MAX

BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTROLLI NG DIMENSIONS ARE IN INCHES; MIL LIMETER DIME NSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUI VAL ENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE O R HALF LEADS.

9

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

8

0.060 (1.52)
MAX

0.015
(0.38)

0.015 (0.3 8)

MIN

GAUGE

PLANE

SEATING
PLANE

0.005 (0.13)
MIN

COMPLIANT TO JEDEC STANDARDS MS-001-AB

Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]

(N-16)

Dim

ensions shown in inches and (millimeters)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.325 (8.2 6)

0.310 (7.8 7)

0.300 (7.6 2)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

051206-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]

5.00 (0.1968)

4.80 (0.1890)

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Dimensions shown in millimeters and (inches)

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Dimensions shown in millimeters and (inches)

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

row Body

Nar

(R-8)

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

Wide Body

(RW-16)

0.25 (0.0098)

0.17 (0.0067)

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

× 45°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Rev. A | Page 18 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

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10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.10

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

Figure 37. 16-Lead Standard Small Outline Package [SOIC_N]

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

× 45°

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Narrow Body

(R-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM8690AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8690ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8690ARN −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8690ARN-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8690ARNZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8691AN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8691ANZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8691ARN −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARN-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARNZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARWZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8691ARU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8691ARUZ1 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8692AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8692ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8692ARN −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8692ARN-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8692ARNZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8693AN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8693ANZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8693ARN −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARN-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARNZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARWZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8693ARU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8693ARUZ1 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

5.10

5.00

4.90

16

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40
BSC

SEATING
PLANE

0.20

0.09

(RU-16)

Dimensions shown in millimeters

8°
0°

0.75

0.60

0.45

Rev. A | Page 19 of 20

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695

www.BDTIC.com/ADI

Model Temperature Range Package Description Package Option

ADM8694AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8694ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8694ARN −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8694ARN-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8694ARNZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8695ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8695ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8695ARWZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16

1

Z = Pb-free part.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00093-0-9/06(A)

Rev. A | Page 20 of 20