Microprocessor
V
BATT
V
CC
CMOS
RAM
CE
IN
OSC IN
OSC SEL
BAT
ON
LOW LINE
V
OUT
CE
OUT
RESET RESET
PFO
WDI
V
CC
WDO
I/O LINE
NMI
A0–A15
µP
POWER
µP
ADDRESS
DECODE
ADM691A
ADM693A
ADM800L
ADM800M
GND
PFI
BATTERY
0.1µF
+5V
NC
R2
R1
INPUT
POWER
7805
SYSTEM
STATUS
INDICATORS
a
ADM691A/ADM693A/ADM800L/M
FEATURES
Low Power Consumption:
Precision Voltage Monitor
62% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 mA Standby Current
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring
GENERAL DESCRIPTION
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include µP reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
V
as low as 1 V.
CC
2. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.
V
V
BATT
CE
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
Supervisory Circuits
FUNCTIONAL BLOCK DIAGRAM
BATT ON
1
4.65V
CC
CHIP ENABLE
OUTPUT
CONTROL
IN
RESET &
WATCHDOG
TIMEBASE
WATCHDOG
TRANSITION DETECTOR
1.25V
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
RESET &
GENERATOR
WATCHDOG
TIMER
ADM691A/ADM693A
ADM800L/ADM800M
LOW LINE
V
OUT
CE
OUT
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO
)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Figure 1. Typical Application
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS
(VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) V
Parameter Min Typ Max Unit Test Conditions/Comments
BATTERY BACKUP SWITCHING
, V
V
CC
V
OUT
V
CC
V
OUT
V
BATT
Supply Current (Excludes I
Supply Current in B. Backup (Excludes I
Battery Standby Current 5.5 V > V
(+ = Discharge, – = Charge) –0.1 +0.02 µA(V
Battery Switchover Threshold V
V
CC–VBATT
Battery Switchover Hysteresis 60 mV
BATT ON Output Voltage Low 0.1 0.4 V I
BATT ON Output Short Circuit Current 60 mA Sink Current
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM691A, ADM800L 4.5 4.65 4.75 V
ADM693A, ADM800M 4.25 4.40 4.50 V
ADM800L, V
ADM800M, V
Reset Threshold Hysteresis 15 mV
V
CC
LOW LINE to RESET Delay 800 ns
Reset Timeout Period Internal Oscillator 140 200 280 ms Power Up
Reset Timeout Period External Clock 2048 Cycles Power Up
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period
Watchdog Timeout Period, External Clock 4096 Cycles Long Period
Minimum WDI Input Pulse Width 100 ns V
RESET Output Voltage 0.004 0.3 V I
RESET Output Short Circuit Current 7 20 mA
RESET Output Voltage Low 0.1 0.4 V I
LOW LINE Output Voltage 0.4 V I
LOW LINE Short Circuit Source Current 1 15 100 µA
WDO Output Voltage 0.4 V I
WDO Short Circuit Source Current 3 10 mA
WDI Input Threshold
Logic Low 0.8 V
Logic High 0.75 × V
WDI Input Current –50 –10 µA WDI = 0 V
POWER FAIL DETECTOR
PFI Input Threshold ADM69xA 1.2 1.25 1.3 V V
PFI Input Threshold ADM800L/M 1.225 1.25 1.275 V V
PFI Input Current ±0.01 ±25 nA
PFO Output Voltage 0.4 V I
PFO Short Circuit Source Current 1 15 100 µA
PFI to PFO Delay 25 µsV
Operating Voltage Range 0 5.5 V
BATT
Output Voltage VCC – 0.05 VCC – 0.02 V I
– 0.3 VCC – 0.2 V I
V
to V
Output Resistance 0.8 1.2 Ω VCC = 4.5 V
OUT
in Battery Backup Mode V
to V
Output Resistance 12 Ω V
OUT
) 70 100 µAVCC > (V
OUT
) 0.04 1 µAVCC < (V
OUT
CC
– 0.3 V V
BATT
– 0.25 V V
V
BATT
– 0.15 V V
V
BATT
–1.0 +0.02 µA(V
BATT
V
BATT
0.7 1.5 V I
1 15 100 µA Source Current
Falling 4.55 4.70 V TA = +25°C
CC
Falling 4.3 4.45 V TA = +25°C
CC
to RESET Delay 80 µs Power Down
70 100 140 ms Short Period
1024 Cycles Short Period
0.1 0.4 V I
3.5 V I
3.5 V I
3.5 V I
CC
20 50 µA WDI = V
3.5 I
60 µsV
= +2.8 V, TA = T
BATT
20 Ω V
25 Ω V
MIN
to T
unless otherwise noted)
MAX
= 25 mA
OUT
= 250 mA
OUT
= 4.5 V, I
BATT
= 2.8 V, I
BATT
= 2.0 V, I
BATT
= 4.5 V
BATT
= 2.8 V
BATT
= 2.0 V
BATT
BATT
BATT
CC
+0.2 V) < V
BATT
+0.2 V) < V
BATT
+ 0.03 V Power Up
– 0.03 V Power Down
= 3.2 mA
SINK
= 25 mA
SINK
= 0.4, VIH = 0.75 × V
IL
= 50 µ A, VCC = 1 V, V
SINK
= 3.2 mA, VCC = 4.25 V
SINK
= 1.6 mA, VCC = 5 V
SOURCE
= 3.2 mA
SINK
= 3.2 mA, VCC = 4.25 V
SINK
= 1 µA, VCC = 5 V
SOURCE
= 3.2 mA, VCC = 4.25 V
SINK
= 500 µA, VCC = 5 V
SOURCE
V
OUT
= 5 V
CC
= 5 V
CC
= 3.2 mA
SINK
= 1 µA
SOURCE
= –20 mV
IN
= 20 mV
IN
= 20 mA
OUT
= 10 mA
OUT
= 5 mA
OUT
– 1 V)
– 1.2 V), V
> V
BATT
+ 0.2 V
CC
CC
= 2.8 V
BATT
, TA = +25°C
CC
BATT
= 0 V
–2–
REV. 0
ADM691A/ADM693A/ADM800L/M
Parameter Min Typ Max Units Test Conditions/Comments
CHIP ENABLE GATING
CE
Leakage Current ±0.005 ±1 µA Disable Mode
IN
CEIN to CE
CEIN to CE
CE
OUT
CE
OUT
RESET to CE
OSCILLATOR
OSC IN Input Current 0.1 ±5 µA OSC SEL = 0 V
OSC In Input Pullup Current 10 100 µA OSC SEL = V
OSC SEL Input Pullup Current 10 100 µA OSC SEL = 0 V
OSC IN Frequency Range 500 kHz OSC SEL = 0 V
OSC IN Threshold Voltage V
OSC IN Frequency with Ext Capacitor 100 kHz OSC SEL = 0 V, C
NOTES
1
Either VCC or V
Specifications subject to change without notice.
Resistance 40 150 Ω Enable Mode
OUT
Propagation Delay 6 10 ns RIN = 50 Ω, C
OUT
LOAD
Short-Circuit Current 0.1 0.75 2.0 mA Disable Mode, CE
Output Voltage 3.5 V VCC = 5 V, I
Propagation Delay 12 µs Power Down
OUT
– 0.4 V
OUT
– 0.6 V V
OUT
3.65 2.00 V V
can be 0 V if the other > +2.0 V.
BATT
2.7 V V
= 0 V, V
CC
IH
IL
= –100 µA
OUT
BATT
OUT
= 50 pF
= 0 V
OUT
= 2.8 V, I
or Floating
= 47 pF
OSC
OUT
= 1 µ A
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
BATT
OUT
+ 0.5 V
Input Current
V
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA
CC
V
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
CC
V
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
BATT
V
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
BATT
GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
ϑA
Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .110°W
JA
Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
JA
Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Option
ADM691AAN –40°C to +85°C N-16
ADM691AARN –40°C to +85°C R-16N
ADM691AARW –40°C to +85°C R-16W
ADM691AARU –40°C to +85°C RU-16
ADM693AAN –40°C to +85°C N-16
ADM693AARN –40°C to +85°C R-16N
ADM693AARW –40°C to +85°C R-16W
ADM800LAN –40°C to +85°C N-16
ADM800LARN –40°C to +85°C R-16N
ADM800LARW –40°C to +85°C R-16W
ADM800MAN –40°C to +85°C N-16
ADM800MARN –40°C to +85°C R-16N
ADM800MARW –40°C to +85°C R-16W
Table I. Product Selection Table
Power On Low V
CC
Watchdog Battery Backup Base Drive Chip Enable
Part No. Reset Time Threshold Timeout Switching Ext PNP Signals
ADM691A 200 ms or Adj. 4.65 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM693A 200 ms or Adj. 4.4 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM800M 200 ms or Adj. 4.4 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM800L 200 ms or Adj. 4.65 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes
REV. 0
–3–
ADM691A/ADM693A/ADM800L/M
Pin Mnemonic Function
PIN DESCRIPTIONS
1V
BATT
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
2V
3V
OUT
CC
Output Voltage, VCC or V
tial. When V
When V
V
if a backup battery is not being used.
CC
is higher than V
CC
is lower than V
CC
is internally switched to V
BATT
BATT
and below the reset threshold, V
BATT
Power Supply Input; +5 V.
depending on which is at the highest poten-
OUT
and is also higher than the reset threshold, VCC is switched to V
is switched to V
BATT
. Connect V
OUT
OUT
OUT
.
to
4 GND 0 V. Ground reference for all signals.
5 BATT ON Logic Output. BATT ON goes high when V
V
is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an ex-
OUT
ternal PNP transistor to increase the output current above the 250 mA rating of V
6
7 OSC
LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as
V
rises above the reset threshold.
CC
IN Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC
is internally switched to the V
OUT
IN low selects 100 ms while leaving it floating
input. It goes low when
BATT
.
OUT
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
8 OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC
IN, is enabled. OSC SEL has a 10 µA internal pullup.
9 PFI Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
10
1.25 V,
PFO Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than
PFO goes low. Connect PFI to GND or V
OUT
when not used.
1.25 V.
11 WDI Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period,
RESET pulses low and WDO goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
12
13
14 WDO Logic Output. The Watchdog Output,
CE
CE
OUT
IN
Output. CE
reset is asserted, CE
Chip Enable Input. The input to the CE gating circuit. Connect to GND or V
goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when
OUT
will remain low for 15 µs or until CE
OUT
goes high, whichever occurs first.
IN
if not used.
OUT
WDO, goes low if WDI remains either high or low for longer than
the Watchdog timeout period.
WDO is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
15
RESET Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after
V
goes above the reset threshold.
CC
16 RESET Logic Output. RESET is an open-drain output. It is the inverse of RESET.
PIN CONFIGURATIONS
V
BATT
V
OUT
V
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
CC
1
2
3
ADM691A
ADM693A
4
ADM800L
5
ADM800M
6
TOP VIEW
(Not to Scale)
7
8
16
15
14
13
12
11
10
9
RESET
RESET
WDO
CE
CE
WDI
PFO
PFI
–4–
IN
OUT
REV. 0
Typical Performance Curves–
I
OUT
– mA
70
0
410
V
BATT
TO V
OUT
– mV
68
60
50
40
20
10
30
R
OUT
= 7Ω
ADM691A/ADM693A/ADM800L/M
100
90
80
70
60
50
SUPPLY CURRENT – µA
CC
40
V
30
20
–50 125–25 0 25 50 75 100
TEMPERATURE – °C
Figure 2. ICC vs. Temperature: Normal Operation
60
55
50
45
40
35
BATTERY SUPPLY CURRENT – nA
30
–50 90–30 –10 10 30 50 70
TEMPERATURE – °C
1.2
1.1
1.0
0.9
ON RESISTANCE – R
OUT
0.8
TO V
CC
V
0.7
0.6
–50 90–30 –10 10 30 50 70
Figure 5. VCC to V
80
70
60
50
– mV
OUT
40
TO V
30
CC
V
20
10
0
40 120
TEMPERATURE – °C
ON-Resistance vs. Temperature
OUT
R
= 0.67Ω
OUT
60 80 100
I
OUT
– mA
Figure 3. I
80
70
60
50
RESISTANCE – Ω
40
ON
CE
30
20
Figure 4. Chip Enable ON-Resistance vs. Temperature
vs. Temperature: Battery Backup Mode
BATT
–50 125–25 0 25 50 75 100
TEMPERATURE – °C
Figure 6. VCC to V
Figure 7. V
BATT
to V
Voltage Drop vs. Current
OUT
Voltage Drop vs. Current
OUT
REV. 0
–5–
ADM691A/ADM693A/ADM800L/M
TEMPERATURE – °C
–50 130–20
10
40 70 100
1200
0
RESET OUTPUT RESISTANCE – Ω
600
1000
800
400
200
VCC = 5V, V
BATT
= 2.8V
SOURCING CURRENT
VCC = 0V, V
BATT
= 2.8V
SINKING CURRENT
10
9
8
7
6
– µA
5
BATT
I
4
3
2
1
0
0 5.00.5 1.0 1.5 2.0 2.5 3.0
VCC – V
V
= 2.8V
BATT
3.5 4.0 4.5
Figure 8. Battery Current vs. Input Supply Voltage
100
LONG WATCHDOG TIMEOUT PERIOD
10
RESET ACTIVE
TIMEOUT PERIOD = >
1
SHORT WATCHDOG
TIMEOUT PERIOD
WATCHDOG AND RESET TIMEOUT PERIOD – s
0.1
10 1k100
C
– pF
OSC
16
14
12
10
8
6
4
PROPAGATION DELAY – ns
2
0
0 30050 100 150 200 250
LOAD CAPACITANCE – pF
Figure 11. Chip Enable Propagation Delay vs.
Load Capacitance
230
220
210
200
190
RESET DELAY – ms
180
170
–50 90–30 –10 10 30 50 70
TEMPERATURE – °C
Figure 9. Watchdog and Reset Timeout Period vs.
OSC IN Capacitor
7.0
6.5
6.0
5.5
5.0
PROPAGATION DELAY – ns
4.5
4.0
–50 125–25 0 25 50 75 100
TEMPERATURE – °C
Figure 10. Chip Enable Propagation Delay vs.
Temperature
Figure 12. Reset Timeout Relay vs. Temperature
Figure 13.
RESET
Output Resistance vs. Temperature
–6–
REV. 0
ADM691A/ADM693A/ADM800L/M
100
90
10
0%
400ms1V
Figure 14.
RESET
Output Voltage vs. Supply
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to the
Microprocessor whenever V
is at an invalid level. When V
CC
CC
falls below the reset threshold, the RESET output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up
V
rises above the appropriate reset threshold. This allows time
CC
RESET will remain low for 200 milliseconds after
for the power supply and microprocessor to stabilize. On powerdown, the
RESET output remains low with VCC as low as 1 V.
This ensures that the microprocessor is held in a stable shutdown condition. If
RESET is required to be low for voltages below 1 V, this may be achieved by connecting a pull-down resistor
on the
RESET line. The resistor will help maintain RESET low
down to V
below 2 V. With battery voltages ≥2 V
rectly with V
= 0 V. Note that this is only necessary if V
CC
RESET will function cor-
from 0 V to +5.5 V.
CC
BATT
is
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaranteed thresholds of the ADM693A/ADM800M are 4.25 V and
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V ± 10% supplies.
In addition to
This is the complement of
RESET an active high RESET output is provided.
RESET and is useful for processors
requiring an active high RESET signal.
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watchdog timeout period may be configured for either a fixed “short”
100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V
falling be-
CC
low the reset threshold.
100
90
10
0%
1V
Figure 15.
RESET
10µs
Response Time
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
BATT ON
1
V
V
BATT
CE
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
4.65V
CC
CHIP ENABLE
OUTPUT
CONTROL
IN
RESET &
WATCHDOG
TIMEBASE
WATCHDOG
TRANSITION DETECTOR
1.25V
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
RESET &
GENERATOR
ADM691A/ADM693A
ADM800L/ADM800M
WATCHDOG
TIMER
LOW LINE
V
OUT
CE
OUT
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO
)
Figure 16. Functional Block Diagram
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input.
set high when V
mains high or low indefinitely,
goes below the reset threshold. If WDI re-
CC
RESET and RESET will gener-
WDO is also
ate 200 ms pulses every 1.6 sec.
REV. 0
–7–
ADM691A/ADM693A/ADM800L/M
CE
IN
RESET
RESET
V
CC
CE
OUT
OSC SEL
RESET
THRESHOLD
80µs
t
RS
12µs
t
RS
80µs
OSC SEL
OSC IN
7
8
ADM69_A
ADM800_
NC
NC
Changing the Watchdog and Reset Timeout
The watchdog and reset timeout periods may be controlled using OSC SEL and OSC IN. Please refer to Table II. With both
these inputs floating (or connected to V
) as in Figure 16, the
OUT
reset timeout is fixed at 200 ms and the watchdog timeout is
fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure
16, the reset timeout period remains at 200 ms but a short
When V
disabled and WDI goes high impedance as it is disconnected
from its internal resistor network.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods.
is below the reset threshold, the watchdog function is
CC
(100 ms) watchdog timeout period is selected (except immediately following a reset where it reverts to 1.6 sec). By connecting
OSC SEL to GND it is possible to select alternative timeout periods by either connecting a capacitor from OSC IN to GND or
by overdriving OSC IN with an external clock. With an external
capacitor, the watchdog timeout period is
Twd (ms) = 600 (C/47 pF)
and the reset active period is
Treset (ms) = 1200 (C/47 pF)
With an external clock connected to OSC IN, the timeout
periods become
Twd = 1024 (1/f
Treset = 2048 (1/f
Battery-Switchover Section
During normal operation with VCC higher than the reset threshold and higher than V
, VCC is internally switched to V
BATT
via an internal PMOS transistor switch. This switch has a typical on-resistance of 0.75 Ω and can supply up to 250 mA at the
V
terminal. V
OUT
is normally used to drive a RAM memory
OUT
bank which may require instantaneous currents of greater than
CLK
CLK
)
)
Figure 17. RESET and Chip Enable Timing
8
OUT
CLOCK
0 TO 250kHz
OSC SEL
7
OSC IN
ADM69_A
ADM800_
250 mA. If this is the case then a bypass capacitor should be
connected to V
transients to the RAM. A capacitance value of 0.1 µF or greater
. The capacitor will provide the peak current
OUT
Figure 18a. External Clock Source
may be used.
If the continuous output current requirement at V
250 mA or if a lower V
CC–VOUT
voltage differential is desired,
OUT
exceeds
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can drive
the base of the external transistor.
If V
drops below V
CC
backup is selected. A 7 Ω MOSFET switch connects the V
input to V
. This MOSFET has very low input-to-output
OUT
differential (dropout voltage) at the low current levels required for
battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.04 µA.
High value capacitors, either standard electrolytic or the faradsize double layer capacitors, can also be used for short-term
and below the reset threshold, battery
BATT
BATT
Figure 18b. Internal Oscillator (1.6 s Watchdog)
8
OSC SEL
ADM69_A
7
C
OSC
ADM800_
OSC IN
memory backup.
If the battery-switchover section is not used, V
connected to GND and V
should be connected to VCC.
OUT
Table II. Reset Pulse Width and Watchdog Timeout Selections
BATT
should be
Figure 18c. External Capacitor
Watchdog Timeout Period
OSC SEL OSC IN Normal Immediately After Reset Reset Active Period
Low External Clock Input 1024 clks 4096 clks 2048 clks
Low External Capacitor 600 ms × C/47 pF 2.4 s × C/47 pF 1200 ms × C/47 pF
Floating Low 100 ms 1.6 s 200 ms
Floating Floating or V
OUT
1.6 s 1.6 s 200 ms
–8–
REV. 0
ADM691A/ADM693A/ADM800L/M
8
OSC SEL
ADM69_A
7
C
OSC
ADM800_
OSC IN
Figure 18d. Internal Oscillator (100 ms Watchdog)
WDI
WDO
t
2
RESET
t
1
t
= RESET TIME.
1
t
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
2
t
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
3
t
1
t
3
t
1
Figure 19. Watchdog Timing
CE Gating and RAM Write Protection
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when V
CEIN and CE
of CMOS RAM. When V
lica of
low the reset voltage threshold, an internal gate forces
is at an invalid level. There are two additional pins,
CC
, that control the Chip Enable or Write inputs
OUT
is present, CE
CC
is a buffered rep-
OUT
CEIN, with a 5 ns propagation delay. When VCC falls be-
CE
OUT
high, independent of CEIN.
CE
typically drives the CE, CS, or Write input of battery
OUT
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
is at an in-
CC
valid level. Similar protection of EEPROMs can be achieved by
using the
CE
to drive the Store or Write inputs of an
OUT
EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output (
PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regulator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold.
PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down procedure executed before power is lost.
INPUT
POWER
POWER
R1
INPUT
R2
FAIL
1.25V
PFO
POWER
FAIL
OUTPUT
Figure 20. Power Fail Comparator
Table III. Input and Output Status in Battery Backup Mode
Signal Status
V
BATT
V
OUT
Supply Current is <1 µA.
V
is connected to V
OUT
via an internal
BATT
PMOS switch.
V
CC
Switchover comparator monitors VCC for
active switchover.
GND 0 V.
BATT ON Logic High. The open circuit voltage is equal
to V
OUT
.
LOW LINE Logic Low.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
PFI The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥ V
BATT
–1.2 V. With VCC lower than this, PFO is
forced low.
PFO The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥ V
BATT
–1.2 V. With VCC lower than this, PFO is
forced low.
WDI WDI is ignored.
CE
CE
OUT
IN
Logic High. The open circuit voltage is equal
to V
OUT
.
High Impedance.
WDO Logic High. The open circuit voltage is equal
to V
OUT
.
RESET Logic Low.
RESET High Impedance.
REV. 0
–9–
ADM691A/ADM693A/ADM800L/M
APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at V
250 mA or if a lower V
CC–VOUT
voltage differential is desired, an
OUT
exceeds
external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output can drive the
base of the external transistor via a current limiting transistor.
+5V
INPUT
POWER
BATTERY
0.1µF
V
V
BATT
TRANSISTOR
CC
PNP
BATT
ON
0.1µF
V
OUT
Figure 21. Increasing the Drive Current
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
since this
OUT
eliminates the discharge path that would exist during power
down if the resistor were connected to V
+5V
INPUT
POWER
RECHARGEABLE
BATTERY
0.1µF
V
V
CC
BATT
CC.
V
OUT
I =
R
ADM69_A
ADM800_
– V
R
BATT
V
0.1µF
OUT
Figure 22. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting,
hysteresis can be added simply by connecting a resistor between
the
PFO output and the PFI input as shown in Figure 23. When
PFO is low, resistor R3 sinks current from the summing junction
at the PFI pin. When
PFO is high, R3 sources current into the
PFI summing junction. This results in differing trip levels for the
comparator. Resistors R1 and R2 therefore set the trip point
while R3 adds hysteresis. R3 should be larger than 10 kΩ so that
it does not cause excessive loading on the PFO output. Additional noise rejection and filtering may be achieved by adding a
capacitor from PFI to GND.
INPUT
POWER
R1
R2
5V
PFO
0V
0V V
PFI
1.25V
L
(PFO)
R3
V
M
V
IN
TO
µP NMI
VH =
VL = 1
1.25 1
.25+R1
V
MID
R2+R
+ R
R
1.25
R
=
1.25
2
×
VCC–
2
R1+R
3
1
R
3
1.25
R
3
2
R
2
Figure 23. Adding Hysteresis to the Power Fail Comparator
Typical Operating Circuit
A typical operating circuit is shown in Figure 24. The circuit
features power supply monitoring, battery backup switching
and watchdog timing.
CMOS RAM is powered from V
present, this is routed to V
routed to V
OUT
. V
OUT
OUT
can supply up to 250 mA from VCC, but
. When 5 V power is
OUT
. If VCC fails, then V
BATT
is
if more current is required, an external PNP transistor can be
added. When V
is higher than V
CC
and the reset threshold,
BATT
BATT ON goes low, providing base drive for the external transistor. When V
is lower than V
CC
and the reset threshold,
BATT
an internal 7 Ω. MOSFET connects the backup battery to
V
.
OUT
Reset Output
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s RESET line low
when V
is below the reset threshold. An internal timer holds
CC
RESET low for 200 ms after VCC rises above the threshold.
This prevents repeated toggling of
RESET even if the 5 V
power drops out and recovers with each power line cycle.
Early Power Fail Detector
The input power line is monitored via a resistive potential divider connected to the Power Fail Input (PFI). When the voltage at PFI falls below 1.25 V, the Power Fail Output (
PFO)
drives the processor’s NMI input low. If a Power Fail threshold
of 7 V is set with resistors R1 and R2, the microprocessor will
have the time when V
drops below 7 V to save data into
CC
RAM. Power supply capacitance will extend the time available.
This will allow more time for microprocessor housekeeping
tasks to be completed before power is lost.
–10–
REV. 0
ADM691A/ADM693A/ADM800L/M
3V
BATTERY
0.1µF0.1µF
OSC IN
OSC SEL
GND
PFI
NC
0.1µF
RESET
WDO
LOW LINE
SYSTEM STATUS
INDICATORS
RESET
PFO
WDI
CE
IN
CE
OUT
V
BATT
R2
R1
CMOS
RAM
ADDRESS
DECODE
INPUT POWER
+5V
V
CC
BATT
ON
V
OUT
A0–A15
I/O LINE
NMI
RESET
µ
P
ADM691A
ADM693A
ADM800L
ADM800M
RAM Write Protection
The CE
RAM.
threshold. If V
high, independent of the logic level at
line drives the Chip Select inputs of the CMOS
OUT
CE
follows CEIN as long as VCC is above the reset
OUT
falls below the reset threshold, CE
CC
CEIN. This prevents the
OUT
goes
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power interruptions. The
LOW LINE output goes low when VCC falls
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are unconnected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typically restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (
dog timer is not serviced within its timeout period. Once
WDO) goes low if the watch-
WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI unconnected. OSC IN and OSC SEL also allow other watchdog timing options.
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The
RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector
RESET bus or directly drive a
CMOS gate without an external pullup resistor.
Figure 24. Typical Application Circuit
REV. 0
–11–
ADM691A/ADM693A/ADM800L/M
16 9
8
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.0118 (0.30)
0.0040 (0.10)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
16-Lead Wide SOIC
0.4133 (10.50)
0.3977 (10.00)
16 9
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
9
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
(R-16W)
0.2992 (7.60)
0.2914 (7.40)
81
0.1043 (2.65)
0.0926 (2.35)
SEATING
PLANE
0.130
(3.30)
MIN
SEATING
PLANE
0.4193 (10.65)
0.3937 (10.00)
0.0125 (0.32)
0.0091 (0.23)
0.325 (8.25)
0.300 (7.62)
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
8°
0°
0.0157 (0.40)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.1574 (4.00)
0.1497 (5.80)
0.0098 (0.25)
x 45°
0.0040 (0.10)
SEATING
PLANE
16-Lead TSSOP
(RU-16)
16-Lead Narrow SOIC
(R-16N)
0.3937 (10.00)
0.3859 (9.80)
16 9
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.2550 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
C2198–12–10/96
x 45°
–12–
PRINTED IN U.S.A.
REV. 0
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