Low Cost Microprocessor
www.BDTIC.com/ADI
FEATURES
Guaranteed
190 μA quiescent current
Precision supply voltage monitor
4.65 V (ADM705/ADM707)
4.40 V (ADM706/ADM708)
200 ms reset pulse width
Debounced TTL/CMOS manual reset input (
Independent watchdog timer (ADM705/ADM706)
1.60 sec timeout (ADM705/ADM706)
Active high reset output (ADM707/ADM708)
Voltage monitor for power-fail or low battery warning
Superior upgrade for MAX705 to MAX708
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Critical microprocessor supply monitoring
valid with VCC = 1 V
RESET
MR
)
Supervisory Circuits
ADM705/ADM706/ADM707/ADM708
FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
INPUT (WDI)
V
POWER-FAIL
INPUT (PFI)
V
POWER-FAIL
INPUT (PFI)
WATCHDOG
TRANSITION
DETECTOR
V
CC
250μA
MR
CC
4.65V*
1.25V
*
VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM 706)
Figure 1. ADM705/ADM706
V
CC
250μA
MR
CC
4.65V*
1.25V
WATCHDOG
TIMER
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
ADM705/
ADM706
RESET
GENERATOR
ADM707/
ADM708
WATCHDOG
OUTPUT (WDO)
RESET
POWER-FAIL
OUTPUT (PFO)
RESET
RESET
POWER-FAIL
OUTPUT (PFO)
00088-001
GENERAL DESCRIPTION
The ADM705/ADM706/ADM707/ADM708 microprocessor
supervisory circuits are suitable for monitoring 5 V power
supplies/batteries and can also monitor microprocessor activity.
The ADM705/ADM706 provide power-supply monitoring
circuitry that generate a reset output during power-up, powerdown, and brownout conditions. The reset output remains
operational with V
monitoring circuitry is also provided. This is activated if the
watchdog input has not been toggled within 1.60 seconds.
In addition, there is a 1.25 V threshold detector to warn of
power-failures, to detect low battery conditions, or to monitor an
additional power supply. An active low, debounced manual reset
MR
input (
) is also included.
as low as 1 V. Independent watchdog
CC
* VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
Figure 2. ADM707/ADM708
The ADM705 and ADM706 are identical except for the reset
threshold monitor levels, which are 4.65 V and 4.40 V, respectively.
The ADM707 and ADM708 provide a similar functionality to
the ADM705 and ADM706 and only differ in that a watchdog
timer function is not available. Instead, an active high reset
output (RESET) is available as well as the active low reset output
RESET
(
). The ADM707 and ADM708 are identical except for
the reset threshold monitor levels, which are 4.65 V and 4.40 V,
respectively.
All parts are available in narrow 8-lead PDIP and 8-lead SOIC
packages.
00088-002
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Circuit Information .......................................................................... 8
REVISION HISTORY
3/08—Rev. F to Rev. G
Changes to Applications .................................................................. 1
Changes to Table 2 ............................................................................ 4
Changes to Figure 9 .......................................................................... 6
Changes to Figure 10, Figure 11, and Figure 12 ........................... 7
Changes to Figure 14 ........................................................................ 8
Changes to Ordering Guide .......................................................... 12
2/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Watchdog Timeout Period .......................................... 3
Replaced Pin Configurations and Function Descriptions
Section ................................................................................................ 5
7/06—Rev. D to Rev. E
Added RM-8 (MSOP) Package ......................................... Universal
Changes to Table 2 ............................................................................ 4
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
Power-Fail
Manual Reset ..................................................................................8
Watchdog Timer (ADM705/ADM706) .....................................8
Power-Fail Comparator ................................................................8
Va l id
Applications Information .............................................................. 10
Monitoring Additional Supply Levels ...................................... 10
Microprocessor with Bidirectional RESET ............................. 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 12
11/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Deleted Figure 2 ................................................................................. 4
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
8/02—Rev. B to Rev. C
Removed RM-8 (μSOIC) Package .................................... Universal
Updated N-8 and R-8 Packages ....................................................... 8
RESET
Output ...........................................................8
RESET
Below 1 V VCC ........................................................9
Rev. G | Page 2 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
SPECIFICATIONS
VCC = 4.75 V to 5.5 V, TA = T
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
VCC Operating Voltage Range 1.0
Supply Current
LOGIC OUTPUT
Reset Threshold 4.5 4.65 4.75 V ADM705/ADM707
Reset Threshold Hysteresis
RESET PULSE WIDTH 160 200 280 ms
RESET OUTPUT VOLTAGE
RESET OUTPUT VOLTAGE VCC − 1.5
WATCHDOG TIMEOUT PERIOD (tWD) 1.00 1.60 2.25 sec VIL = 0.4 V, VIH = VCC × 0.8, WDI = VCC
WDI Pulse Width (t
WATCHDOG INPUT
WDI Input Threshold
Logic Low
Logic High 3.5
WDI Input Current
) 50
WP
WDO OUTPUT VOLTAGE
MANUAL RESET INPUT
MR Pull-Up Current
MR Pulse Width
MR INPUT THRESHOLD
Logic Low
Logic High
MR TO RESET OUTPUT DELAY
POWER-FAIL INPUT
PFI Input Threshold 1.2 1.25 1.3 V
PFI Input Current −25 +0.01 +25 nA
PFO OUTPUT VOLTAGE
MIN
to T
, unless otherwise noted.
MAX
4.25 4.40 4.50 V ADM706/ADM708
VCC − 1.5
−150 −50
VCC − 1.5
100 250 600 μA
150
2.0
V
− 1.5
CC
190 250 μA
40
5.5 V
mV
0.4 V I
0.3 V VCC = 1 V, I
0.3 V VCC = 1.2 V, I
0.4 V ADM707/ADM708, I
V I
V ADM707/ADM708, I
ns
SOURCE
= 3.2 mA
SINK
= 800 μA
0.8 V
50 150 μA WDI = 0 V
0.4 V I
0.8 V
250 ns
V
μA WDI = 0 V
V I
ns
V
SOURCE
= 1.2 mA
SINK
= 0 V
MR
= 800 μA
0.4 V I
V I
= 800 μA
SOURCE
= 3.2 mA
SINK
= 50 μA
SINK
SINK
= 100 μA
SOURCE
SINK
= 800 μA
= 1.2 mA
Rev. G | Page 3 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VCC −0.3 V to +6 V
All Other Inputs −0.3 V to VCC + 0.3 V
Input Current
VCC 20 mA
GND 20 mA
Digital Output Current 20 mA
Power Dissipation, N-8 PDIP 727 mW
θJA Thermal Impedance 135°C/W
Power Dissipation, R-8 SOIC 470 mW
θJA Thermal Impedance 110°C/W
Power Dissipation, RM-8 MSOP 900 mW
θJA Thermal Impedance 206°C/W
Operating Temperature Range
Industrial (Version A) −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Storage Temperature Range −65°C to +150°C
ESD Rating >4.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. G | Page 4 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MR
V
GND
PFI
CC
1
ADM705/
2
ADM706
3
TOP VIEW
(Not to Scale)
4
8
7
6
5
WDO
RESET
WDI
PFO
Figure 3. ADM705/ADM706 PDIP/SOIC
Pin Configuration
1
MR
ADM707/
2
V
CC
ADM708
3
GND
00088-003
TOP VIEW
(Not to Scale)
4
PFI
NC = NO CONNECT
Figure 4. ADM707/ADM708 PDIP/SOIC
Pin Configuration
8
7
6
5
RESET
RESET
NC
PFO
00088-004
Table 3. Pin Function Descriptions
Pin Number
Mnemonic
MR
ADM705/
ADM706
(PDIP, SOIC)
1 1 3
ADM707/
ADM708
(PDIP, SOIC)
ADM708
(MSOP)
Description
Manual Reset Input. When this pin is taken below 0.8 V, a reset is generated.
MR
can be driven from TTL, CMOS logic, or from a manual reset switch as it is
internally debounced. An internal 250 μA pull-up current holds the input high
when floating.
VCC 2 2 4 5 V Power Supply Input.
GND 3 3 5 0 V Ground Reference for All Signals.
PFI 4 4 6
PFO
5 5 7
Power-Fail Input. PFI is the noninverting input to the power-fail comparator.
When PFI is less than 1.25 V, PFO
to GND or V
.
CC
goes low. If unused, PFI should be connected
Power-Fail Output. PFO is the output from the power-fail comparator. It goes
low when PFI is less than 1.25 V.
WDI 6 N/A N/A
Watchdog Input. WDI is a three-level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output (WDO)
goes low. The timer resets with each transition at the WDI input. Either a highto-low or a low-to-high transition clears the counter. The internal timer is also
cleared whenever reset is asserted. The watchdog timer is disabled when WDI
is left floating or connected to a three-state buffer.
NC N/A 6 8 No Connect.
RESET
7 7 1
Logic Output. RESET
gered either by V
CC
goes low for 200 ms when triggered. It can be trig-
being below the reset threshold or by a low signal on the
manual reset input (MR). RESET remains low whenever VCC is below the reset
threshold (4.65 V in ADM705/ADM707, 4.40 V in ADM706/ADM708). It remains
low for 200 ms after V
goes above the reset threshold or MR goes from low to
CC
high. A watchdog timeout does not trigger RESET
WDO
8 N/A N/A
Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO
also goes low during low line conditions. Whenever V
goes low if the internal WDO remains low. As soon as VCC goes
goes high.
RESET N/A 8 2
threshold, WDO
above the reset threshold, WDO
Logic Output. RESET is an active high output suitable for systems that use
active high reset logic. It is the inverse of RESET
RESET
RESET
MR
V
CC
1
ADM708
2
3
TOP VIEW
(Not to S cale)
4
NC = NO CONNECT
8
NC
PFO
7
6
PFI
5
GND
Figure 5. ADM708 MSOP
Pin Configuration
unless WDO is connected to MR.
is below the reset
CC
.
00088-005
Rev. G | Page 5 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 5V
T
= 25°C
4.50VA1
100
V
CC
90
1.3V
PFI
5V
A
1.2V
PFO
10
0%
RESET
V
RESET
CC
1V
Figure 6.
100
90
10
0%
1V
1V
RESET
Output Voltage vs. Supply Voltage
4.50VA1
1V
500msH
500msH
O
O
Figure 7. ADM707/ADM708 RESET Output Voltage vs. Supply Voltage
0V
00088-014
00088-012
500ns/DIV
Figure 8. PFI Comparator Assertion Response Time
VCC = 5V
T
= 25°C
A
1.3V
1.2V
PFO
0V
00088-013
500ns/DIV
PFI
4.4V
00088-015
Figure 9. PFI Comparator Deassertion Response Time
Rev. G | Page 6 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
5V
0V
5V
RESET
VCC = V
TA = 25°C
VCC = V
TA = 25°C
RT
RESET
RT
Figure 10.
100ns/DIV
RESET
, RESET Assertion
RESET
RESET
5V
0V
00088-016
5V
V
CC
5V
RESET
2μs/DIV
Figure 12. ADM705/ADM707
TA = 25°C
RESET
Response Time
4V
00088-018
0V
5V
0V
100ns/DIV
Figure 11.
RESET
, RESET Deassertion
0V
00088-017
Rev. G | Page 7 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
CIRCUIT INFORMATION
POWER-FAIL RESET OUTPUT
RESET
is an active low output that provides a reset signal to
the microprocessor whenever the V
threshold. An internal timer holds
the voltage on V
rises above the threshold. This functions as a
CC
input is below the reset
CC
RESET
low for 200 ms after
power-on reset signal for the microprocessor. It allows time for
both the power supply and the microprocessor to stabilize after
power-up. The
(low) with V
RESET
output is guaranteed to remain valid
as low as 1 V. This ensures that the micropro-
CC
cessor is held in a stable shutdown condition as the power
supply voltage ramps up.
In addition to
RESET
, an active high RESET output is also
available on the ADM707/ADM708. This is the complement
RESET
of
and is useful for processors requiring an active high
reset signal.
MANUAL RESET
The manual reset input (MR) allows other reset sources, such
as a manual reset switch, to generate a processor reset. The
input is effectively debounced by the timeout period (200 ms
typical). The
MR
input is TTL-/CMOS-compatible, so it can
also be driven by any logic reset output.
V
RESET
MR
WDO
CC
V
RT
Figure 13.
V
RT
RESET
t
RS
, MR, and
WDO
MR EXTERNALLY
DRIVEN LOW
Timing
t
RS
WATCHDOG TIMER (ADM705/ADM706)
The watchdog timer circuit can be used to monitor the activity of
the microprocessor to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the watchdog input (WDI) line. If this line is not toggled within the timeout
period (1.60 sec), then the watchdog output (
WDO
The
can be connected to a nonmaskable interrupt (NMI)
on the processor; therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine should then
be used to rectify the problem.
RESET
If a
signal is required when a timeout occurs, the
should be connected to the manual reset input (
The watchdog timer is cleared by either a high-to-low or a lowto-high transition on WDI. It is also cleared by
low; therefore, the watchdog timeout period begins after
goes high.
WDO
MR
RESET
) goes low.
WDO
).
going
RESET
When V
falls below the reset threshold,
CC
whether or not the watchdog timer has timed out. Normally, this
generates an interrupt, but it is overridden by
The watchdog monitor can be deactivated by floating the
watchdog input (WDI). The
WDO
line output, because it goes low only when V
reset threshold.
t
WDI
WDO
RESET
WP
t
WD
RESET EXTERNALLY
TRIGGERED BY MR
Figure 14. Watchdog Timing
POWER-FAIL COMPARATOR
The power-fail comparator is an independent comparator that
can be used to monitor the input power supply. The comparator’s
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input can be used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output (
indicating a power failure. For early warning of power failure,
the comparator can be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network.
PFO
The
a shutdown procedure is implemented before power is lost.
00088-007
output can be used to interrupt the processor so that
INPUT
POWER
R1
POWER-FAIL
R2
INPUT
Figure 15. Power-Fail Comparator
1.25V
PFI
ADM705/ADM706/
ADM707/ADM708
WDO
is forced low
RESET
going low.
can then be used as a low
falls below the
CC
t
WD
PFO
PFO
t
WD
t
RS
) goes low,
POWER-FAIL
OUTPUT
00088-009
00088-008
Rev. G | Page 8 of 12
ADM705/ADM706/ADM707/ADM708
V
www.BDTIC.com/ADI
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis can be added to
the power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the
PFO
output and the PFI input, as shown in
. Figure 16
7V TO 15
INPUT
POWER
ADP3367
R1
R2
5V
PFO
5V
V
CC
1.25V
–
PFO
PFI
ADM705/ADM706/
ADM707/ADM708
+
R3
TO
MICROPROCESSOR
NMI
VALID RESET BELOW 1 V VCC
The ADM705/ADM706/ADM707/ADM708 are guaranteed to
provide a valid reset level with V
Performance Characteristics section). As V
the internal transistor does not have sufficient drive to hold the
RESET
voltage
externally, as shown in , to hold the line low if
at 0 V. A pull-down resistor can be connected
Figure 17
required.
ADM705/ADM706/
ADM707/ADM708
Figure 17.
as low as 1 V (see the Ty pi ca l
CC
drops below 1 V,
CC
RESET
GND
RESET
Valid Below 1 V
R1
00088-011
0V
0V
Figure 16. Adding Hysteresis to the Power-Fail Comparator
PFO
When
is low, Resistor R3 sinks current from the summing
junction at the PFI pin. When
V
V
H
L
V
IN
PFO
is high, Resistor R3 sources
00088-010
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity can be
achieved by connecting a capacitor between PFI and GND. The
equations used to calculate the hysteresis are as follows:
+
R3R2
⎡
⎛
125.1
V
H
L
V
MID
+=
⎜
⎢
⎣
25.1
25.1
=
×
⎝
25.1
⎛
R1V
⎜
R2
⎝
+
R2R1
⎛
⎜
R2
⎝
⎤
⎞
R1
⎟
⎥
R3R2
⎠
⎦
25.1
−
V
CC
−+=
⎞
⎟
⎠
R3
⎞
⎟
⎠
Rev. G | Page 9 of 12
ADM705/ADM706/ADM707/ADM708
V
V
V
V
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
A typical application circuit is shown in Figure 18. The
unregulated dc input supply is monitored using PFI via the
resistive divider network. Resistor R1 and Resistor R2 should
be selected so that when the supply voltage drops below the
desired level (such as 8 V), the voltage on PFI drops below
the 1.25 V threshold, thereby generating an interrupt to the
microprocessor. Monitoring the preregulator input provides
additional time to execute an orderly shutdown procedure
before power is lost.
7V TO 15V
INPUT POWER
ADP3367
R1
R2
Figure 18. Typical Application Circuit
5
V
CC
1.25V
–
PFI
ADM705/ADM706/
ADM707/ADM708
+
PFO
RESET
MICROPROCESSOR
Microprocessor activity is monitored using WDI. This is driven
using an output line from the processor. The software routines
should toggle this line at least once every 1.60 seconds. If a
problem occurs and this line is not toggled,
WDO
goes low and
a nonmaskable interrupt is generated. This interrupt routine can be
used to clear the problem.
If, in the event of inactivity on the WDI line, a system reset
is required,
WDO
should be connected to MR, as shown in
Figure 19.
ADM705/
ADM706
MR
RESET
WDO
GND
Figure 19.
WDI
MICROPROCESSOR
RESET
From
RESET
I/O LINE
WDO
00088-021
00088-020
MONITORING ADDITIONAL SUPPLY LEVELS
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 20. The two sensing resistors,
R1 and R2, are selected so that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply.
connected to
MR
so that a reset is generated when the supply
PFO
can be
drops out of tolerance. In this case, if either supply drops out
of tolerance, a reset is generated.
X
R1
R2
Figure 20. Monitoring 5 V and an Additional Supply, V
5
V
ADM705/
ADM706
PFI
MR
GND
CC
RESET
PFO
RESET
MICROPROCESSOR
00088-022
X
MICROPROCESSOR WITH BIDIRECTIONAL RESET
To prevent contention for microprocessors with a bidirectional
reset line, a current limiting resistor should be inserted between
the ADM70x
RESET
output pin and the microprocessor
pin. This limits the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 kΩ. If the reset
output is required for other uses, it should be buffered, as shown in
Figure 21.
5
V
CC
ADM70x
RESET
GND
Figure 21. Bidirectional Input/Output
BUFFERED
RESET
MICROPROCESSOR
RESET
GND
RESET
RESET
00088-023
Rev. G | Page 10 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
PIN 1
0.100 (2.54)
0.210
(5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 22. 8-Lead Plastic Dual-in-Line Package [PDIP]
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
4
BSC
0.005 (0.13)
MIN
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
GAUGE
PLANE
MAX
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
85
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2440)
5.80 (0.2284)
41
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Figure 23. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
× 45°
3.20
3.00
2.80
8
5
4
SEATING
PLANE
5.15
4.90
4.65
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
3.20
3.00
1
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
0.15
0.38
0.00
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 24. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. G | Page 11 of 12
ADM705/ADM706/ADM707/ADM708
www.BDTIC.com/ADI
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADM705AN −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM705ANZ
ADM705AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM705AR–REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM705AR–REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM705ARZ
ADM705ARZ–REEL
ADM705ARZ–REEL7
ADM706AN −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM706ANZ1 −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM706AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM706AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM706AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM706ARZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM706ARZ-REEL1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM706ARZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM707AN −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM707ANZ1 −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM707AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM707AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM707ARZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM707ARZ-REEL1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM708AN −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM708ANZ1 −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
ADM708AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM708AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM708ARZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM708ARZ-REEL1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM708ARM −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 AD70, M8
ADM708ARM-REEL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 AD70, M8
ADM708ARMZ
ADM708ARMZ-REEL
1
Z = RoHS Compliant Part.
1
1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
1
−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8F
−40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
1
−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8F
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00088-0-3/08(G)
Rev. G | Page 12 of 12
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